SN74ACT ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

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1 dependent Asynchronous puts and puts ow-power Advanced CMOS Technology Bidirectional Dual 024 by 9 Bits Programmable Almost-Full/Almost-Empty Flag Empty, Full, and alf-full Flags SN74ACT2235 ASYNCRONOUS BIDIRECTIONA FIRST-IN, FIRST-OUT MEMORY Access Times of 25 ns With a 50-pF oad Data Rates up to 50 Mz Fall-Through Times of 22 ns Maximum igh put Drive for Direct Bus terface Package Options clude 44-Pin Plastic eaded Chip Carriers (FN) and 64-Pin Thin Quad Flat (PAG, PM) Packages description A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ACT2235 is arranged as two bit FIFOs for high speed and fast access times. It processes data at rates up to 50 Mz, with access times of 25 ns in a bit-parallel format. The SN74ACT2235 consists of bus-transceiver circuits, two bit FIFOs, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable ( and ) inputs are provided to control the transceiver functions. The select-control ( and ) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 2 shows the eight fundamental bus-management functions that can be performed with the SN74ACT2235. For more information on this device family, see the application report, K 9 2 Asynchronous FIFO SN74ACT2235, literature number SCAA00. The SN74ACT2235 is characterized for operation from 0 C to 70 C. FN PACKAGE (TOP VIEW) A2 A A0 B0 B A3 A4 A5 A6 A7 A8 AF/AEA FA DCKA B2 B3 B4 B5 B6 B7 B8 AF/AEB FB FUA UNCKB EMPTYB DAF RSTA RSTB DBF EMPTYA UNCKA FUB DCKB Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas struments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas struments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2003, Texas struments corporated POST OFFICE BOX DAAS, TEXAS 75265

2 ASYNCRONOUS BIDIRECTIONA FIRST-IN, FIRST-OUT MEMORY PAG OR PM PACKAGE (TOP VIEW) A2 A A0 B0 B B2 A3 A4 A5 A6 A7 A8 AF/AEA FA NC B3 B4 B5 B6 B7 B8 AF/AEB FB NC DCKA FUA UNCKB EMPTYB DAF RSTA NC RSTB DBF EMPTYA NC UNCKA FUB DCKB NC NC No internal connection 2 POST OFFICE BOX DAAS, TEXAS 75265

3 logic symbol SN74ACT2235 ASYNCRONOUS BIDIRECTIONA FIRST-IN, FIRST-OUT MEMORY RSTA DAF DCKA UNCKA FUA EMPTYA AF/AEA FA EN EN2 Reset A DEF A FAG DCKA UNCKA FUA MODE Φ FIFO SN74ACT2235 RESET B DEF B FAG DCKB UNCKB FU B EMPTYA EMPTYB AMOST-FU/ AMOST-FU/ AMOST-EMPTY A AMOST-EMPTY A AF-FU A AF-FU B RSTB DBF DCKB UNCKB FUB EMPTYB AF/AEB FB A0 A A2 A3 A4 A5 A6 A7 A A Data B Data B0 B B2 B3 B4 B5 B6 B7 B8 This symbol is in accordance with ANSI/IEEE Std and IEC Publication Pin numbers shown are for the FN package. POST OFFICE BOX DAAS, TEXAS

4 ASYNCRONOUS BIDIRECTIONA FIRST-IN, FIRST-OUT MEMORY logic diagram (positive logic) FB AF/AEB EMPTYB UNCKB Φ RSTB DBF FUB DCKB Q D B0 One of Nine Channels To Other Channels RSTA DAF FUA DCKA Φ FA AF/AEA EMPTYA UNCKA A0 D Q One of Nine Channels To Other Channels 4 POST OFFICE BOX DAAS, TEXAS 75265

5 TERMINA NAME AF/AEA AF/AEB A0 A8 B0 B8 DAF DBF EMPTYA EMPTYB FUA FUB FA FB DCKA DCKB RSTA RSTB UNCKA UNCKB NO , , I/O O I/O I/O Terminals listed are for the FN package. I O O O I I I I I SN74ACT2235 ASYNCRONOUS BIDIRECTIONA FIRST-IN, FIRST-OUT MEMORY Terminal Functions DESCRIPTION Almost full/almost empty flags. The almost-full/almost-empty A flag (AF/AEA) is defined by the almost-full/almost-empty offset value for (X). AF/AEA is high when contains X or fewer words or 024 X words. AF/AEA is low when contains between (X + ) or (023 X) words. The operation of the almost-full/almost-empty B flag (AF/AEB) is the same as AF/AEA for. A-data inputs and outputs B-data inputs and outputs Define-flag inputs. The high-to-low transition of DAF stores the binary value on A0 A8 as the almost-full/almost-empty offset value for (X). The high-to-low transition of DBF stores the binary value of B0 B8 as the almost-full/almost-empty offset value for (Y). Empty flags. EMPTYA and EMPTYB are low when their corresponding memories are empty and high when they are not empty. Full flags. FUA and FUB are low when their corresponding memories are full and high when they are not full. alf-full flags. FA and FB are high when their corresponding memories contain 52 or more words and low when they contain 5 or fewer words. oad clocks. Data on A0 A8 is written into on a low-to-high transition of DCKA. Data on B0 B8 is written into on a low-to-high transition of DCKB. When the FIFOs are full, DCKA and DCKB have no effect on the data residing in memory. put enables., control the transceiver functions. When is low, A0 A8 are in the high-impedance state. When is low, B0 B8 are in the high-impedance state. Reset. A reset is accomplished in each direction by taking RSTA and RSTB low. This sets EMPTYA, EMPTYB, FUA, FUB, and AF/AEB high. Both FIFOs must be reset upon power up. Select-control inputs. and select whether real-time or stored data is transferred. A low level selects real-time data and a high level selects stored data. Eight fundamental bus-management functions can be performed as shown in Figure 2. Unload clocks. Data in is read to B0 B8 on a low-to-high transition of UNCKA. Data in is read to A0 A8 on a low-to-high transition of UNCKB. When the FIFOs are empty, UNCKA and UNCKB have no effect on data residing in memory. programming procedure for AF/AEA The almost-full/almost-empty flags (AF/AEA, AF/AEB) are programmed during each reset cycle. The almost-full/almost-empty offset value for (X) and for (Y) is either a user-defined value or the default values of X = 256 and Y = 256. Below are instructions to program AF/AEA using both methods. AF/AEB is programmed in the same manner for. user-defined X Take DAF from high to low. This stores A0 A8 as X. If RSTA is not already low, take RSTA low. With DAF held low, take RSTA high. This defines AF/AEA using X. To retain the current offset for the next reset, keep DAF low. default X To redefine AF/AE using the default value of X = 256, hold DAF high during the reset cycle.figure POST OFFICE BOX DAAS, TEXAS

6 ASYNCRONOUS BIDIRECTIONA FIRST-IN, FIRST-OUT MEMORY RSTA Don t Care DAF DCKA X Don t Care A0 A8 UNCKA valid valid 2 Q0 Q8 EMPTYA FUA FA AF/AEA Set Flag to Empty + X/Full X oad X into Flag Register Full 256 Full 256 alf Full Empty Empty Empty Full alf Full Set Flag to Empty + 256/ Full 256 (default) (0 X 5) Operation of is identical to that of. ast valid data stays on outputs when FIFO goes empty due to a read. Figure. Timing Diagram for 6 POST OFFICE BOX DAAS, TEXAS 75265

7 ASYNCRONOUS BIDIRECTIONA FIRST-IN, FIRST-OUT MEMORY Bus A Bus B Bus A Bus B X X X Bus A Bus B Bus A Bus B X Bus A Bus B Bus A Bus B X Bus A Bus B Bus A Bus B X Figure 2. Bus-Management Functions POST OFFICE BOX DAAS, TEXAS

8 ASYNCRONOUS BIDIRECTIONA FIRST-IN, FIRST-OUT MEMORY SEECT-MODE CONTRO CONTRO OPERATION A BUS B BUS Real-time B to A bus Real-time A to B bus to A bus Real-time A to B bus Real-time B to A bus to B bus to A bus to B bus OUTPUT-ENABE CONTRO CONTRO OPERATION A BUS B BUS A bus enabled B bus enabled A bus enabled Isolation/input to B bus Isolation/input to A bus B bus enabled Isolation/input to A bus Isolation/input to B bus Figure 2. Bus-Management Functions (Continued) absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V to 7 V put voltage range, V I : Control inputs V to 7 V I/O ports V to 5.5 V Voltage range applied to a disabled 3-state output V Package thermal impedance, θ JA (see Note ): FN package C/W PAG package C/W PM package C/W Storage temperature range, T stg C to 50 C Maximum junction temperature, T J C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE : The package thermal impedance is calculated in accordance with JESD 5. recommended operating conditions ACT ACT ACT ACT UNIT MIN MAX MIN MAX MIN MAX MIN MAX VCC Supply voltage V VI igh-level input voltage V VI ow-level input voltage V IO IO igh-level output current ow-level output current A or B ports Status flags A or B ports Status flags TA Operating free-air temperature C ma ma 8 POST OFFICE BOX DAAS, TEXAS 75265

9 ASYNCRONOUS BIDIRECTIONA FIRST-IN, FIRST-OUT MEMORY electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO VCC = 4.5 V, IO = 8 ma 2.4 V VO Flags VCC = 4.5 V, IO = 8 ma 0.5 I/O ports VCC = 4.5 V, IO = 6 ma 0.5 II VCC = 5.5 V, VI = VCC or 0 ±5 µa IOZ VCC = 5.5 V, VO = VCC or 0 ±5 µa ICC VI = VCC 0.2 V or µa ICC VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or ma Ci VI = 0, f = Mz 4 pf Co VO = 0, f = Mz 8 pf All typical values are at VCC = 5 V, TA = 25 C. ICC is tested with outputs open. This is the supply current when each input is at one of the specified TT voltage levels, rather than 0 V or VCC. V timing requirements over recommended operating conditions (unless otherwise noted) (see Figure 3) fclock Clock frequency tw tsu Pulse duration Setup time ACT ACT ACT ACT MIN MAX MIN MAX MIN MAX MIN MAX DCKA or DCKB UNCKA or UNCKB RSTA or RSTB low DCKA or DCKB low DCKA or DCKB high UNCKA or UNCKB low UNCKA or UNCKB high DAF or DBF high Data before DCKA or DCKB Define AF/AE: D0 D8 before DAF or DBF Define AF/AE: DAF or DBF before RSTA or RSTB Define AF/AE (default): DAF or DBF high before RSTA or RSTB RSTA or RSTB inactive (high) before DCKA or DCKB Data after DCKA or DCKB 2 2 Define AF/AE: D0 D8 after DAF or DBF th old time Define AF/AE: DAF or DBF low after RSTA or RSTB Define AF/AE (default): DAF or DBF high after RSTA or RSTB UNIT Mz ns ns ns POST OFFICE BOX DAAS, TEXAS

10 ASYNCRONOUS BIDIRECTIONA FIRST-IN, FIRST-OUT MEMORY switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C = 50 pf (unless otherwise noted) (see Figure 3) PARAMETER fmax tpd tp tp FROM TO ACT ACT ACT ACT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX MIN MAX DCK UNCK DCK, DCKB UNCKA, UNCKB DCK, DCKB UNCKA, UNCKB RSTA, RSTB DCK, DCKB UNCKA, UNCKB BorA EMPTYA, EMPTYB EMPTYA, EMPTYB UNIT Mz ns ns FUA, FUB FUA, FUB FUA, FUB tp RSTA, RSTB AF/AEA, AF/AEB DCK, FA, FB DCKB tp tpd UNCKA, UNCKB RSTA, RSTB or A or B DCK, DCKB UNCKA, UNCKB FA, FB BorA AF/AEA, AF/AEB ns ten or A or B ns tdis or A or B ns All typical values are at VCC = 5 V, TA = 25 C. These parameters are measured with the internal output state of the storage register opposite that of the bus input. operating characteristics, = 5 V, T A = 25 C ns ns ns Cpd PARAMETER TEST CONDITIONS TYP UNIT puts enabled 7 Power dissipation capacitance per K bits C =50pF pf, f=5mz pf puts disabled 57 0 POST OFFICE BOX DAAS, TEXAS 75265

11 ASYNCRONOUS BIDIRECTIONA FIRST-IN, FIRST-OUT MEMORY PARAMETER MEASUREMENT INFORMATION 7 V From put Under Test C = 50 pf (see Note A) S 500 Ω 500 Ω Test Point PARAMETER ten tdis tpd tpz tpz tpz tpz tp tp S Open Closed Open Closed Open Open tw OAD CIRCUIT 3 V put.5 V.5 V Timing put.5 V 3 V 0 V VOTAGE WAVEFORMS PUSE DURATION 0 V tsu th Data put.5 V.5 V VOTAGE WAVEFORMS SETUP AND OD TIMES 3 V 3 V put.5 V.5 V 0 V Control tpz tpz 0 V put.5 V.5 V 3 V 0 V put Waveform S at 7 V.5 V 3.5 V VO V VO tp tp tpz tpz put.5 V.5 V VO VO put Waveform 2 S at Open.5 V VO VO 0.3 V 0 V VOTAGE WAVEFORMS PROPAGATION DEAY TIMES VOTAGE WAVEFORMS ENABE AND DIE TIMES NOTE A: C includes probe and jig capacitance. Figure 3. oad Circuit and Voltage Waveforms POST OFFICE BOX DAAS, TEXAS 75265

12 ASYNCRONOUS BIDIRECTIONA FIRST-IN, FIRST-OUT MEMORY TYPICA CARACTERISTICS t pd Propagation Delay Time ns typ + 8 typ + 6 typ + 4 typ + 2 typ VCC = 5 V TA = 25 C R = 500 Ω PROPAGATION DEAY TIME vs OAD CAPACITANCE Power Dissipation Capacitance pf C pd typ + 2 typ + typ typ typ 2 POWER-DISSIPATION CAPACITANCE vs SUPPY VOTAGE VCC = 5 V fi = 5 Mz TA = 25 C typ C oad Capacitance pf Figure 4 typ VCC Supply Voltage V Figure 5 2 POST OFFICE BOX DAAS, TEXAS 75265

13 MECANICA DATA MPC004A OCTOBER 994 FN (S-PQCC-J**) 20 PIN SOWN PASTIC J-EADED CIP CARRIER Seating Plane (0,0) 3 D D (4,57) MAX 0.20 (3,05) (2,29) (0,5) MIN (0,8) (0,66) D2 / E2 E E D2 / E (,27) (0,20) NOM 0.02 (0,53) 0.03 (0,33) (0,8) M NO. OF PINS ** MIN D/E MAX MIN D / E MAX MIN D2 / E2 MAX (9,78) (0,03) (8,89) (9,04) 0.4 (3,58) 0.69 (4,29) (2,32) (2,57) (,43) (,58) 0.9 (4,85) 0.29 (5,56) (7,40) (7,65) (6,5) (6,66) 0.29 (7,39) 0.39 (8,0) (9,94) (20,9) (9,05) (9,20) 0.34 (8,66) (9,37) (25,02) (25,27) (24,3) (24,33) 0.44 (,20) (,9) (30,0).95 (30,35).50 (29,2).58 (29,4) 0.54 (3,74) (4,45) / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-08 POST OFFICE BOX DAAS, TEXAS 75265

14 MECANICA DATA MTQF006A JANUARY 995 REVISED DECEMBER 996 PAG (S-PQFP-G64) PASTIC QUAD FATPACK 0,27 0,50 0,08 M 0, ,3 NOM 6 7,50 TYP 0,20 SQ 9,80 2,20,80 SQ 0,05 MIN 0,25 Gage Plane 0 7,05 0,95 0,75 0,45 Seating Plane,20 MAX 0, / C /96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX DAAS, TEXAS 75265

15 MECANICA DATA MTQF008A JANUARY 995 REVISED DECEMBER 996 PM (S-PQFP-G64) PASTIC QUAD FATPACK 0,27 0,50 0,08 M 0, ,3 NOM 6 7,50 TYP 0,20 SQ 9,80 2,20,80 SQ 0,05 MIN 0,25 Gage Plane 0 7,45,35 0,75 0,45 Seating Plane,60 MAX 0, / C /96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 D. May also be thermally enhanced plastic with leads connected to the die pads. POST OFFICE BOX DAAS, TEXAS 75265

16 IMPORTANT NOTICE Texas struments corporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. formation published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas struments Post Office Box Dallas, Texas Copyright 2003, Texas struments corporated

SN74ABT STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SN74ABT STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY Member of the Texas struments Widebus Family Advanced BiCMOS Technology dependent Asynchronous puts and puts Two Separate 512 18 FIFOs Buffering Data in Opposite Directions Programmable Almost-Full/Almost-Empty