TPS7201Q, TPS7225Q, TPS7230Q TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS

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1 Available in 5-, 4.85-, 3.3-, 3.-, and 2.5- Fixed-Output and Adjustable ersions Dropout oltage <85 m Max at I O = 1 ma (TPS725) Low Quiescent Current, Independent of Load, 18 µa Typ 8-Pin SOIC and 8-Pin TSSOP Package Output Regulated to ±2% Over Full Operating Range for Fixed-Output ersions Extremely Low Sleep-State Current,.5 µa Max Power-Good (PG) Status Output description The TPS72xx family of low-dropout (LDO) voltage regulators offers the benefits of low-dropout voltage, micropower operation, and miniaturized packaging. These regulators feature extremely low dropout voltages and quiescent currents compared to conventional LDO regulators. Offered in small-outline integrated-circuit (SOIC) packages and 8-terminal thin shrink small-outline (TSSOP), the TPS72xx series devices are ideal for cost-sensitive designs and for designs where board space is at a premium. A combination of new circuit design and process innovation has enabled the usual pnp pass transistor to be replaced by a PMOS device. Because the PMOS pass element behaves as a low-value resistor, the dropout voltage is very low maximum of 85 m at 1 ma of load current (TPS725) and is directly proportional to the load current (see Figure 1). Since the PMOS pass Dropout oltage m DO element is a voltage-driven device, the quiescent current is very low (3 µa maximum) and is stable over the entire range of output load current ( ma to 25 ma). Intended for use in portable systems such as laptops and cellular phones, the low-dropout voltage and micropower operation result in a significant increase in system battery operating life. The TPS72xx also features a logic-enabled sleep mode to shut down the regulator, reducing quiescent current to.5 µa maximum at T J = 25 C. Other features include a power-good function that reports low output voltage and may be used to implement a power-on reset or a low-battery indicator. The TPS72xx is offered in 2.5-, 3-, 3.3-, 4.85-, and 5- fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 to 9.75 ). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for adjustable version) SENSE /FB RESET/PG GND EN D, P, OR PW PACKAGE (TOP IEW) OUT OUT IN IN SENSE Fixed voltage options only (TPS7225, TPS723, TPS7233, TPS7248, and TPS725) FB Adjustable version only (TPS721) TPS7225 TPS725 TPS723 TPS7233 TPS IO Output Current ma Figure 1. Typical Dropout oltage ersus Output Current Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS

2 TJ OUTPUT OLTAGE () MIN TYP MAX AAILABLE OPTIONS SMALL OUTLINE (D) PACKAGED DEICES PDIP (P) TSSOP (PW) CHIP FORM (Y) TPS725QD TPS725QP TPS725QPWR TPS725Y TPS7248QD TPS7248QP TPS7248QPWR TPS7248Y TPS7233QD TPS7233QP TPS7233QPWR TPS7233Y 55 C to 15 C TPS723QD TPS723QP TPS723QPWR TPS723Y TPS7225QD TPS7225QP TPS7225QPWR TPS7225Y Adjustable TPS721QD TPS721QP TPS721QPWR TPS721Y 1.2 to 9.75 The D package is available taped and reeled. Add R suffix to device type (e.g., TPS725QDR). The PW package is only available left-end taped and reeled. The TPS721Q is programmable using an external resistor divider (see application information). The chip form is tested at 25 C. TPS72xx I.1 µf IN PG IN SENSE OUT EN OUT GND PG 25 kω O CO (see Note A) + 1 µf CSR = 1 Ω TPS7225Q, TPS723Q, TPS7233Q, TPS7248Q, TPS725Q (fixed-voltage options) NOTE A: Capacitor selection is nontrivial. See application information section for details. Figure 2. Typical Application Configuration 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 TPS72xx chip information These chips, when properly assembled, display characteristics similar to the TPS72xxQ. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform. 7 BONDING PAD ASSIGNMENTS (5) (4) (6) IN EN (3) (2) TPS72xx (5) (6) (4) (7) SENSE FB OUT PG (1) (7) GND CHIP THICKNESS: 15 MILS TYPICAL 57 BONDING PADS: 4 4 MILS MINIMUM TJmax = 15 C 1 TOLERANCES ARE ±1%. ALL DIMENSIONS ARE IN MILS. (1) (2) 2 3 (3) Fixed-voltage options only (TPS7225, TPS723, TPS7233, TPS7248, and TPS725) Adjustable version only (TPS721) 69 NOTE A. For most applications, OUT and SENSE should be tied together as close as possible to the device; for other implementations, refer to the SENSE-pin connection discussion in the application information section of this data sheet. functional block diagram IN RESISTOR DIIDER OPTIONS EN _ + PG OUT DEICE TPS721 TPS7225 TPS723 TPS7233 TPS7248 TPS725 R R UNIT Ω kω kω kω kω kω ref = _ GND R1 R2 SENSE /FB Switch positions are shown with EN low (active). For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to the SENSE-pin connection discussion in application information section. NOTE A: Resistors are nominal values only. COMPONENT COUNT MOS transistors Bilpolar transistors Diodes Capacitors Resistors POST OFFICE BOX DALLAS, TEXAS

4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Input voltage range, I, PG, SENSE, EN to 11 Output current, I O A Continuous total power dissipation See Dissipation Rating Tables 1 and 2 Operating virtual junction temperature range, T J C to 15 C Storage temperature range, T stg C to 15 C Lead temperature 1,6 mm (1/16 inch) from case for 1 seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. PACKAGE D P PW DISSIPATION RATING TABLE 1 FREE-AIR TEMPERATURE (see Note 1 and Figure 3) TA 25 C DERATING FACTOR TA = 7 C TA = 85 C TA = 125 C POWER RATING ABOE POWER RATING POWER RATING POWER RATING 725 mw 5.8 mw/ C 464 mw 377 mw 145 mw 1175 mw 8.74 mw/ C 782 mw 65 mw 31 mw 525 mw 4.2 mw/ C 336 mw 273 mw 15 mw PACKAGE D P PW NOTE 1: DISSIPATION RATING TABLE 2 CASE TEMPERATURE (see Note 1 and Figure 4) TC 25 C DERATING FACTOR TC = 7 C TC = 85 C TC = 125 C POWER RATING ABOE TC = 25 C POWER RATING POWER RATING POWER RATING 263 mw 2738 mw 29 mw 16.5 mw/ C 2.49 mw/ C 23.2 mw/ C 132 mw 1816 mw 1856 mw 173 mw 158 mw 158 mw 413 mw 689 mw 58 mw Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum of 15 C. For guidelines on maintaining junction temperature within the recommended operating range, see application information section. P D Maximum Continuous Dissipation mw MAXIMUM CONTINUOUS DISSIPATION FREE-AIR TEMPERATURE P Package RθJA = C/W PW Package RθJA = 238 C/W D Package RθJA = 172 C/W P D Maximum Continuous Dissipation mw MAXIMUM CONTINUOUS DISSIPATION CASE TEMPERATURE P Package RθJC = 48.8 C/W D Package RθJC = 6.6 C/W PW Package RθJC = 43.1 C/W TA Free-Air Temperature C Figure TC Case Temperature C Figure POST OFFICE BOX DALLAS, TEXAS 75265

5 recommended operating conditions MIN MAX UNIT TPS721Q 3 1 TPS7225Q TPS723Q Input voltage, I TPS7233Q TPS7248Q TPS725Q High-level input voltage at EN, IH 2 Low-level input voltage at EN, IL.5 Output current, IO 25 ma Operating virtual junction temperature, TJ C Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To calculate the minimum input voltage for the maximum load current used in a given application, use the following equation: I(min) O(max) DO(max load) Because the TPS721 is programmable, rds(on) should be used to calculate DO before applying the above equation. The equation for calculating DO from rds(on) is given in Note 3 under the TPS721 electrical characteristics table. The minimum value of 3 is the absolute lower limit for the recommended input-voltage range for the TPS721. POST OFFICE BOX DALLAS, TEXAS

6 electrical characteristics, I O = 1 ma, EN =, C O = 4.7 µf (CSR = 1 Ω), SENSE/FB shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS TJ Ground current (active mode) Input current (standby mode) EN = I, 3 I 1 Output current limit threshold O = I =1 Pass-element leakage current in standby mode TPS72xxQ MIN TYP MAX EN.5, = 25 C I O + 1, ma IO 25 ma 4 C to 125 C 325 EN = I, 3 I 1 PG leakage current PG = 1, Normal operation 25 C.5 4 C to 125 C 1 25 C C to 125 C C.5 4 C to 125 C 1 25 C.5 4 C to 125 C.5 Output voltage temperature coefficient 4 C to 125 C ppm/ C Thermal shutdown junction temperature 165 C EN logic high (standby mode) EN logic low (active mode) 3 I 6 6 I 1 3 I 1 4 C to125 C C.5 4 C to 125 C.5 EN hysteresis voltage 25 C 5 m EN input current Minimum I for active pass element I 1 Minimum I for valid PG IPG = 3 µa 25 C C to 125 C C C to 125 C C C to 125 C 1.9 CSR(compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. UNIT µa µa A µa µa µa 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 TPS721Q electrical characteristics, I O = 1 ma, I = 3.5, EN =, C O = 4.7 µf (CSR = 1 Ω), FB shorted to OUT at device leads (unless otherwise noted) PARAMETER TEST CONDITIONS TJ TPS721Q MIN TYP MAX Reference voltage (measured I = 3.5, IO = 1 ma 25 C at FB with OUT connected to FB) Reference voltage temperature coefficient Pass-element series resistance (see Note 3) 3 I 1, See Note 2 5 ma IO 25 ma, UNIT 4 C to 125 C C to 125 C ppm/ C I = 2.4, 5 µa IO 1 ma 25 C 2.1 I = 2.4, 1 ma IO 2 ma 25 C 2.9 I =29 2.9, 5 µa IO 25 ma 25 C C to 125 C 4.5 I = 3.9, 5 µa IO 25 ma 25 C 1 I = 5.9, 5 µa IO 25 ma 25 C.8 I = 3 to 1, 5 µa IO 25 ma, 25 C 23 Input regulation O See Note 2 4 C to 125 C 36 Output regulation Ripple rejection IO = 5 ma to 25 ma, 3 I 1, 25 C See Note 2 4 C to 125 C 36 IO O = 5 µa to 25 ma, 3 I I 1, 25 C See Note 2 4 C to 125 C 43 f = 12 Hz IO =5µA 25 C C to 125 C 32 IO O = 25 ma, 25 C 45 5 See Note 2 4 C to 125 C 3 Output noise spectral density f = 12 Hz 25 C 2 µ/ Hz Output noise voltage 1 Hz f 1 khz, CSR =1Ω Ω CO = 4.7 µf 25 C 235 Ω m m CO = 1 µf 25 C 19 µrms CO = 1 µf 25 C 125 PG trip-threshold voltage FB voltage decreasing from above PG 4 C to 125 C.95 FB(nom) PG hysteresis voltage Measured at FB 25 C 12 m PG output low voltage IPG = 4 µa, I = 2.13 FB input current 25 C C to 125 C.4 25 C C to 125 C 2 2 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. This voltage is not recommended. Output voltage programmed to 2.5 with closed-loop configuration (see application information). NOTES: 2. When I < 2.9 and IO > 1 ma simultaneously, pass element rds(on) increases (see Figure 1) to a point such that the resulting dropout voltage prevents the regulator from maintaining the specified tolerance range. 3. To calculate dropout voltage, use equation: DO = IO rds(on) rds(on) is a function of both output current and input voltage. The parametric table lists rds(on) for I = 2.4, 2.9, 3.9, and 5.9, which corresponds to dropout conditions for programmed output voltages of 2.5, 3, 4, and 6, respectively. For other programmed values, refer to Figures 1 and 11. db na POST OFFICE BOX DALLAS, TEXAS

8 TPS7225Q electrical characteristics, I O = 1 ma, I = 3.5, EN =, C O = 4.7 µf (CSR = 1 Ω), SENSE shorted to OUT (unless otherwise noted) Output voltage PARAMETER TEST CONDITIONS TJ TPS7225Q MIN TYP MAX I = 3.5, IO = 1 ma 25 C I 1, 5 ma IO 25 ma 4 C to 125 C Dropout voltage IO = 25 ma, I = 2.97 Pass-element series resistance UNIT 25 C m 4 C to 125 C 1.1 (2.97 O)/IO, O, I = 2.97, 25 C IO = 25 ma 4 C to 125 C C 9 27 Input regulation I =35to1 3.5, 5 µa IO 25 ma m 4 C to 125 C 33 Output regulation Ripple rejection IO =5mAto25mA ma, IO =5µA to 25 ma, f = 12 Hz I I 1 IO =5µA IO = 25 ma 25 C C to 125 C 6 25 C C to 125 C C C to 125 C C C to 125 C 38 Output noise spectral density f = 12 Hz 25 C 2 µ/ Hz Output noise voltage 1 Hz f 1 khz, CSR = 1 Ω CO = 4.7 µf 25 C 248 Ω m CO = 1 µf 25 C 2 µrms CO = 1 µf 25 C 13 PG trip-threshold voltage O voltage decreasing from above PG 4 C to 125 C.95 O(nom) PG hysteresis voltage 25 C 5 m PG output low voltage IPG =12mA 1.2 ma, I = C C to 125 C.5 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. db 8 POST OFFICE BOX DALLAS, TEXAS 75265

9 TPS723Q electrical characteristics, I O = 1 ma, I = 4, EN =, C O = 4.7 µf (CSR = 1 Ω), SENSE shorted to OUT (unless otherwise noted) Output voltage Dropout voltage PARAMETER TEST CONDITIONS TJ Pass-element series resistance TPS723Q MIN TYP MAX I = 4, IO = 1 ma 25 C 3 4 I 1, 5 ma IO 25 ma 4 C to 125 C IO = 1 ma, IO = 25 ma, I = 2.97 I = C C to 125 C C C to 125 C 9 (2.97 O)/IO, O, I I = 2.97, 25 C IO = 25 ma 4 C to 125 C C 9 27 Input regulation I =4to1, 5 µa IO 25 ma m 4 C to 125 C 33 Output regulation Ripple rejection IO =5mAto25mA ma, IO =5µA to 25 ma, f = 12 Hz 4 I 1 4 I 1 IO =5µA IO = 25 ma 25 C C to 125 C C C to 125 C C C to 125 C C C to 125 C 38 Output noise spectral density f = 12 Hz 25 C 2 µ/ Hz Output noise voltage 1 Hz f 1 khz, CSR = 1 Ω CO = 4.7 µf 25 C 256 UNIT m Ω m db CO = 1 µf 25 C 26 µrms CO = 1 µf 25 C 132 PG trip-threshold voltage O voltage decreasing from above PG 4 C to 125 C.95 O(nom) PG hysteresis voltage 25 C 5 m PG output low voltage IPG =12mA 1.2 ma, I = C C to 125 C.44 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. POST OFFICE BOX DALLAS, TEXAS

10 TPS7233Q electrical characteristics, I O = 1 ma, I = 4.3, EN =, C O = 4.7 µf (CSR = 1 Ω), SENSE shorted to OUT (unless otherwise noted) Output voltage PARAMETER TEST CONDITIONS TJ TPS7233Q MIN TYP MAX I = 4.3, IO = 1 ma 25 C I 1, 5 ma IO 25 ma 4 C to 125 C IO =1mA ma, I = 3.23 Dropout voltage IO = 1 ma, I = 3.23 Pass-element series resistance IO = 25 ma, I = C C to 125 C 3 25 C C to 125 C C C to 125 C 61 (3.23 O)/IO, O, I = 3.23, 25 C IO = 25 ma 4 C to 125 C C 8 25 Input regulation I =43to1 4.3, 5 µa IO 25 ma m 4 C to 125 C 33 Output regulation Ripple rejection IO =5mAto25mA ma, IO =5µA to 25 ma, f = 12 Hz I I 1 IO =5µA IO = 25 ma 25 C C to 125 C C C to 125 C C C to 125 C C C to 125 C 33 Output noise spectral density f = 12 Hz 25 C 2 µ/ Hz Output noise voltage 1 Hz f 1 khz, CSR = 1 Ω CO = 4.7 µf 25 C 265 UNIT m Ω m CO = 1 µf 25 C 212 µrms CO = 1 µf 25 C 135 PG trip-threshold voltage O voltage decreasing from above PG 4 C to 125 C.95 O(nom) PG hysteresis voltage 25 C 32 m PG output low voltage IPG =12mA 1.2 ma, I = C C to 125 C.4 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. db 1 POST OFFICE BOX DALLAS, TEXAS 75265

11 TPS7248Q electrical characteristics, I O = 1 ma, I = 5.85, EN =, C O = 4.7 µf (CSR = 1 Ω), SENSE shorted to OUT (unless otherwise noted) Output voltage PARAMETER TEST CONDITIONS TJ TPS7248Q MIN TYP MAX I = 5.85, IO = 1 ma 25 C I 1, 5 ma IO 25 ma 4 C to 125 C IO =1mA ma, I = 4.75 Dropout voltage IO = 1 ma, I = 4.75 Pass-element series resistance IO = 25 ma, I = C C to 125 C 3 25 C C to 125 C C C to 125 C 285 (4.75 O)/IO, O, I = 4.75, 25 C.8 1 IO = 25 ma 4 C to 125 C C 34 Input regulation I =585to1 5.85, 5 µa IO 25 ma m 4 C to 125 C 5 Output regulation Ripple rejection IO =5mAto25mA ma, IO =5µA to 25 ma, f = 12 Hz I I 1 IO =5µA IO = 25 ma 25 C C to 125 C C C to 125 C C C to 125 C C C to 125 C 34 Output noise spectral density f = 12 Hz 25 C 2 µ/ Hz Output noise voltage 1 Hz f 1 khz, CSR = 1 Ω CO = 4.7 µf 25 C 37 UNIT m Ω m db CO = 1 µf 25 C 29 µrms CO = 1 µf 25 C 168 PG trip-threshold voltage O voltage decreasing from above PG 4 C to 125 C.95 O(nom) PG hysteresis voltage 25 C 5 m PG output low voltage IPG =12mA 1.2 ma, I = C C to 125 C.4 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. POST OFFICE BOX DALLAS, TEXAS

12 TPS725Q electrical characteristics, I O = 1 ma, I = 6, EN =, C O = 4.7 µf (CSR = 1 Ω), SENSE shorted to OUT (unless otherwise noted) Output voltage PARAMETER TEST CONDITIONS TJ TPS725Q MIN TYP MAX I = 6, IO = 1 ma 25 C 5 6 I 1, 5 ma IO 25 ma 4 C to 125 C IO =1mA ma, I = 4.88 Dropout voltage IO = 1 ma, I = 4.88 Pass-element series resistance IO = 25 ma, I = C C to 125 C 3 25 C C to 125 C C C to 125 C 312 (4.88 O)/IO, O, I = 4.88, 25 C IO = 25 ma 4 C to 125 C C 28 Input regulation I =6to1, 5 µa IO 25 ma m 4 C to 125 C 35 Output regulation Ripple rejection IO =5mAto25mA ma, IO =5µA to 25 ma, f = 12 Hz 6 I 1 6 I 1 IO =5µA IO = 25 ma 25 C C to 125 C 1 25 C C to 125 C C C to 125 C C C to 125 C 32 Output noise spectral density f = 12 Hz 25 C 2 µ/ Hz Output noise voltage 1 Hz f 1 khz, CSR = 1 Ω CO = 4.7 µf 25 C 39 UNIT m Ω m db CO = 1 µf 25 C 3 µrms CO = 1 µf 25 C 175 PG trip-threshold voltage O voltage decreasing from above PG 4 C to 125 C.95 O(nom) PG hysteresis voltage 25 C 5 m PG output low voltage IPG =12mA 1.2 ma, I = C C to 125 C.4 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. 12 POST OFFICE BOX DALLAS, TEXAS 75265

13 electrical characteristics, I O = 1 ma, EN =, C O = 4.7 µf (CSR = 1 Ω), T J = 25 C, SENSE/FB shorted to OUT (unless otherwise noted) Ground current (active mode) PARAMETER TEST CONDITIONS EN.5, ma IO 25 ma I = O + 1, TPS72xxY MIN TYP MAX UNIT 18 µa Output current limit threshold O =, I = 1.6 A Thermal shutdown junction temperature 165 C EN hysteresis voltage 5 m Minimum I for active pass element 1.9 Minimum I for valid PG IPG = 3 µa 1.1 electrical characteristics, I O = 1 ma, EN =, C O = 4.7 µf (CSR = 1 Ω), T J = 25 C, FB shorted to OUT at device leads (unless otherwise noted) PARAMETER Reference voltage (measured at FB with OUT connected to FB) TEST CONDITIONS TPS721Y MIN TYP MAX I = 3.5, IO = 1 ma I = 2.4, 5 µa IO 1 ma 2.1 I = 2.4, 1 ma IO 2 ma 2.9 Pass-element series resistance (see Note 3) I = 2.9, 5 µa IO 25 ma 1.6 Ω Output regulation Ripple rejection I = 3.9, 5 µa IO 25 ma 1 I = 5.9, 5 µa IO 25 ma.8 3 I 1, See Note 2 IO = 5 ma to 25 ma, 15 3 I 1, See Note 2 IO = 5 µa to 25 ma, 17 I =35 3.5, f = 12 Hz IO = 5 µa 6 IO = 25 ma, See Note 2 5 Output noise spectral density I = 3.5, f = 12 Hz 2 µ/ Hz Output noise voltage UNIT m CO = 4.7 µf 235 I = 3.5, 1 Hz f 1 khz, CO = 1 µf 19 µrms CSR = 1 Ω CO = 1 µf 125 PG hysteresis voltage I = 3.5, Measured at FB 12 m PG output low voltage I = 2.13, IPG = 4 µa.1 FB input current I = na CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. This voltage is not recommended. Output voltage programmed to 2.5 with closed-loop configuration (see application information). NOTES: 2 When I < 2.9 and IO > 1 ma simultaneously, pass element rds(on) increases (see Figure 1) to a point such that the resulting dropout voltage prevents the regulator from maintaining the specified tolerance range. 3 To calculate dropout voltage, use equation: DO = IO rds(on) rds(on) is a function of both output current and input voltage. The parametric table lists rds(on) for I = 2.4, 2.9, 3.9, and 5.9, which corresponds to dropout conditions for programmed output voltages of 2.5, 3, 4, and 6, respectively. For other programmed values, refer to Figures 1 and 11. db POST OFFICE BOX DALLAS, TEXAS

14 electrical characteristics, I O = 1 ma, EN =, C O = 4.7 µf (CSR = 1 Ω), T J = 25 C, FB shorted to OUT at device leads (unless otherwise noted) PARAMETER TEST CONDITIONS TPS7225Y MIN TYP MAX Output voltage I = 3.5, IO = 1 ma 2.5 Dropout voltage I = 2.97, IO = 25 ma 56 m Pass-element series resistance (2.97 O)/IO, IO = 25 ma I = 2.97, UNIT 2.24 Ω Input regulation I = 3.5 to 1, 5 µa IO 25 ma 9 m Output regulation 3.5 I 1 IO = 5 ma to 25 ma I 1 IO = 5 µa to 25 ma 24 I = 3.5, IO = 5 µa 58 Ripple rejection f = 12 Hz IO = 25 ma 46 Output noise spectral density I = 3.5, f = 12 Hz 2 µ/ Hz Output noise voltage I = 3.5, 1 Hz f 1 khz, CSR = 1 Ω CO = 4.7 µf 248 m db CO = 1 µf 2 µrms CO = 1 µf 13 PG hysteresis voltage I = m PG output low voltage I = 2.13 IPG = 1.2 ma.3 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. 14 POST OFFICE BOX DALLAS, TEXAS 75265

15 electrical characteristics, I O = 1 ma, EN =, C O = 4.7 µf (CSR = 1 Ω), T J = 25 C, SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS TPS723Y MIN TYP MAX Output voltage I = 4, IO = 1 ma 3 Dropout voltage Pass-element series resistance I = 2.97, IO = 1 ma 145 I = 2.97, IO = 25 ma 39 (2.97 O)/IO, IO = 25 ma I = 2.97, UNIT m 1.56 Ω Input regulation I = 4 to 1, 5 µa IO 25 ma 9 m Output regulation 4 I 1 IO = 5 ma to 25 ma 34 4 I 1 IO = 5 µa to 25 ma 41 I = 4, IO = 5 µa 56 Ripple rejection I f = 12 Hz IO = 25 ma 45 Output noise spectral density I = 4, f = 12 Hz 2 µ/ Hz Output noise voltage I = 4, 1 Hz f 1 khz, CSR = 1 Ω CO = 4.7 µf 256 m db CO = 1 µf 26 µrms CO = 1 µf 132 PG hysteresis voltage I = 4 5 m PG output low voltage I = 2.55 IPG = 1.2 ma.25 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. TPS7233Y PARAMETER TEST CONDITIONS UNIT MIN TYP MAX Output voltage I = 4.3, IO = 1 ma 3.3 I = 3.23, IO = 1 ma 14 Dropout voltage I = 3.23, IO = 1 ma 14 m Pass-element series resistance I = 3.23, IO = 25 ma 36 (3.23 O)/IO, IO = 25 ma I = 3.23, 1.5 Ω Input regulation I = 4.3 to 1, 5 µa IO 25 ma 8 m Output regulation 4.3 I 1, IO = 5 ma to 25 ma I 1, IO = 5 µa to 25 ma 41 I = 4.3, IO = 5 µa 52 Ripple rejection I f = 12 Hz IO = 25 ma 44 Output noise spectral density I = 4.3, f = 12 Hz 2 µ/ Hz Output noise voltage I = 4.3, 1 Hz f 1 khz, CSR = 1 Ω CO = 4.7 µf 265 m db CO = 1 µf 212 µrms CO = 1 µf 135 PG hysteresis voltage I = m PG output low voltage I = 2.8, IPG = 1.2 ma.22 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. POST OFFICE BOX DALLAS, TEXAS

16 electrical characteristics, I O = 1 ma, EN =, C O = 4.7 µf (CSR = 1 Ω), T J = 25 C, SENSE shorted to OUT (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS TPS7248Y MIN TYP MAX Output voltage I = 5.85, IO = 1 ma 4.85 I = 4.75, IO = 1 ma 1 Dropout voltage I = 4.75, IO = 1 ma 9 m Pass-element series resistance Output regulation I = 4.75, IO = 25 ma 216 (4.75 O)/IO, IO = 25 ma I = 4.75, 5.85 I 1 IO = 5 ma to 25 ma I 1 IO = 5 µa to 25 ma 55 I = 5.85, IO = 5 µa 53 Ripple rejection I f = 12 Hz IO = 25 ma 46 UNIT.8 Ω Output noise spectral density I = 5.85, f = 12 Hz 2 µ/ Hz Output noise voltage I = 5.85, 1 Hz f 1 khz, CSR = 1 Ω CO = 4.7 µf 37 m db CO = 1 µf 29 µrms CO = 1 µf 168 PG hysteresis voltage I = m PG output low voltage I = 4.12 IPG = 1.2 ma.2 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. TPS725Y PARAMETER TEST CONDITIONS UNIT MIN TYP MAX Output voltage I = 6, IO = 1 ma 5 I = 4.88 IO = 1 ma 8 Dropout voltage I = 4.88 IO = 1 ma 76 m Pass-element series resistance I = 4.88, IO = 25 ma 19 (4.88 O)/IO, IO = 25 ma I = 4.88,.76 Ω Input regulation I = 6 to 1, 5 µa IO 25 ma m Output regulation 6 I 1, IO = 5 ma to 25 ma 46 6 I 1, IO = 5 µa to 25 ma 59 I = 6, IO = 5 µa 52 Ripple rejection f = 12 Hz IO = 25 ma 46 Output noise spectral density I = 6, f = 12 Hz 2 µ/ Hz Output noise voltage I = 6, 1 Hz f 1 khz, CSR = 1 Ω CO = 4.7 µf 39 m db CO = 1 µf 3 µrms CO = 1 µf 175 PG hysteresis voltage I = 6 5 m PG output low voltage I = 4.25, IPG = 1.2 ma.19 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. 16 POST OFFICE BOX DALLAS, TEXAS 75265

17 TYPICAL CHARACTERISTICS IQ Quiescent current Table of Graphs FIGURE Output current 5 Input voltage 6 IQ Change in quiescent current Free-air temperature 7 DO Dropout voltage Output current 8 DO Change in dropout voltage Free-air temperature 9 DO Dropout voltage (TPS721 only) Output current 1 rds(on) Pass-element series resistance Input voltage 11 O Change in output voltage Free-air temperature 12 O Output voltage Input voltage 13 Line regulation (TPS721, TPS7233, TPS7248, TPS725) 14 Load regulation (TPS7225, TPS7233, TPS7248, TPS725) 15 O(PG) Power-good (PG) voltage Output voltage 16 rds(on)pg Power-good (PG) on-resistance Input voltage 17 I Minimum input voltage for valid PG Free-air temperature 18 Output voltage response from enable (EN) 19 Load transient response (TPS721/ TPS7233) 2 Load transient response (TPS7248/ TPS725) 21 Line transient response (TPS721) 22 Line transient response (TPS7233) 23 Line transient response (TPS7248/ TPS725) 24 Ripple rejection Frequency 25 Output Spectral Noise Density Frequency 26 Output current (CO = 4.7 µf) 27 Compensation series resistance (CSR) Added ceramic capacitance (CO = 4.7 µf) 28 Output current (CO = 1 µf) 29 Added ceramic capacitance (CO = 1 µf) 3 This symbol is not currently listed within EIA or JEDEC standards for semiconductor symbology. POST OFFICE BOX DALLAS, TEXAS

18 TYPICAL CHARACTERISTICS QUIESCENT CURRENT OUTPUT CURRENT TPS7248 I = 1 25 TA 25 C IO = 25 ma QUIESCENT CURRENT INPUT OLTAGE TPS7248 I Q Quiescent Current µ A TPS7233 I = 1 TPS725 I = 1 TPS7248 I = 5.85 TPS725 I = 6. I Q Quiescent Current µ A TPS725 TPS7233 TPS721 With O Programmed to TPS7233 I = IO Output Current ma Figure I Input oltage Figure 6 CHANGE IN QUIESCENT CURRENT FREE-AIR TEMPERATURE DROPOUT OLTAGE OUTPUT CURRENT I Q Change in Quiescent Current µ A IO = 1 ma I = O + 1 Dropout oltage m DO TPS7225 TPS725 TPS723 TPS7233 TPS TA Free-Air Temperature C Figure IO Output Current ma Figure 8 18 POST OFFICE BOX DALLAS, TEXAS 75265

19 TYPICAL CHARACTERISTICS CHANGE IN DROPOUT OLTAGE FREE-AIR TEMPERATURE TPS721 DROPOUT OLTAGE OUTPUT CURRENT DO Change in Dropout oltage TPS7233 TPS723 TPS7248/TPS725 DO Dropout oltage I = 2.9 I = 3.2 I = 3.9 I = 5.9 I = 9.65 I = 2.4 I = TA Free-Air Temperature C Figure IO Output Current ma This voltage is not recommended. Figure 1 PASS ELEMENT SERIES RESISTANCE INPUT OLTAGE CHANGE IN OUTPUT OLTAGE FREE-AIR TEMPERATURE 6 15 r DS(on) Pass Element Series Resistance Ω IO = 25 ma IO = 1 ma I Input oltage FB = O Change in Output oltage m IO = 1 ma I = O TA Free-Air Temperature C Figure 11 Figure 12 POST OFFICE BOX DALLAS, TEXAS

20 TYPICAL CHARACTERISTICS OUTPUT OLTAGE INPUT OLTAGE LINE REGULATION Output oltage O IO = 25 ma TPS725 TPS7248 TPS7233 TPS721 With O Programmed to 2.5 O Change in Output oltage m IO = 25 ma TPS7233 TPS721 With O Programmed to 2.5 TPS725 TPS I Input oltage Figure I Input oltage Figure LOAD REGULATION 6 POWER-GOOD (PG) OLTAGE OUTPUT OLTAGE PG Pulled Up to I With 5 kω Resistor O Change in Output oltage m TPS7225 TPS7233 TPS7248 TPS725 Power-Good (PG) oltage ÁÁ O(PG) I GND IO Output Current ma Figure O Output oltage % O as a percent of Onom. Figure 16 2 POST OFFICE BOX DALLAS, TEXAS 75265

21 TYPICAL CHARACTERISTICS r DS(on) Power-Good (PG) On-Resistance k Ω POWER-GOOD (PG) ON-RESISTANCE INPUT OLTAGE I Input oltage Figure Minimum Input oltage for alid PG I MINIMUM INPUT OLTAGE FOR ALID PG FREE-AIR TEMPERATURE TA Free-Air Temperature C Figure 18 O nom OUTPUT OLTAGE RESPONSE FROM ENABLE (EN) CI = CO = 4.7 µf (CSR = 1 Ω) 1 5 O Output oltage (alues ary With Selection of Device) I(EN) EN oltage t Time µs Figure 19 POST OFFICE BOX DALLAS, TEXAS

22 TYPICAL CHARACTERISTICS O Change in Output oltage m TPS721 (WITH O PROGRAMMED TO 2.5 ), TPS7233 LOAD TRANSIENT RESPONSE I = 6 CI = CO = 4.7 µf (CSR = 1 Ω) Output Current ma t Time µs I O Figure 2 O Change in Output oltage m TPS7248/TPS725 LOAD TRANSIENT RESPONSE I = 6 CI = CO = 4.7 µf (CSR = 1 Ω) I O Output Current ma t Time µs Figure POST OFFICE BOX DALLAS, TEXAS 75265

23 TYPICAL CHARACTERISTICS O Change in Output oltage m TPS721 WITH O PROGRAMMED TO 2.5 LINE TRANSIENT RESPONSE CI = CO = 4.7 µf (CSR = 1 Ω) Input oltage t Time µs I Figure 22 O Change in Output oltage m TPS7233 LINE TRANSIENT RESPONSE CI = CO = 4.7 µf (CSR = 1 Ω) Input oltage I t Time µs Figure 23 POST OFFICE BOX DALLAS, TEXAS

24 TYPICAL CHARACTERISTICS O Change in Output oltage m TPS7248/TPS725 LINE TRANSIENT RESPONSE CI = CO = 4.7 µf (CSR = 1 Ω) Input oltage t Time µs I Figure 24 Ripple Rejection db TPS7233 TPS7248/ TPS725 RIPPLE REJECTION FREQUENCY K 1 K 1 K 1 M 1 M f Frequency Hz Figure 25 No Input Capacitance Added I = O + 1 IO = 1 ma CO = 4.7 µf (CSR = 1 Ω) TPS721 With O Programmed to 2.5 Output Spectral Noise Density µ / Hz OUTPUT SPECTRAL NOISE DENSITY FREQUENCY CO = 1 µf (CSR = 1 Ω) No Input Capacitance Added I = O + 1 CO = 4.7 µf (CSR = 1 Ω) k 1 k 1 k f Frequency Hz Figure 26 CO = 1 µf (CSR = 1 Ω) 24 POST OFFICE BOX DALLAS, TEXAS 75265

25 TYPICAL CHARACTERISTICS CSR Compensation Series Resistance Ω TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE (CSR) OUTPUT CURRENT Region of Instability I = O + 1 CO = 4.7 µf No Added Ceramic Capacitance No Input Capacitance Added CSR Compensation Series Resistance Ω TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE (CSR) ADDED CERAMIC CAPACITANCE Region of Instability I = O + 1 IO = 25 ma CO = 4.7 µf No Input Capacitor Added Region of Instability Region of Instability IO Output Current ma Added Ceramic Capacitance µf Figure 27 Figure 28 CSR Compensation Series Resistance Ω TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE (CSR) OUTPUT CURRENT Region of Instability I = O + 1 CO = 1 µf No Added Ceramic Capacitance No Input Capacitor Added Region of Instability CSR Compensation Series Resistance Ω 1 TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE (CSR) ADDED CERAMIC CAPACITANCE Region of Instability I = O + 1 IO = 25 ma CO = 1 µf No Input Capacitor Added Region of Instability IO Output Current ma Added Ceramic Capacitance µf Figure 29 Figure 3 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. POST OFFICE BOX DALLAS, TEXAS

26 APPLICATION INFORMATION The design of the TPS72xx family of low-dropout (LDO) regulators is based on the higher-current TPS71xx family. These new families of regulators have been optimized for use in battery-operated equipment and feature extremely low dropout voltages, low supply currents that remain constant over the full-output-current range of the device, and an enable input to reduce supply currents to less than.5 µa when the regulator is turned off. device operation The TPS72xx uses a PMOS pass element to dramatically reduce both dropout voltage and supply current over more conventional PNP-pass-element LDO designs. The PMOS transistor is a voltage-controlled device that, unlike a PNP transistor, does not require increased drive current as output current increases. Supply current in the TPS72xx is essentially constant from no-load to maximum. Current limiting and thermal protection prevent damage by excessive output current and/or power dissipation. The device switches into a constant-current mode at approximately 1 A; further load increases reduce the output voltage instead of increasing the output current. The thermal protection shuts the regulator off if the junction temperature rises above 165 C. Recovery is automatic when the junction temperature drops approximately 5 C below the high temperature trip point. The PMOS pass element includes a back diode that safely conducts reverse current when the input voltage level drops below the output voltage level. A logic high on the enable input, EN, shuts off the output and reduces the supply current to less than.5 µa. EN should be grounded in applications where the shutdown feature is not used. Power good (PG) is an open-drain output signal used to indicate output-voltage status. A comparator circuit continuously monitors the output voltage. When the output drops to approximately 95% of its nominal regulated value, the comparator turns on and pulls PG low. Transient loads or line pulses can also cause activation of PG if proper care is not taken in selecting the input and output capacitors. Load transients that are faster than 5 µs can cause a signal on PG if high-esr output capacitors (greater than approximately 7 Ω) are used. A 1-µs transient causes a PG signal when using an output capacitor with greater than 3.5 Ω of ESR. It is interesting to note that the output-voltage spike during the transient can drop well below the reset threshold and still not trip if the transient duration is short. A 1-µs transient must drop at least 5 m below the threshold before tripping the PG circuit. A 2-µs transient trips PG at just 4 m below the threshold. Lower-ESR output capacitors help by reducing the drop in output voltage during a transient and should be used when fast transients are expected. A typical application circuit is shown in Figure POST OFFICE BOX DALLAS, TEXAS 75265

27 APPLICATION INFORMATION TPS72xx (see Note A) I C1.1 µf IN PG IN SENSE OUT EN OUT GND PG 25 kω O + 1 µf 3 CSR = 1 Ω external capacitor requirements NOTE A: TPS7225, TPS723, TPS7233, TPS7248, TPS725 (fixed-voltage options). Figure 31. Typical Application Circuit Although not required, a.47-µf to.1-µf ceramic bypass input capacitor, connected between IN and GND and located close to the TPS72xx, is recommended to improve transient response and noise rejection. A higher-value electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated and the device is located several inches from the power source. An output capacitor is required to stabilize the internal feedback loop. For most applications, a 1-µF to 15-µF solid-tantalum capacitor with a.5-ω resistor (see capacitor selection table) in series is sufficient. The maximum capacitor ESR should be limited to 1.3 Ω to allow for ESR doubling at cold temperatures. Figure 32 shows the transient response of a 5-mA to 85-mA load using a 1-µF output capacitor with a total ESR of 1.7 Ω. A 4.7-µF solid-tantalum capacitor in series with a 1-Ω resistor may also be used (see Figures 27 and 28) provided the ESR of the capacitor does not exceed 1 Ω at room temperature and 2 Ω over the full operating temperature range. POST OFFICE BOX DALLAS, TEXAS

28 APPLICATION INFORMATION I = O O IO = 85 ma 2 IO = 5 ma Ch1 5 m Ch 2 5 ma 1 µs/div Figure 32. Load Transient Response (CSR total = 1.7 Ω), TPS7248Q A partial listing of surface-mount capacitors usable with the TPS72xx family is provided below. This information (along with the stability graphs, Figures 27 through 3) is included to assist the designer in selecting suitable capacitors. CAPACITOR SELECTION PART NO. MFR. ALUE MAX ESR SIZE (H L W) 592D156X2R2T Sprague 15 µf, D156X25C2T Sprague 15 µf, D16X25C2T Sprague 1 µf, D16X35G2T Sprague 1 µf, Size is in mm. ESR is maximum resistance in ohms at 1 khz and. Listings are sorted by height. sense-pin connection SENSE must be connected to OUT for proper operation of the regulator. Normally this connection should be as short as possible; however, remote sense may be implemented in critical applications when proper care of the circuit path is exercised. SENSE internally connects to a high-impedance wide-bandwidth amplifier through a resistor-divider network, and any noise pickup on the PCB trace will feed through to the regulator output. SENSE must be routed to minimize noise pickup. Filtering SENSE using an RC network is not recommended because of the possibility of inducing regulator instability. 28 POST OFFICE BOX DALLAS, TEXAS 75265

29 APPLICATION INFORMATION output voltage programming The output voltage of the TPS721 adjustable regulator is programmed using an external resistor divider as shown in Figure 33. The output voltage is calculated using:.1 R1. O ref R2 (1) Where: ref = typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately 7-µA divider current. Lower value resistors can be used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 169 kω to set the divider current at 7 µa and then calculate R1 using: R1. O ref 1. R2 (2) OUTPUT OLTAGE OUTPUT OLTAGE PROGRAMMING GUIDE DIIDER RESISTANCE (kω) () R1 R % values shown. >2.7 I.1 µf < TPS721 IN IN PG OUT EN OUT FB GND kω R1 R2 Power-Good Indicator + O 1 µf CSR = 1 Ω Figure 33. TPS721 Adjustable LDO Regulator Programming POST OFFICE BOX DALLAS, TEXAS

30 APPLICATION INFORMATION power dissipation and junction temperature Specified regulator operation is assured to a junction temperature of 125 C; the maximum junction temperature allowable to avoid damaging the device is 15 C. These restrictions limit the power dissipation that the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, P D(max), and the actual dissipation, P D, which must be less than or equal to P D(max). The maximum-power-dissipation limit is determined using the following equation: P D(max) T J max T A R JA Where: T J max is the maximum allowable junction temperature, i.e.,15 C absolute maximum and 125 C recommended operating temperature. R θja is the thermal resistance junction-to-ambient for the package, i.e., 172 C/W for the 8-terminal SOIC and 238 C/W for the 8-terminal TSSOP. T A is the ambient temperature. The regulator dissipation is calculated using: P D. I O. I O Power dissipation resulting from quiescent current is negligible. regulator protection The TPS72xx PMOS-pass transistor has a built-in back diode that safely conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. If extended reverse voltage is anticipated, external limiting might be appropriate. The TPS72xx also features internal current limiting and thermal protection. During normal operation, the TPS72xx limits output current to approximately 1 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 165 C, thermal-protection circuitry shuts it down. Once the device has cooled, regulator operation resumes. 3 POST OFFICE BOX DALLAS, TEXAS 75265

31 D (R-PDSO-G**) 14 PIN SHOWN MECHANICAL DATA PLASTIC SMALL-OUTLINE PACKAGE.5 (1,27).2 (,51).14 (,35).1 (,25) M (4,).15 (3,81).244 (6,2).228 (5,8).8 (,2) NOM Gage Plane 1 A (,25).44 (1,12).16 (,4).69 (1,75) MAX.1 (,25).4 (,1) Seating Plane.4 (,1) DIM PINS ** A MAX.197 (5,).344 (8,75).394 (1,) A MIN.189 (4,8).337 (8,55).386 (9,8) 4447/ D 1/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed.6 (,15). D. Falls within JEDEC MS-12 POST OFFICE BOX DALLAS, TEXAS

32 P (R-PDIP-T8) MECHANICAL DATA PLASTIC DUAL-IN-LINE PACKAGE.4 (1,6).355 (9,2) (6,6).24 (6,1) (1,78) MAX.2 (,51) MIN.31 (7,87).29 (7,37).2 (5,8) MAX Seating Plane.125 (3,18) MIN.1 (2,54) (,53).15 (,38).1 (,25) M.1 (,25) NOM 4482/ B 3/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-1 32 POST OFFICE BOX DALLAS, TEXAS 75265

33 PW (R-PDSO-G**) 14 PIN SHOWN MECHANICAL DATA PLASTIC SMALL-OUTLINE PACKAGE,3,65,1 M, ,5 4,3 6,6 6,2,15 NOM Gage Plane 1 A 7 8,25,75,5 Seating Plane 1,2 MAX,15,5,1 DIM PINS ** A MAX 3,1 5,1 5,1 6,6 7,9 9,8 A MIN 2,9 4,9 4,9 6,4 7,7 9,6 4464/ E 8/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed,15. D. Falls within JEDEC MO-153 POST OFFICE BOX DALLAS, TEXAS

34 PACKAGE OPTION ADDENDUM 18-Jul-26 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty TPS721QD ACTIE SOIC D 8 75 Green (RoHS & TPS721QDG4 ACTIE SOIC D 8 75 Green (RoHS & TPS721QDR ACTIE SOIC D 8 25 Green (RoHS & TPS721QDRG4 ACTIE SOIC D 8 25 Green (RoHS & TPS721QP ACTIE PDIP P 8 5 Pb-Free (RoHS) TPS721QPE4 ACTIE PDIP P 8 5 Pb-Free (RoHS) TPS721QPW ACTIE TSSOP PW 8 15 Green (RoHS & TPS721QPWG4 ACTIE TSSOP PW 8 15 Green (RoHS & Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TPS721QPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI TPS721QPWR ACTIE TSSOP PW 8 2 Green (RoHS & TPS721QPWRG4 ACTIE TSSOP PW 8 2 Green (RoHS & TPS7225QD ACTIE SOIC D 8 75 Green (RoHS & TPS7225QDG4 ACTIE SOIC D 8 75 Green (RoHS & TPS7225QDR ACTIE SOIC D 8 25 Green (RoHS & TPS7225QDRG4 ACTIE SOIC D 8 25 Green (RoHS & TPS7225QP ACTIE PDIP P 8 5 Pb-Free (RoHS) TPS7225QPE4 ACTIE PDIP P 8 5 Pb-Free (RoHS) TPS7225QPWR ACTIE TSSOP PW 8 2 Green (RoHS & TPS723QD ACTIE SOIC D 8 75 Green (RoHS & TPS723QDR ACTIE SOIC D 8 25 Green (RoHS & TPS723QDRG4 ACTIE SOIC D 8 25 Green (RoHS & TPS723QP ACTIE PDIP P 8 5 Pb-Free (RoHS) TPS723QPE4 ACTIE PDIP P 8 5 Pb-Free (RoHS) TPS723QPWR ACTIE TSSOP PW 8 2 Green (RoHS & TPS723QPWRG4 ACTIE TSSOP PW 8 2 Green (RoHS & Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-26C-UNLIM Level-1-26C-UNLIM Addendum-Page 1

35 PACKAGE OPTION ADDENDUM 18-Jul-26 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty TPS7233QD ACTIE SOIC D 8 75 Green (RoHS & TPS7233QDG4 ACTIE SOIC D 8 75 Green (RoHS & TPS7233QDR ACTIE SOIC D 8 25 Green (RoHS & TPS7233QDRG4 ACTIE SOIC D 8 25 Green (RoHS & TPS7233QP ACTIE PDIP P 8 5 Pb-Free (RoHS) TPS7233QPE4 ACTIE PDIP P 8 5 Pb-Free (RoHS) TPS7233QPW ACTIE TSSOP PW 8 15 Green (RoHS & TPS7233QPWG4 ACTIE TSSOP PW 8 15 Green (RoHS & Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TPS7233QPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI TPS7233QPWR ACTIE TSSOP PW 8 2 Green (RoHS & TPS7233QPWRG4 ACTIE TSSOP PW 8 2 Green (RoHS & TPS7248QD ACTIE SOIC D 8 75 Green (RoHS & TPS7248QDG4 ACTIE SOIC D 8 75 Green (RoHS & TPS7248QDR ACTIE SOIC D 8 25 Green (RoHS & TPS7248QDRG4 ACTIE SOIC D 8 25 Green (RoHS & TPS7248QP ACTIE PDIP P 8 5 Pb-Free (RoHS) TPS7248QPE4 ACTIE PDIP P 8 5 Pb-Free (RoHS) TPS7248QPW ACTIE TSSOP PW 8 15 Green (RoHS & TPS7248QPWG4 ACTIE TSSOP PW 8 15 Green (RoHS & TPS7248QPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI TPS7248QPWR ACTIE TSSOP PW 8 2 Green (RoHS & TPS7248QPWRG4 ACTIE TSSOP PW 8 2 Green (RoHS & TPS725QD ACTIE SOIC D 8 75 Green (RoHS & TPS725QDG4 ACTIE SOIC D 8 75 Green (RoHS & TPS725QDR ACTIE SOIC D 8 25 Green (RoHS & TPS725QDRG4 ACTIE SOIC D 8 25 Green (RoHS & Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM TPS725QP ACTIE PDIP P 8 5 Pb-Free N / A for Pkg Type Addendum-Page 2

36 PACKAGE OPTION ADDENDUM 18-Jul-26 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) (RoHS) TPS725QPE4 ACTIE PDIP P 8 5 Pb-Free (RoHS) TPS725QPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI TPS725QPWR ACTIE TSSOP PW 8 2 Green (RoHS & TPS725QPWRG4 ACTIE TSSOP PW 8 2 Green (RoHS & N / A for Pkg Type Level-1-26C-UNLIM Level-1-26C-UNLIM (1) The marketing status values are defined as follows: ACTIE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3