TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS

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1 Available in 5-V, 4.85-V, and 3.3-V Fixed-Output and Adjustable Versions Very Low-Dropout Voltage...Maximum of 32 mv at I O = 0 ma (TPS750) Very Low Quiescent Current Independent of Load µa Typ Extremely Low Sleep-State Current 0.5 µa Max 2% Tolerance Over Specified Conditions For Fixed-Output Versions Output Current Range of 0 ma to 500 ma TSSOP Package Option Offers Reduced Component Height for Space-Critical Applications Power-Good (PG) Status Output description The TPS7xx integrated circuits are a family of micropower low-dropout (LDO) voltage regulators. An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device. TPS7Q, TPS733Q, TPS748Q, TPS750Q NC No internal connection SENSE Fixed voltage options only (TPS733, TPS748, and TPS750) FB Adjustable version only (TPS7) Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 32 mv at an output current of 0 ma for the TPS750) and is directly proportional to the output current (see Figure ). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and remains independent of output loading (typically 285 µa over the full range of output current, 0 ma to 500 ma). These two key specifications yield a significant improvement in operating life for battery-powered systems. The LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 0.5 µa maximum at T J = 25 C. GND EN IN IN GND GND GND NC NC EN NC IN IN IN D OR P PACKAGE (TOP VIEW) PW PACKAGE (TOP VIEW) PG SENSE /FB OUT OUT PG NC NC FB NC SENSE OUT OUT NC NC Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2003, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS 75265

2 TPS7Q, TPS733Q, TPS748Q, TPS750Q description (continued) Dropout Voltage V TPS733 TPS748 TPS IO Output Current A Figure. Dropout Voltage Versus Output Current Power good (PG) reports low output voltage and can be used to implement a power-on reset or a low-battery indicator. The TPS7xx is offered in 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for adjustable version). The TPS7xx family is available in PDIP (8 pin), SO (8 pin), and TSSOP (20-pin) packages. The TSSOP has a maximum height of,2 mm. TJ OUTPUT VOLTAGE (V) MIN TYP MAX AVAILABLE OPTIONS SMALL OUTLINE (D) PACKAGED DEVICES PLASTIC DIP (P) TSSOP (PW) CHIP FORM (Y) TPS750QD TPS750QP TPS750QPW TPS750Y TPS748QD TPS748QP TPS748QPW TPS748Y 40 C to 25 C TPS733QD TPS733QP TPS733QPW TPS733Y Adjustable.2 V to 9.75 V TPS7QD TPS7QP TPS7QPW TPS7Y The D and PW packages are available taped and reeled. Add R suffix to device type (e.g., TPS750QDR). The TPS7Q is programmable using an external resistor divider (see application information). The chip form is tested at 25 C. 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 TPS7Q, TPS733Q, TPS748Q, TPS750Q TPS7xx VI 0. µf IN PG IN SENSE IN OUT EN OUT GND PG VO CO + µf 2 3 CSR TPS733, TPS748, TPS750 (fixed-voltage options) Capacitor selection is nontrivial. See application information section for details. Figure 2. Typical Application Configuration TPS7xx chip information These chips, when properly assembled, display characteristics similar to the TPS7xxQ. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS (6) (5) (4) IN EN (3) (2) TPS7xx (5) (6) (4) (7) SENSE FB OUT PG () (7) GND 80 CHIP THICKNESS: 5 MILS TYPICAL BONDING PADS: 4 4 MILS MINIMUM TJmax = 50 C TOLERANCES ARE ±%. ALL DIMENSIONS ARE IN MILS. () (2) (3) SENSE Fixed voltage options only (TPS733, TPS748, and TPS750) FB Adjustable version only (TPS7) 92 NOTE A: For most applications, OUT and SENSE should be tied together as close as possible to the device; for other implementations, refer to SENSE-pin connection discussion in the Applications Information section of this data sheet. POST OFFICE BOX DALLAS, TEXAS

4 TPS7Q, TPS733Q, TPS748Q, TPS750Q functional block diagram IN EN _ PG RESISTOR DIVIDER OPTIONS DEVICE TPS7 TPS733 TPS748 TPS750 R R UNIT Ω kω kω kω Vref =.78 V +.2 V + _ R OUT SENSE /FB NOTE A: Resistors are nominal values only. COMPONENT COUNT MOS transistors Bilpolar transistors Diodes Capacitors Resistors R2 GND Switch positions are shown with EN low (active). For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to SENSE-pin connection discussion in Applications Information section. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Input voltage range, V I, PG, SENSE, EN V to V Output current, I O A Continuous total power dissipation See Dissipation Rating Tables and 2 Operating virtual junction temperature range, T J C to 50 C Storage temperature range, T stg C to 50 C Lead temperature,6 mm (/6 inch) from case for seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network terminal ground. DISSIPATION RATING TABLE FREE-AIR TEMPERATURE (see Figure 3)# PACKAGE TA A 25 C DERATING FACTOR TA A = 70 C TA A = 25 C POWER RATING ABOVE POWER RATING POWER RATING D 725 mw 5.8 mw/ C 464 mw 45 mw P 75 mw 9.4 mw/ C 752 mw 235 mw PW 700 mw 5.6 mw/ C 448 mw 40 mw PACKAGE DISSIPATION RATING TABLE 2 CASE TEMPERATURE (see Figure 4)# TC 25 C DERATING FACTOR TC = 70 C TC = 25 C POWER RATING ABOVE TC = 25 C POWER RATING POWER RATING D P 288 mw 2738 mw 7.5 mw/ C 2.9 mw/ C 400 mw 752 mw 438 mw 548 mw PW 4025 mw 32.2 mw/ C 2576 mw 805 mw # Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 50 C. For guidelines on maintaining junction temperature within recommended operating range, see the Thermal Information section. Refer to Thermal Information section for detailed power dissipation considerations when using the TSSOP packages. 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 TPS7Q, TPS733Q, TPS748Q, TPS750Q 400 DISSIPATION DERATING CURVE FREE-AIR TEMPERATURE 4800 DISSIPATION DERATING CURVE CASE TEMPERATURE P D Maximum Continuous Dissipation mw PW and PWP Package RθJA = 78 C/W P Package RθJA = 6 C/W D Package RθJA = 72 C/W P D Maximum Continuous Dissipation mw PW Package RθJC = 3 C/W D Package RθJC = 57 C/W P Package RθJC = 46 C/W TA Free-Air Temperature C TC Case Temperature C Figure 3 Figure 4 Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 50 C. For guidelines on maintaining junction temperature within recommended operating range, see the Thermal Information section. recommended operating conditions MIN MAX UNIT TPS7Q 2.5 TPS733Q 3.77 Input voltage, VI V TPS748Q 5.2 TPS750Q 5.33 High-level input voltage at EN, VIH 2 V Low-level input voltage at EN, VIL 0.5 V Output current range, IO ma Operating virtual junction temperature range, TJ C Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load) Because the TPS7 is programmable, rds(on) should be used to calculate VDO before applying the above equation. The equation for calculating VDO from rds(on) is given in Note 2 in the electrical characteristics table. The minimum value of 2.5 V is the absolute lower limit for the recommended input voltage range for the TPS7. POST OFFICE BOX DALLAS, TEXAS

6 TPS7Q, TPS733Q, TPS748Q, TPS750Q electrical characteristics at I O = ma, EN = 0 V, C O = 4.7 µf/csr = Ω, SENSE/FB shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS TJ Ground current (active mode) TPS7Q, TPS733Q TPS748Q, TPS750Q MIN TYP MAX EN 0.5 V, = 25 C VI VO + V, 0 ma IO 500 ma 40 C to 25 C C 0.5 Input current (standby mode) EN = VI, 27V 2.7 VI V µa 40 C to 25 C 2 Output current limit VO =0 0, VI =V Pass-element leakage current in standby mode PG leakage current Normal operation, VPG = V 25 C C to 25 C 2 25 C 0.5 EN = VI, 27V 2.7 VI V µa 40 C to 25 C 25 C C to 25 C 0.5 Output voltage temperature coefficient 40 C to 25 C 6 75 ppm/ C Thermal shutdown junction temperature 65 C EN logic high (standby mode) EN logic low (active mode) 2.5 V VI 6 V 6 V VI V 27V 2.7 VI V 40 C to25 C C C to 25 C 0.5 EN hysteresis voltage 25 C 50 mv EN input current 0V VI V 0V VI V Minimum VI for active pass element Minimum VI for valid PG IPG = 300 µa IPG = 300 µa 25 C C to 25 C C C to 25 C C C to 25 C.9 CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. UNIT µa A µa V V µa V V 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 TPS7Q, TPS733Q, TPS748Q, TPS750Q TPS7 electrical characteristics at I O = ma, V I = 3.5 V, EN = 0 V, C O = 4.7 µf/csr = Ω, FB shorted to OUT at device leads (unless otherwise noted) TPS7Q PARAMETER TEST CONDITIONS TJ UNIT MIN TYP MAX V I = 3.5 V, IO = ma 25 C.78 V Reference voltage (measured at FB with OUT connected to FB) 2.5 V VI V, 5 ma IO 500 ma, 40 C to 25 C V See Note Reference voltage temperature coefficient Pass-element series resistance (see Note 2) VI =24V 2.4 V, VI =24V 2.4 V, VI =29V 2.9 V, 50 µa IO 50 ma 40 C to 25 C 6 75 ppm/ C 25 C C to 25 C 50 ma IO C ma 40 C to 25 C.3 50 µa IO 500 ma 25 C C to 25 C 0.85 VI = 3.9 V, 50 µa IO 500 ma 25 C 0.32 VI = 5.9 V, 50 µa IO 500 ma 25 C 0.23 VI = 2.5 V to V, 50 µa IO 500 ma, 25 C 8 Input regulation I O See Note 40 C to 25 C 25 Output regulation Ripple rejection IO = 5 ma to 500 ma, 2.5 V VI V, 25 C 4 See Note 40 C to 25 C 25 IO = 50 µa to 500 ma, 2.5 V VI V, 25 C 22 See Note 40 C to 25 C 54 f = 20 Hz IO =50µA 25 C C to 25 C 44 IO = 500 ma, 25 C See Note 40 C to 25 C 44 Output noise-spectral density f = 20 Hz 25 C 2 µv/ Hz Output noise voltage Hz f 0 khz, CSR =Ω Ω CO = 4.7 µf 25 C 95 Ω mv mv mv db CO = µf 25 C 89 µvrms CO = 0 µf 25 C 74 PG trip-threshold voltage VFB voltage decreasing from above VPG 40 C to 25 C..45 V PG hysteresis voltage Measured at VFB 25 C 2 mv PG output low voltage IPG = 400 µa, VI = 2.3 V FB input current 25 C C to 25 C C C to 25 C CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. Output voltage programmed to 2.5 V with closed-loop configuration (see application information). NOTES:. When VI < 2.9 V and IO > 50 ma simultaneously, pass element rds(on) increases (see Figure 27) to a point such that the resulting dropout voltage prevents the regulator from maintaining the specified tolerance range. 2. To calculate dropout voltage, use equation: VDO = IO rds(on) rds(on) is a function of both output current and input voltage. The parametric table lists rds(on) for VI = 2.4 V, 2.9 V, 3.9 V, and 5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other programmed values, refer to Figure 26. V na POST OFFICE BOX DALLAS, TEXAS

8 TPS7Q, TPS733Q, TPS748Q, TPS750Q TPS733 electrical characteristics at I O = ma, V I = 4.3 V, EN = 0 V, C O = 4.7 µf/csr = Ω, SENSE shorted to OUT (unless otherwise noted) TPS733Q PARAMETER TEST CONDITIONS TJ MIN TYP MAX VI = 4.3 V, IO = ma 25 C 3.3 Output voltage 4.3 V VI V, 5 ma IO 500 ma 40 C to 25 C IO =ma ma, VI = 3.23 V Dropout voltage IO = 0 ma, VI = 3.23 V Pass-element series resistance IO = 500 ma, VI = 3.23 V 25 C C to 25 C 8 25 C C to 25 C C C to 25 C 400 (3.23 V VO)/IO, O, VI = 3.23 V, 25 C IO = 500 ma 40 C to 25 C C 20 Input regulation VI =43VtoV 4.3 V, 50 µa IO 500 ma mv 40 C to 25 C 27 Output regulation Ripple rejection IO =5mAto500mA 500 ma, IO =50µA to 500 ma, f = 20 Hz 43V 4.3 VI V 43V 4.3 VI V IO =50µA IO = 500 ma 25 C C to 25 C C C to 25 C C C to 25 C C C to 25 C 36 Output noise-spectral density f = 20 Hz 25 C 2 µv/ Hz Output noise voltage Hz f 0 khz, CSR = Ω CO = 4.7 µf 25 C 274 UNIT V mv Ω mv mv db CO = µf 25 C 228 µvrms CO = 0 µf 25 C 59 PG trip-threshold voltage VO voltage decreasing from above VPG 40 C to 25 C V PG hysteresis voltage 25 C 35 mv PG output low voltage IPG =ma ma, VI =28V C C to 25 C 0.4 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. V 8 POST OFFICE BOX DALLAS, TEXAS 75265

9 TPS7Q, TPS733Q, TPS748Q, TPS750Q TPS748 electrical characteristics at I O = ma, V I = 5.85 V, EN = 0 V, C O = 4.7 µf/csr = Ω, SENSE shorted to OUT (unless otherwise noted) TPS748Q PARAMETER TEST CONDITIONS TJ MIN TYP MAX VI = 5.85 V, IO = ma 25 C 4.85 Output voltage 5.85 V VI V, 5 ma IO 500 ma 40 C to 25 C IO =ma ma, VI = 4.75 V Dropout voltage IO = 0 ma, VI = 4.75 V Pass-element series resistance IO = 500 ma, VI = 4.75 V 25 C C to 25 C 8 25 C C to 25 C C C to 25 C 250 (4.75 V VO)/IO, O, VI = 4.75 V, 25 C IO = 500 ma 40 C to 25 C C 27 Input regulation VI =585VtoV 5.85 V, 50 µa IO 500 ma mv 40 C to 25 C 37 Output regulation Ripple rejection IO =5mAto500mA 500 ma, IO =50µA to 500 ma, f = 20 Hz 585V 5.85 VI V 585V 5.85 VI V IO =50µA IO = 500 ma 25 C C to 25 C C C to 25 C C C to 25 C C C to 25 C 35 Output noise-spectral density f = 20 Hz 25 C 2 µv/ Hz Output noise voltage Hz f 0 khz, CSR = Ω CO = 4.7 µf 25 C 4 UNIT V mv Ω mv mv db CO = µf 25 C 328 µvrms CO = 0 µf 25 C 22 PG trip-threshold voltage VO voltage decreasing from above VPG 40 C to 25 C V PG hysteresis voltage 25 C 50 mv 25 C PG output low voltage IPG =2mA.2 ma, VI = 4.2 V V 40 C to 25 C 0.4 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. POST OFFICE BOX DALLAS, TEXAS

10 TPS7Q, TPS733Q, TPS748Q, TPS750Q TPS750 electrical characteristics at I O = ma, V I = 6 V, EN = 0 V, C O = 4.7 µf/csr = Ω, SENSE shorted to OUT (unless otherwise noted) TPS750Q PARAMETER TEST CONDITIONS TJ MIN TYP MAX VI = 6 V, IO = ma 25 C 5 Output voltage 6 V VI V, 5 ma IO 500 ma 40 C to 25 C IO =ma ma, VI = 4.88 V Dropout voltage IO = 0 ma, VI = 4.88 V Pass-element series resistance IO = 500 ma, VI = 4.88 V 25 C C to 25 C 8 25 C C to 25 C C C to 25 C 230 (4.88 V VO)/IO, O, VI = 4.88 V, 25 C IO = 500 ma 40 C to 25 C C 25 Input regulation VI =6VtoV V, 50 µa IO 500 ma mv 40 C to 25 C 32 Output regulation Ripple rejection IO =5mAto500mA 500 ma, IO =50µA to 500 ma, f = 20 Hz 6V VI V 6V VI V IO =50µA IO = 500 ma 25 C C to 25 C C C to 25 C C C to 25 C C C to 25 C 36 Output noise-spectral density f = 20 Hz 25 C 2 µv/ Hz Output noise voltage Hz f 0 khz, CSR = Ω CO = 4.7 µf 25 C 430 UNIT V mv Ω mv mv db CO = µf 25 C 345 µvrms CO = 0 µf 25 C 220 PG trip-threshold voltage VO voltage decreasing from above VPG 40 C to 25 C V PG hysteresis voltage 25 C 53 mv PG output low voltage IPG =2mA.2 ma, VI = 4.25 V 25 C C to 25 C 0.4 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. V POST OFFICE BOX DALLAS, TEXAS 75265

11 TPS7Q, TPS733Q, TPS748Q, TPS750Q electrical characteristics at I O = ma, EN = 0 V, C O = 4.7 µf/csr = Ω, T J = 25 C, SENSE/FB shorted to OUT (unless otherwise noted) PARAMETER Ground current (active mode) EN 0.5 V, 0 ma IO 500 ma TEST CONDITIONS VI = VO + V, TPS7Y, TPS733Y TPS748Y, TPS750Y MIN TYP MAX UNIT 285 µa Output current limit VO = 0, VI = V.2 A PG leakage current Normal operation, VPG = V 0.02 µa Thermal shutdown junction temperature 65 C EN hysteresis voltage 50 mv Minimum VI for active pass element 2.05 V Minimum VI for valid PG IPG = 300 µa.06 V PARAMETER Reference voltage (measured at FB with OUT connected to FB) TEST CONDITIONS TPS7Y MIN TYP MAX UNIT VI = 3.5 V, IO = ma.78 V VI = 2.4 V, 50 µa IO 50 ma 0.7 VI = 2.4 V, 50 ma IO 500 ma 0.83 Pass-element series resistance (see Note 2) VI = 2.9 V, 50 µa IO 500 ma 0.52 Ω Input regulation Output regulation Ripple rejection VI = 3.9 V, 50 µa IO 500 ma 0.32 VI = 5.9 V, 50 µa IO 500 ma 0.23 VI = 2.5 V to V, 50 µa IO 500 ma, See Note 2.5 V VI V, IO = 5 ma to 500 ma, See Note 2.5 V VI V, IO = 50 µa to 500 ma, See Note VI = 3.5 V, IO = 50 µa f = 20 Hz, 8 mv 4 mv 22 mv 59 db Output noise-spectral density VI = 3.5 V, f = 20 Hz 2 µv/ Hz Output noise voltage CO = 4.7 µf 95 VI = 3.5 V, Hz f 0 khz, CO = µf 89 µvrms CSR = Ω CO = 0 µf 74 PG hysteresis voltage VI = 3.5 V, Measured at VFB 2 mv PG output low voltage VI = 2.3 V, IPG = 400 µa 0. V FB input current VI = 3.5 V VI = 3.5 V 0. na CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. Output voltage programmed to 2.5 V with closed-loop configuration (see application information). NOTES:. When VI < 2.9 V and IO > 50 ma simultaneously, pass element rds(on) increases (see Figure 27) to a point such that the resulting dropout voltage prevents the regulator from maintaining the specified tolerance range. 2. To calculate dropout voltage, use equation: VDO = IO rds(on) rds(on) is a function of both output current and input voltage. The parametric table lists rds(on) for VI = 2.4 V, 2.9 V, 3.9 V, and 5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other programmed values, refer to Figure 26. POST OFFICE BOX DALLAS, TEXAS 75265

12 TPS7Q, TPS733Q, TPS748Q, TPS750Q electrical characteristics at I O = ma, EN = 0 V, C O = 4.7 µf/csr = Ω, T J = 25 C, SENSE shorted to OUT (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS TPS733Y MIN TYP MAX Output voltage VI = 4.3 V, IO = ma 3.3 V VI = 3.23 V, IO = ma 0.02 Dropout voltage VI = 3.23 V, IO = 0 ma 47 mv Pass-element series resistance Output regulation VI = 3.23 V, IO = 500 ma 235 (3.23 V VO)/IO, IO = 500 ma VI = 3.23 V, UNIT 0.47 Ω 4.3 V VI V, IO = 5 ma to 500 ma 2 mv 4.3 V VI V, IO = 50 µa to 500 ma 30 mv VI = 4.3 V, IO = 50 µa 54 Ripple rejection f = 20 Hz IO = 500 ma 49 Output noise-spectral density VI = 4.3 V, f = 20 Hz 2 µv/ Hz Output noise voltage VI = 4.3 V, Hz f 0 khz, CSR = Ω CO = 4.7 µf 274 db CO = µf 228 µvrms CO = 0 µf 59 PG hysteresis voltage VI = 4.3 V 35 mv PG output low voltage VI = 2.8 V, IPG = ma 0.22 V PARAMETER TEST CONDITIONS TPS748Y MIN TYP MAX Output voltage VI = 5.85 V, IO = ma 4.85 V VI = 4.75 V, IO = ma 0.08 Dropout voltage VI = 4.75 V, IO = 0 ma 30 mv Pass-element series resistance Output regulation VI = 4.75 V, IO = 500 ma 50 (4.75 V VO)/IO, IO = 500 ma VI = 4.75 V, UNIT 0.32 Ω 5.85 V VI V, IO = 5 ma to 500 ma 2 mv 5.85 V VI V, IO = 50 µa to 500 ma 42 mv VI = 5.85 V, IO = 50 µa 53 Ripple rejection f = 20 Hz IO = 500 ma 50 Output noise-spectral density VI = 5.85 V, f = 20 Hz 2 µv/ Hz Output noise voltage VI = 5.85 V, Hz f 0 khz, CSR = Ω CO = 4.7 µf 4 db CO = µf 328 µvrms CO = 0 µf 22 PG hysteresis voltage VI = 5.85 V 50 mv PG output low voltage VI = 4.2 V, IPG =.2 ma V CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. 2 POST OFFICE BOX DALLAS, TEXAS 75265

13 TPS7Q, TPS733Q, TPS748Q, TPS750Q electrical characteristics at I O = ma, EN = 0 V, C O = 4.7 µf/csr = Ω, T J = 25 C, SENSE shorted to OUT (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS TPS750Y MIN TYP MAX Output voltage VI = 6 V, IO = ma 5 V VI = 4.88 V, IO = ma 0.3 Dropout voltage VI = 4.88 V, IO = 0 ma 27 mv Pass-element series resistance Output regulation VI = 4.88 V, IO = 500 µa 46 (4.88 V VO)/IO, IO = 500 ma VI = 4.88 V, UNIT 0.29 Ω 6 V VI V, IO = 5 ma to 500 ma 30 mv 6 V VI V, IO = 50 µa to 500 ma 45 mv VI = 6 V, IO = 50 µa 55 Ripple rejection f = 20 Hz IO = 500 ma 52 Output noise-spectral density VI = 6 V, f = 20 Hz 2 µv/ Hz Output noise voltage VI = 6V, Hz f 0 khz, CSR = Ω CO = 4.7 µf 430 db CO = µf 345 µvrms CO = 0 µf 220 PG hysteresis voltage VI = 6 V 53 mv PG output low voltage VI = 4.25 V, PG =.2 ma 0.2 V CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. POST OFFICE BOX DALLAS, TEXAS

14 TPS7Q, TPS733Q, TPS748Q, TPS750Q TYPICAL CHARACTERISTICS Table of Graphs FIGURE Output current 5 IQ Quiescent current Input voltage 6 Free-air temperature 7 VDO Dropout voltage Output current 8 VDO Change in dropout voltage Free-air temperature 9 VO Change in output voltage Free-air temperature VO Output voltage Input voltage VO Change in output voltage Input voltage 2 VO Output voltage Output current Ripple rejection Output spectral noise density Frequency Frequency rds(on) Pass-element resistance Input voltage 25 R Divider resistance Free-air temperature 26 II(SENSE) SENSE pin current Free-air temperature 27 VI FB leakage current Free-air temperature 28 Minimum input voltage for active-pass element Free-air temperature 29 Minimum input voltage for valid PG Free-air temperature 30 II(EN) Input current (EN) Free-air temperature 3 Output voltage response from Enable (EN) 32 VPG Power-good (PG) voltage Output voltage 33 CSR Compensation series resistance Output current CSR Compensation series resistance Added ceramic capacitance CSR Compensation series resistance Output current CSR Compensation series resistance Added ceramic capacitance POST OFFICE BOX DALLAS, TEXAS 75265

15 TYPICAL CHARACTERISTICS TPS7Q, TPS733Q, TPS748Q, TPS750Q QUIESCENT CURRENT OUTPUT CURRENT RL = Ω QUIESCENT CURRENT INPUT VOLTAGE µ A Quiescent Current IQ TPS7xx, VI = V TPS750, VI = 6 V TPS748, VI = 5.85 V TPS733, VI = 4.3 V Quiescent Current µ A IQ TPS733 TPS750 TPS748 TPS7 With VO Programmed to 2.5 V IO Output Current ma Figure VI Input Voltage V Figure 6 IQ Quiesent Current µ A TPS748Q QUIESCENT CURRENT FREE-AIR TEMPERATURE VI = VO(nom) + V IO = ma Dropout Voltage V DROPOUT VOLTAGE OUTPUT CURRENT TPS733 TPS748 TPS TA Free-Air Temperature C Figure IO Output Current ma Figure 8 POST OFFICE BOX DALLAS, TEXAS

16 TPS7Q, TPS733Q, TPS748Q, TPS750Q TYPICAL CHARACTERISTICS Change in Dropout Voltage mv CHANGE IN DROPOUT VOLTAGE FREE-AIR TEMPERATURE IO = 0 ma V O Change in Output Voltage mv CHANGE IN OUTPUT VOLTAGE FREE-AIR TEMPERATURE VI = VO(nom) + V IO = ma TA Free-Air Temperature C Figure TA Free-Air Temperature C Figure Output Voltage V V O RL = Ω OUTPUT VOLTAGE INPUT VOLTAGE TPS733 TPS750 TPS7 With VO Programmed to 2.5 V TPS748 V O Change In Output Voltage mv RL = Ω CHANGE IN OUTPUT VOLTAGE INPUT VOLTAGE TPS733 TPS750 TPS VI Input Voltage V Figure VI Input Voltage V Figure 2 6 POST OFFICE BOX DALLAS, TEXAS 75265

17 TYPICAL CHARACTERISTICS TPS7Q, TPS733Q, TPS748Q, TPS750Q TPS7Q OUTPUT VOLTAGE OUTPUT CURRENT VO Programmed to 2.5 V TPS733Q OUTPUT VOLTAGE OUTPUT CURRENT V O Output Voltage V VI = V VI = 3.5 V Output Voltage V V O VI = 4.3 V VI = V IO Output Current ma Figure IO Output Current ma Figure 4 Output Voltage V V O TPS748Q OUTPUT VOLTAGE OUTPUT CURRENT VI = 5.85 V VI = V Output Voltage V V O TPS750Q OUTPUT VOLTAGE OUTPUT CURRENT VI = 6 V VI = V IO Output Current ma Figure IO Output Current ma Figure 6 POST OFFICE BOX DALLAS, TEXAS

18 TPS7Q, TPS733Q, TPS748Q, TPS750Q TYPICAL CHARACTERISTICS 70 TPS7Q RIPPLE REJECTION FREQUENCY 70 TPS733Q RIPPLE REJECTION FREQUENCY Ripple Rejection db VI = 3.5 V CO = 4.7 µf (CSR = Ω) No Input Capacitance VO Programmed to 2.5 V RL = Ω 0 0 K K 0K M M f Frequency Hz RL = 0 kω RL = 500 Ω Ripple Rejection db VI = 3.5 V CO = 4.7 µf (CSR = Ω) No Input Capacitance 0 k k RL = 0 kω RL = 500 Ω 0 k f Frequency Hz RL = Ω M M Figure 7 Figure 8 70 TPS748Q RIPPLE REJECTION FREQUENCY 70 TPS750Q RIPPLE REJECTION FREQUENCY Ripple Rejection db RL = Ω VI = 3.5 V CO = 4.7 µf (CSR = Ω) No Input Capacitance 0 k k Figure 9 RL = 0 kω RL = 500 Ω 0 k f Frequency Hz M M Ripple Rejection db RL = Ω VI = 3.5 V CO = 4.7 µf (CSR = Ω) No Input Capacitance 0 0 k k RL = 0 kω RL = 500 Ω 0 k f Frequency Hz Figure 20 M M 8 POST OFFICE BOX DALLAS, TEXAS 75265

19 TYPICAL CHARACTERISTICS TPS7Q, TPS733Q, TPS748Q, TPS750Q Output Spectral Noise Density µ V/ Hz 0. TPS7Q OUTPUT SPECTRAL NOISE DENSITY FREQUENCY No Input Capacitance VI = 3.5 V VO Programmed to 2.5 V CO = 4.7 µf (CSR = Ω) CO = µf (CSR = Ω) Output Spectral Noise Density µ V/ Hz 0. TPS733Q OUTPUT SPECTRAL NOISE DENSITY FREQUENCY No Input Capacitance VI = 4.3 V CO = µf (CSR = Ω) CO = 4.7 µf (CSR = Ω) CO = 0 µf (CSR = Ω) CO = 0 µf (CSR = Ω) f Frequency Hz f Frequency Hz Figure 2 Figure 22 Output Spectral Noise Density µ V/ Hz 0. TPS748Q OUTPUT SPECTRAL NOISE DENSITY FREQUENCY CO = 0 µf (CSR = Ω) No Input Capacitance VI = 5.85 V CO = µf (CSR = Ω) CO = 4.7 µf (CSR = Ω) k k 0 k f Frequency Hz Output Spectral Noise Density µ V/ Hz 0. TPS750Q OUTPUT SPECTRAL NOISE DENSITY FREQUENCY CO = µf (CSR = Ω) CO = 4.7 µf (CSR = Ω) CO = 0 µf (CSR = Ω) k k 0 k f Frequency Hz No Input Capacitance VI = 6 V Figure 23 Figure 24 POST OFFICE BOX DALLAS, TEXAS

20 TPS7Q, TPS733Q, TPS748Q, TPS750Q TYPICAL CHARACTERISTICS r DS(on) Pass-Element Resistance Ω PASS-ELEMENT RESISTANCE INPUT VOLTAGE IO = 500 ma IO = 0 ma VI(FB) =.2 V Ω R Divider Resistance M DIVIDER RESISTANCE FREE-AIR TEMPERATURE TPS748 TPS750 TPS733 VI = VO(nom) + V VI(sense) = VO(nom) VI Input Voltage V Figure TA Free-Air Temperature C Figure 26 II(sense) Sense Pin Current µ A FIXED-OUTPUT VERSIONS SENSE PIN CURRENT FREE-AIR TEMPERATURE VI = VO(nom) + V VI(sense) = VO(nom) FB Leakage Current na VFB = 2.5 V ADJUSTABLE VERSION FB LEAKAGE CURRENT FREE-AIR TEMPERATURE TA Free-Air Temperature C Figure TA Free-Air Temperature C Figure POST OFFICE BOX DALLAS, TEXAS 75265

21 TYPICAL CHARACTERISTICS TPS7Q, TPS733Q, TPS748Q, TPS750Q MINIMUM INPUT VOLTAGE FOR ACTIVE PASS ELEMENT FREE-AIR TEMPERATURE RL = 500 Ω. MINIMUM INPUT VOLTAGE FOR VALID POWER GOOD (PG) FREE-AIR TEMPERATURE Minimum Input Voltage V ÁÁ V I Minimum Input Voltage V ÁÁ V I TA Free-Air Temperature C Figure TA Free-Air Temperature C Figure 30 EN INPUT CURRENT FREE-AIR TEMPERATURE 0 90 VI = VI(EN) = V 80 Input Current na II(EN) TA Free-Air Temperature C Figure 3 POST OFFICE BOX DALLAS, TEXAS

22 TPS7Q, TPS733Q, TPS748Q, TPS750Q TYPICAL CHARACTERISTICS OUTPUT VOLTAGE RESPONSE FROM ENABLE (EN) Output Voltage V VO(nom) V O RL = 500 Ω CO = 4.7 µf (ESR = Ω) No Input Capacitance EN Voltage V Time µs Figure 32 Power-Good (PG) Voltage V ÁÁ V PG POWER-GOOD (PG) VOLTAGE OUTPUT VOLTAGE PG Pulled Up to 5 V With 5 kω VO Output Voltage (VO as a percent of VO(nom)) % Figure POST OFFICE BOX DALLAS, TEXAS 75265

23 TYPICAL CHARACTERISTICS TPS7Q, TPS733Q, TPS748Q, TPS750Q CSR Compensation Series Resistance Ω 0 TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE OUTPUT CURRENT VI = VO(nom) + V No Input Capacitance CO = 4.7 µf No Added Ceramic Capacitance Region of Instability Region of Instability CSR Compensation Series Resistance Ω 0 TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE OUTPUT CURRENT VI = VO(nom) + V No Input Capacitance CO = 4.7 µf µf of Ceramic Capacitance Region of Instability Region of Instability IO Output Current ma Figure IO Output Current ma Figure 35 CSR Compensation Series Resistance Ω 0 TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE ADDED CERAMIC CAPACITANCE VI = VO(nom) + V No Input Capacitance IO= 0 ma CO = 4.7 µf Region of Instability Region of Instability CSR Compensation Series Resistance Ω 0 TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE ADDED CERAMIC CAPACITANCE VI = VO(nom) + V No Input Capacitance IO= 500 ma CO = 4.7 µf Region of Instability Region of Instability Ceramic Capacitance µf Figure Ceramic Capacitance µf Figure 37 POST OFFICE BOX DALLAS, TEXAS

24 TPS7Q, TPS733Q, TPS748Q, TPS750Q TYPICAL CHARACTERISTICS CSR Compensation Series Resistance Ω TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE OUTPUT CURRENT Region of Instability VI = VO(nom) + V No Input Capacitance CO = µf No Ceramic Capacitance Compensation Series Resistance Ω CSR TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE OUTPUT CURRENT VI = VO(nom) + V No Input Capacitance CO = µf µf of Added Ceramic Capacitance Region of Instability IO Output Current ma Figure IO Output Current ma Figure 39 CSR Compensation Series Resistance Ω TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE ADDED CERAMIC CAPACITANCE VI = VO(nom) + V No Input Capacitance CO = µf IO = 0 ma Region of Instability CSR Compensation Series Resistance Ω TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE ADDED CERAMIC CAPACITANCE VI = VO(nom) + V No Input Capacitance CO = µf IO = 500 ma Region of Instability Ceramic Capacitance µf Figure Ceramic Capacitance µf Figure 4 CSR values below 0. Ω are not recommended. 24 POST OFFICE BOX DALLAS, TEXAS 75265

25 TYPICAL CHARACTERISTICS TPS7Q, TPS733Q, TPS748Q, TPS750Q VI IN OUT To Load SENSE EN GND + CO CSR Ccer RL Ceramic capacitor Figure 42. Test Circuit for Typical Regions of Stability (Figures 34 through 4) POST OFFICE BOX DALLAS, TEXAS

26 TPS7Q, TPS733Q, TPS748Q, TPS750Q APPLICATION INFORMATION The TPS7xx series of low-dropout (LDO) regulators is designed to overcome many of the shortcomings of earlier-generation LDOs, while adding features such as a power-saving shutdown mode and a power-good indicator. The TPS7xx family includes three fixed-output voltage regulators: the TPS733 (3.3 V), the TPS748 (4.85 V), and the TPS750 (5 V). The family also offers an adjustable device, the TPS7 (adjustable from.2 V to 9.75 V). device operation The TPS7xx, unlike many other LDOs, features very low quiescent currents that remain virtually constant even with varying loads. Conventional LDO regulators use a pnp-pass element, the base current of which is directly proportional to the load current through the regulator (I B = I C /β). Close examination of the data sheets reveals that those devices are typically specified under near no-load conditions; actual operating currents are much higher as evidenced by typical quiescent current versus load current curves. The TPS7xx uses a PMOS transistor to pass current; because the gate of the PMOS element is voltage driven, operating currents are low and invariable over the full load range. The TPS7xx specifications reflect actual performance under load. Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into dropout. The resulting drop in β forces an increase in I B to maintain the load. During power up, this translates to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems, it means rapid battery discharge when the voltage decays below the minimum required for regulation. The TPS7xx quiescent current remains low even when the regulator drops out, eliminating both problems. Included in the TPS7xx family is a 4.85-V regulator, the TPS748. Designed specifically for 5-V cellular systems, its 4.85-V output, regulated to within ± 2%, allows for operation within the low-end limit of 5-V systems specified to ± 5% tolerance; therefore, maximum regulated operating lifetime is obtained from a battery pack before the device drops out, adding crucial talk minutes between charges. The TPS7xx family also features a shutdown mode that places the output in the high-impedance state (essentially equal to the feedback-divider resistance) and reduces quiescent current to under 2 µa. If the shutdown feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulated output voltage is reestablished in typically 20 µs. minimum load requirements The TPS7xx family is stable even at zero load; no minimum load is required for operation. SENSE-pin connection The SENSE pin of fixed-output devices must be connected to the regulator output for proper functioning of the regulator. Normally, this connection should be as short as possible; however, the connection can be made near a critical circuit (remote sense) to improve performance at that point. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier through a resistor-divider network and noise pickup feeds through to the regulator output. Routing the SENSE connection to minimize/avoid noise pickup is essential. Adding an RC network between SENSE and OUT to filter noise is not recommended because it can cause the regulator to oscillate. external capacitor requirements An input capacitor is not required; however, a ceramic bypass capacitor (0.047 pf to 0. µf) improves load transient response and noise rejection if the TPS7xx is located more than a few inches from the power supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise times are anticipated. 26 POST OFFICE BOX DALLAS, TEXAS 75265

27 external capacitor requirements (continued) APPLICATION INFORMATION TPS7Q, TPS733Q, TPS748Q, TPS750Q As with most LDO regulators, the TPS7xx family requires an output capacitor for stability. A -µf solid-tantalum capacitor connected from the regulator output to ground is sufficient to ensure stability over the full load range (see Figure 43). Adding high-frequency ceramic or film capacitors (such as power-supply bypass capacitors for digital or analog ICs) can cause the regulator to become unstable unless the ESR of the tantalum capacitor is less than.2 Ω over temperature. Where component height and/or mounting area is a problem, physically smaller, -µf devices can be screened for ESR. Figures 34 through 4 show the stable regions of operation using different values of output capacitance with various values of ceramic load capacitance. In applications with little or no high-frequency bypass capacitance (< 0.2 µf), the output capacitance can be reduced to 4.7 µf, provided ESR is maintained between the values shown in figures 34 through 4. Because minimum capacitor ESR is seldom if ever specified, it may be necessary to add a 0.5-Ω to -Ω resistor in series with the capacitor and limit ESR to.5 Ω maximum. TPS7xx VI C 0. µf 50 V IN IN IN EN PG SENSE OUT OUT GND PG 250 kω VO + CO µf ESR TPS733, TPS748, TPS750 (fixed-voltage options) Figure 43. Typical Application Circuit programming the TPS7 adjustable LDO regulator Programming the adjustable regulators is accomplished using an external resistor divider as shown in Figure 44. The equation governing the output voltage is: V V. R. O ref R2 where V ref = reference voltage,.78 V typ POST OFFICE BOX DALLAS, TEXAS

28 TPS7Q, TPS733Q, TPS748Q, TPS750Q APPLICATION INFORMATION programming the TPS7 adjustable LDO regulator (continued) Resistors R and R2 should be chosen for approximately 7-µA divider current. A recommended value for R2 is 69 kω with R adjusted for the desired output voltage. Smaller resistors can be used, but offer no inherent advantage and consume more power. Larger values of R and R2 should be avoided as leakage currents at FB introduce an error. Solving equation for R yields a more useful equation for choosing the appropriate resistance: R. V O V ref. R2 >2.7 V VI 0. µf <0.5V TPS7 IN PG EN OUT FB GND Power-Good Indicator 250 kω VO + R R2 OUTPUT VOLTAGE 2.5 V 3.3 V 3.6 V 4 V 5 V 6.4 V OUTPUT VOLTAGE PROGRAMMING GUIDE R R UNIT kω kω kω kω kω kω power-good indicator Figure 44. TPS7 Adjustable LDO Regulator Programming The TPS7xx features a power-good (PG) output that can be used to monitor the status of the regulator. The internal comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal regulated value, the PG output transistor turns on, taking the signal low. The open-drain output requires a pullup resistor. If not used, it can be left floating. PG can be used to drive power-on reset circuitry or as a low-battery indicator. PG does not assert itself when the regulated output voltage falls outside the specified 2% tolerance, but instead reports an output voltage low, relative to its nominal regulated value. regulator protection The TPS7xx PMOS-pass transistor has a built-in back diode that safely conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS7xx also features internal current limiting and thermal protection. During normal operation, the TPS7xx limits output current to approximately A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 65 C, thermal-protection circuitry shuts it down. Once the device has cooled, regulator operation resumes. 28 POST OFFICE BOX DALLAS, TEXAS 75265

29 TPS7Q, TPS733Q, TPS748Q, TPS750Q D (R-PDSO-G**) 4 PIN SHOWN MECHANICAL DATA PLASTIC SMALL-OUTLINE PACKAGE (,27) (0,5) 0.04 (0,35) (0,25) M PINS ** DIM A MAX A MIN (5,00) 0.89 (4,80) (8,75) (8,55) (,00) (9,80) 0.57 (4,00) 0.50 (3,8) (6,20) (5,80) (0,20) NOM 7 Gage Plane A 0.0 (0,25) (,2) 0.06 (0,40) Seating Plane (,75) MAX 0.0 (0,25) (0,) (0,) / B 03/95 NOTES: B. All linear dimensions are in inches (millimeters). C. This drawing is subject to change without notice. D. Body dimensions do not include mold flash or protrusion, not to exceed (0,5). E. Four center pins are connected to die mount pad. F. Falls within JEDEC MS-02 POST OFFICE BOX DALLAS, TEXAS

30 TPS7Q, TPS733Q, TPS748Q, TPS750Q P (R-PDIP-T8) MECHANICAL DATA PLASTIC DUAL-IN-LINE PACKAGE (,60) (9,02) (6,60) (6,) (,78) MAX (0,5) MIN 0.3 (7,87) (7,37) (5,08) MAX Seating Plane 0.25 (3,8) MIN 0.0 (2,54) (0,53) 0.05 (0,38) 0.0 (0,25) M 0.0 (0,25) NOM / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS POST OFFICE BOX DALLAS, TEXAS 75265

31 TPS7Q, TPS733Q, TPS748Q, TPS750Q PW (R-PDSO-G**) 4 PIN SHOWN MECHANICAL DATA PLASTIC SMALL-OUTLINE PACKAGE 0,32 0,65 0,3 M 0, ,50 4,30 6,70 6, 0,5 NOM Gage Plane A ,25 0,75 0,50 Seating Plane,20 MAX 0, MIN 0, DIM PINS ** A MAX 3, 5, 5, 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, / D /95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDEC MO-53 POST OFFICE BOX DALLAS, TEXAS

32 PACKAGE OPTION ADDENDUM 7-Jun-2008 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty TPS7QD ACTIVE SOIC D 8 75 Green (RoHS & TPS7QDG4 ACTIVE SOIC D 8 75 Green (RoHS & TPS7QDR ACTIVE SOIC D Green (RoHS & TPS7QDRG4 ACTIVE SOIC D Green (RoHS & TPS7QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) TPS7QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) TPS7QPW ACTIVE TSSOP PW Green (RoHS & TPS7QPWG4 ACTIVE TSSOP PW Green (RoHS & Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TPS7QPWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI TPS7QPWR ACTIVE TSSOP PW Green (RoHS & TPS7QPWRG4 ACTIVE TSSOP PW Green (RoHS & TPS733QD ACTIVE SOIC D 8 75 Green (RoHS & TPS733QDG4 ACTIVE SOIC D 8 75 Green (RoHS & TPS733QDR ACTIVE SOIC D Green (RoHS & TPS733QDRG4 ACTIVE SOIC D Green (RoHS & TPS733QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) TPS733QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) TPS733QPW ACTIVE TSSOP PW Green (RoHS & TPS733QPWG4 ACTIVE TSSOP PW Green (RoHS & TPS733QPWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI TPS733QPWPLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI TPS733QPWR ACTIVE TSSOP PW Green (RoHS & TPS733QPWRG4 ACTIVE TSSOP PW Green (RoHS & TPS748QD ACTIVE SOIC D 8 75 Green (RoHS & TPS748QDG4 ACTIVE SOIC D 8 75 Green (RoHS & TPS748QDR ACTIVE SOIC D Green (RoHS & N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type Addendum-Page

33 PACKAGE OPTION ADDENDUM 7-Jun-2008 Orderable Device Status () Package Type Package Drawing Pins Package Qty TPS748QDRG4 ACTIVE SOIC D Green (RoHS & TPS748QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) TPS748QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TPS748QPWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI TPS750QD ACTIVE SOIC D 8 75 Green (RoHS & TPS750QDG4 ACTIVE SOIC D 8 75 Green (RoHS & TPS750QDR ACTIVE SOIC D Green (RoHS & TPS750QDRG4 ACTIVE SOIC D Green (RoHS & TPS750QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) TPS750QPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) TPS750QPW ACTIVE TSSOP PW Green (RoHS & TPS750QPWG4 ACTIVE TSSOP PW Green (RoHS & TPS750QPWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI TPS750QPWR ACTIVE TSSOP PW Green (RoHS & TPS750QPWRG4 ACTIVE TSSOP PW Green (RoHS & N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either ) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take Addendum-Page 2

34 PACKAGE OPTION ADDENDUM 7-Jun-2008 reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

35 PACKAGE MATERIALS INFORMATION -Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Reel Diameter Width (mm) W (mm) A0 (mm) B0 (mm) K0 (mm) P (mm) TPS7QDR SOIC D Q TPS7QPWR TSSOP PW Q TPS733QDR SOIC D Q TPS733QPWR TSSOP PW Q TPS748QDR SOIC D Q TPS750QDR SOIC D Q TPS750QPWR TSSOP PW Q W (mm) Pin Quadrant Pack Materials-Page

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