CD4051B, CD4052B, CD4053B

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CD, CD, CD Data sheet acquired from Harris Semiconductor SCHSD ugust - Revised March [ /Title (CD, CD, CD ) /Subject CMOS nalog ultilexrs/dem ltiplexrs with ogic evel onverion) /uthor ) /Keyords

1 CD, CD, CD Data sheet acquired from Harris Semiconductor SCHSD ugust - Revised March [ /Title (CD, CD, CD ) /Subject CMOS nalog ultilexrs/dem ltiplexrs with ogic evel onverion) /uthor ) /Keyords Harris emionducor, D CMOS nalog Multiplexers/Demultiplexers with Logic Level Conversion The CD, CD, and CD analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. Control of analog signals up to P-P can be achieved by digital signal amplitudes of. to (if - =, a - of up to can be controlled; for - level differences above, a - of at least. is required). For example, if = +., =, and = -., analog signals from -. to +. can be controlled by digital inputs of to. These multiplexer circuits dissipate extremely low quiescent power over the full - and - supply-voltage ranges, independent of the logic state of the control signals. When a logic is present at the inhibit input terminal, all channels are off. The CD is a single -Channel multiplexer having three binary control inputs,,, and C, and an inhibit input. The three binary signals select of channels to be turned on, and connect one of the inputs to the output. The CD is a differential -Channel multiplexer having two binary control inputs, and, and an inhibit input. The two binary input signals select of pairs of channels to be turned on and connect the analog inputs to the outputs. The CD is a triple -Channel multiplexer having three separate digital control inputs,,, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole, double-throw configuration. When these devices are used as demultiplexers, the CHNNEL terminals are the outputs and the COMMON OUT/IN terminals are the inputs. Ordering Information PRT NUMER TEMP. RNGE ( o C) PCKGE Features Wide Range of Digital and nalog Signal Levels - Digital to - nalog P-P Low ON Resistance, Ω (Typ) Over P-P Signal Input Range for - = High OFF Resistance, Channel Leakage of ±p (Typ) at - = Logic-Level Conversion for Digital ddressing Signals of to ( - = to ) to Switch nalog Signals to P-P ( - = ) Matched Switch Characteristics, r ON = Ω (Typ) for - = ery Low Quiescent Power Dissipation Under ll Digital- Control Input and Supply Conditions,.µW (Typ) at - = - = inary ddress Decoding on Chip, and Parametric Ratings % Tested for Quiescent Current at Maximum Input Current of µ at Over Full Package Temperature Range, n at and o C reak-efore-make Switching Eliminates Channel Overlap pplications nalog and Digital Multiplexing and Demultiplexing /D and D/ Conversion Signal Gating CDF, CDF, CDF CDE, CDE, CDE - to Ld CERMIC DIP - to Ld PDIP CDM, CDNS - to Ld SOIC CDPW, CDPW, CDPW - to Ld TSSOP CUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright, Texas Instruments Incorporated

2 CD, CD, CD Pinouts CD (PDIP, CDIP, SOIC, TSSOP) TOP IEW CD (PDIP, CDIP, TSSOP) TOP IEW COM OUT/IN INH CHNNELS CHNNELS CHNNELS Y CHNNELS COMMON Y OUT/IN Y CHNNELS INH X CHNNELS COMMON X OUT/IN X CHNNELS C CD (PDIP, CDIP, TSSOP) TOP IEW by bx OUT/IN bx OR by cy OUT/IN ax OR ay OUT/IN CX OR CY CX ay ax INH C Functional lock Diagrams CD CHNNEL C LOGIC LEEL CONERSION INRY TO OF DECODER WITH INHIIT COMMON OUT/IN INH ll inputs are protected by standard CMOS protection network.

3 CD, CD, CD Functional lock Diagrams (Continued) CD X CHNNELS INH LOGIC LEEL CONERSION INRY TO OF DECODER WITH INHIIT COMMON X OUT/IN COMMON Y OUT/IN Y CHNNELS CD LOGIC LEEL CONERSION INRY TO OF DECODERS WITH INHIIT cy cx by bx ay ax COMMON OUT/IN ax OR ay COMMON OUT/IN bx OR by C COMMON OUT/IN cx OR cy INH ll inputs are protected by standard CMOS protection network.

4 CD, CD, CD INPUT STTES TRUTH TLES INHIIT C ON CHNNEL(S) CD X X X None CD INHIIT x, y x, y x, y x, y X X None CD INHIIT OR OR C ax or bx or cx ay or by or cy X None X = Don t Care

5 CD, CD, CD bsolute Maximum Ratings Supply oltage (+ to -) oltages Referenced to Terminal to DC Input oltage Range to +. DC Input Current, ny One Input ±m Operating Conditions Temperature Range o C to o C Thermal Information Thermal Resistance (Typical, Note ) θ J ( o C/W) θ JC ( o C/W) E Package N/ F Package D Package N/ NS Package N/ PW Package N/ Maximum Junction Temperature (Ceramic Package) o C Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to o C Maximum Lead Temperature (Soldering s) o C (SOIC - Lead Tips Only) CUTION: Stresses above those listed in bsolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. The package thermal impedance is calculated in accordance with JESD. Electrical Specifications Common Conditions Here: If Whole Table is For the Full Temp. Range, SUPPLY = ±, = +, = Ω, Unless Otherwise Specified (Note ) CONDITIONS LIMITS T INDICTED TEMPERTURES ( o C) PRMETER IS () () () () - - MIN TYP MX UNITS SIGNL INPUTS ( IS ) ND S ( OS ) Quiescent Device Current, I DD Max µ µ µ µ Drain to Source ON Resistance r ON Max IS Change in ON Resistance (etween ny Two Channels), r ON - - Ω - - Ω - - Ω Ω Ω Ω OFF Channel Leakage Current: ny Channel OFF (Max) or LL Channels OFF (Common OUT/IN) (Max) - ± (Note ) ± (Note ) - ±. ± (Note ) n Capacitance: Input, C IS pf Output, C OS CD pf CD pf CD pf Feedthrough C IOS pf Propagation Delay Time (Signal Input to Output = kω, C L = pf, t r, t f = ns ns ns ns

6 CD, CD, CD Electrical Specifications Common Conditions Here: If Whole Table is For the Full Temp. Range, SUPPLY = ±, = +, = Ω, Unless Otherwise Specified (Continued) (Note ) CONDITIONS LIMITS T INDICTED TEMPERTURES ( o C) PRMETER IS () () () () - - MIN TYP MX UNITS CONTROL (DDRESS OR INHIIT), C Input Low oltage, IL, Max Input High oltage, IH, Min IL = through kω; IH = through kω =, = kω to, I IS < µ on ll OFF Channels Input Current, I IN (Max) IN =, ±. ±. ± ± - ± - ±. µ Propagation Delay Time: ddress-to-signal OUT (Channels ON or OFF) See Figures,, t r, t f = ns, C L = pf, = kω ns ns ns ns Propagation Delay Time: Inhibit-to-Signal OUT (Channel Turning ON) See Figure t r, t f = ns, C L = pf, = kω ns ns ns Propagation Delay Time: Inhibit-to-Signal OUT (Channel Turning OFF) See Figure Input Capacitance, C IN (ny ddress or Inhibit Input) t r, t f = ns, C L = pf, = kω ns ns ns ns ns pf NOTE:. Determined by minimum feasible leakage measurement for automatic testing. Electrical Specifications TEST CONDITIONS LIMITS PRMETER IS () () (kω) TYP UNITS Cutoff (-d) Frequency Channel ON (Sine Wave Input) (Note ) OS at Common OUT/IN CD MHz =, CD MHz Log OS = d IS CD MHz OS at ny Channel MHz

7 CD, CD, CD Electrical Specifications TEST CONDITIONS LIMITS PRMETER IS () () (kω) TYP UNITS Total Harmonic Distortion, THD (Note ). % (Note ). % (Note ). % =, f IS = khz Sine Wave % -d Feedthrough Frequency (ll Channels OFF) -d Signal Crosstalk Frequency (Note ) OS at Common OUT/IN CD MHz =, CD MHz CD MHz OS at ny Channel MHz (Note ) etween ny Channels MHz =, Log OS = d IS Log OS = d IS etween Sections, CD Only Measured on Common MHz Measured on ny Channel MHz etween ny Two Sections, CD Only In Pin, Out Pin. MHz In Pin, Out Pin MHz ddress-or-inhibit-to-signal Crosstalk - (Note ) =, =,t r,t f = ns, CC = - (Square Wave) m PEK m PEK NOTES:. Peak-to-Peak voltage symmetrical about. oth ends of channel Typical Performance Curves r ON, CHNNEL ON RESISTNCE (Ω) - = T = o C T = o C T = - o C r ON, CHNNEL ON RESISTNCE (Ω) - = T = o C T = o C T = - o C IS, INPUT SIGNL OLTGE () FIGURE. CHNNEL ON RESISTNCE vs INPUT SIGNL OLTGE (LL TYPES) IS, INPUT SIGNL OLTGE () FIGURE. CHNNEL ON RESISTNCE vs INPUT SIGNL OLTGE (LL TYPES)

8 CD, CD, CD Typical Performance Curves (Continued) r ON, CHNNEL ON RESISTNCE (Ω) T = o C - = IS, INPUT SIGNL OLTGE () r ON, CHNNEL ON RESISTNCE (Ω) - = T = o C IS, INPUT SIGNL OLTGE () T = o C T = - o C FIGURE. CHNNEL ON RESISTNCE vs INPUT SIGNL OLTGE (LL TYPES) FIGURE. CHNNEL ON RESISTNCE vs INPUT SIGNL OLTGE (LL TYPES) OS, SIGNL OLTGE () = = = - T = o C = kω, = kω kω Ω Ω IS, INPUT SIGNL OLTGE () P D, POWER DISSIPTION PCKGE (µw) T = o C TEST CIRCUIT LTERNTING O DD ND I PTTERN /D C L = pf f CD C DD = Ω CD = = Ω C L C L = pf SWITCHING FREQUENCY (khz) FIGURE. ON CHRCTERISTICS FOR OF CHNNELS (CD) FIGURE. DYNMIC POWER DISSIPTION vs SWITCHING FREQUENCY (CD) P D, POWER DISSIPTION PCKGE (µw) T = o C LTERNTING O ND I PTTERN C L = pf = = C L = pf = Ω SWITCHING FREQUENCY (khz) f TEST CIRCUIT /D CD DD Ω C L CD P D, POWER DISSIPTION PCKGE (µw) T = o C LTERNTING O ND I PTTERN C L = pf C L = pf = Ω = = TEST CIRCUIT f Ω SWITCHING FREQUENCY (khz) CD C L FIGURE. DYNMIC POWER DISSIPTION vs SWITCHING FREQUENCY (CD) FIGURE. DYNMIC POWER DISSIPTION vs SWITCHING FREQUENCY (CD)

9 CD, CD, CD Test Circuits and Waveforms = =. = =. = = = = = () = -. = - = - () (C) (D) NOTE: The DDRESS (digital-control inputs) and INHIIT logic levels are: = and =. The analog signal (through the ) may swing from to. FIGURE. TYPICL IS OLTGES t r = ns t f = ns t r = ns t f = ns % % % TURN-ON TIME % % % % % % % % % % % % TURN-OFF TIME % t PHZ % TURN-OFF TIME % TURN-ON TIME FIGURE. WEFORMS, CHNNEL EING TURNED ON ( = kω) FIGURE. WEFORMS, CHNNEL EING TURNED OFF ( = kω) I DD I DD I DD CD CD CD FIGURE. OFF CHNNEL LEKGE CURRENT - NY CHNNEL OFF

10 CD, CD, CD Test Circuits and Waveforms (Continued) I DD I DD I DD CD CD CD FIGURE. OFF CHNNEL LEKGE CURRENT - LL CHNNELS OFF DD C L C L R C L L EE DD EE DD EE SS CLOCK SS CLOCK IN IN CLOCK IN CD CD CD FIGURE. PROPGTION DELY - DDRESS INPUT TO SIGNL CLOCK IN pf SS CLOCK IN pf RL pf CLOCK IN t PHL ND t PLH CD t PHL ND t SS PLH CD t PHL ND t SS PLH CD FIGURE. PROPGTION DELY - INHIIT INPUT TO SIGNL µ K IH IL K CD IH MESURE < µ ON LL OFF CHNNELS (e.g., CHNNEL ) IL IH IL CD K K µ IH IL MESURE < µ ON LL OFF CHNNELS (e.g., CHNNEL x) IH IL K CD K µ IH IL MESURE < µ ON LL OFF CHNNELS (e.g., CHNNEL by) FIGURE. INPUT OLTGE TEST CIRCUITS (NOISE IMMUNITY)

11 CD, CD, CD Test Circuits and Waveforms (Continued) CD CD CD kω ON KEITHLEY DIGITL MULTIMETER kω RNGE H.P. MOSELEY Y X X-Y PLOTTER FIGURE. QUIESCENT DEICE CURRENT FIGURE. CHNNEL ON RESISTNCE MESUREMENT CIRCUIT CD CD NOTE: Measure inputs sequentially, to both and connect all unused inputs to either or. CD NOTE: Measure inputs sequentially, to both and connect all unused inputs to either or. FIGURE. INPUT CURRENT P-P OFF CHNNEL K RF M COMMON CHNNEL ON CHNNEL OFF RF M P-P CHNNEL OFF CHNNEL ON RF M FIGURE. FEEDTHROUGH (LL TYPES) FIGURE. CROSSTLK ETWEEN NY TWO CHNNELS (LL TYPES) P-P CHNNEL IN X ON OR OFF CHNNEL IN Y ON OR OFF RF M FIGURE. CROSSTLK ETWEEN DULS OR TRIPLETS (CD, CD)

12 CD, CD, CD Test Circuits and Waveforms (Continued) DIFFERENTIL SIGNLS CD CD COMMUNICTIONS LINK DIFF. MPLIFIER/ LINE DRIER DIFF. RECEIER DIFF. MULTIPLEXING DEMULTIPLEXING FIGURE. TYPICL TIME-DIISION PPLICTION OF THE CD Special Considerations In applications where separate power sources are used to drive and the signal inputs, the current capability should exceed / ( = effective external load). This provision avoids permanent current flow or clamp action on the supply when power is applied or removed from the CD, CD or CD. C C CD INH D E E / CD Q Q Q C INH CD COMMON C CD INH FIGURE. -TO- MUX DDRESSING

13 IMPORTNT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. ll products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright, Texas Instruments Incorporated

CD54/74HC4051, CD54/74HCT4051, CD54/74HC4052, CD74HCT4052, CD54/74HC4053, CD74HCT4053

Data sheet acquired from Harris Semiconductor SCHS122B November 1997 - Revised May 2000 CD54/74HC4051, CD54/74HCT4051, CD54/74HC4052, CD74HCT4052, CD54/74HC4053, CD74HCT4053 High Speed CMOS Logic Analog