74AC00 74ACT00 Quad 2-Input NAND Gate
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1 Quad 2-Input NAND Gate General Description The AC/ACT00 contains four 2-input NAND gates. Ordering Code: Features I CC reduced by 50% Outputs source/sink 24 ma ACT00 has TTL-compatible inputs November 1988 Revised February 2005 Order Number Package Number Package Description 74AC00SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74AC00SCX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74AC00SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC00PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74AC00PC_NL N14A Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74ACT00SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ACT00SCX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ACT00SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT00PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering form. PC not available in Tape and Reel. Pb-Free package per JEDEC J-STD-020B. Note 1: _NL indicates Pb-Free package (per JEDEC J-STD-020B). Use this number to order device. 74AC00 74ACT00 Quad 2-Input NAND Gate Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Pin Names A n, B n O n Description Inputs Outputs FACT is a trademark of Fairchild Semiconductor Corporation Fairchild Semiconductor Corporation DS
2 Absolute Maximum Ratings(Note 2) Supply Voltage (V CC ) 0.5V to 7.0V DC Input Diode Current (I IK ) V I 0.5V 20 ma V I V CC 0.5V 20 ma DC Input Voltage (V I ) 0.5V to V CC 0.5V DC Output Diode Current (I OK ) V O 0.5V 20 ma V O V CC 0.5V 20 ma DC Output Voltage (V O ) 0.5V to V CC 0.5V DC Output Source or Sink Current (I O ) r50 ma DC V CC or Ground Current per Output Pin (I CC or I GND ) r50 ma Storage Temperature (T STG ) 65qC to 150qC Junction Temperature (T J ) PDIP 140qC DC Electrical Characteristics for AC Recommended Operating Conditions Supply Voltage (V CC ) AC 2.0V to 6.0V ACT 4.5V to 5.5V Input Voltage (V I ) 0V to V CC Output Voltage (V O ) 0V to V CC Operating Temperature (T A ) 40qC to 85qC Minimum Input Edge Rate ('V/'t) AC Devices V IN from 30% to 70% of V CC V 3.3V, 4.5V, 5.5V 125 mv/ns Minimum Input Edge Rate ('V/'t) ACT Devices V IN from 0.8V to 2.0V V 4.5V, 5.5V 125 mv/ns Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. Symbol Parameter Units Conditions (V) Typ Guaranteed Limits V IH Minimum HIGH Level V OUT 0.1V Input Voltage V or V CC 0.1V V IL Maximum LOW Level V OUT 0.1V Input Voltage V or V CC 0.1V V OH Minimum HIGH Level Output Voltage V I OUT 50 PA I OH 12 ma V I OH 24 ma I OH 24 ma (Note 3) V OL Maximum LOW Level Output Voltage V I OUT 50 PA I OL 12 ma V I OL 24 ma I OL 24 ma (Note 3) I IN Maximum Input 5.5 r0.1 r1.0 PA V I V CC, GND (Note 4) Leakage Current I OLD Minimum Dynamic ma V OLD 1.65V Max I OHD Output Current (Note 5) ma V OHD 3.85V Min I CC Maximum Quiescent Supply Current PA V IN V CC or GND (Note 4) Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: I IN and I 3.0V are guaranteed to be less than or equal to the respective 5.5V V CC. Note 5: Maximum test duration 2.0 ms, one output loaded at a time. 2
3 DC Electrical Characteristics for ACT Symbol Parameter Units Conditions (V) Typ Guaranteed Limits V IH Minimum HIGH Level V OUT 0.1V V Input Voltage or V CC 0.1V V IL Maximum LOW Level V OUT 0.1V V Input Voltage or V CC 0.1V V OH Minimum HIGH Level V I OUT 50 PA Output Voltage AC00 74ACT I OH 24 ma V I OH 24 ma (Note 6) V OL Maximum LOW Level Output Voltage V I OUT 50 PA V I OL 24 ma I OL 24 ma (Note 6) I IN Maximum Input 5.5 r0.1 r1.0 PA V I V CC, GND Leakage Current I CCT Maximum I CC /Input ma V I V CC 2.1V I OLD Minimum Dynamic ma V OLD 1.65V Max I OHD Output Current (Note 7) ma V OHD 3.85V Min I CC Maximum Quiescent PA V IN V CC Supply Current or GND Note 6: All outputs loaded; thresholds on input associated with output under test. Note 7: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC Symbol Parameter (V) C L 50 pf C L 50 pf Units (Note 8) Min Typ Max Min Max t PLH Propagation Delay ns t PHL Propagation Delay ns Note 8: Voltage Range 3.3 is 3.3V r 0.3V Voltage Range 5.0 is 5.0V r 0.5V AC Electrical Characteristics for ACT Symbol Parameter (V) C L 50 pf C L 50 pf Units (Note 9) Min Typ Max Min Max t PLH Propagation Delay ns t PHL Propagation Delay ns Note 9: Voltage Range 5.0 is 5.0V r0.5v Capacitance Symbol Parameter Typ Units Conditions C IN Input Capacitance 4.5 pf V CC Open C PD Power Dissipation Capacitance 30.0 pf V CC 5.0V 3
4 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 4
5 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 74AC00 74ACT00 Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5
6 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 6
7 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 74AC00 74ACT00 Quad 2-Input NAND Gate 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness
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