74AC244 74ACT244 Octal Buffer/Line Driver with 3-STATE Outputs
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1 Octal Buffer/Line Driver with 3-STATE Outputs General Description The AC/ACT244 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus-oriented tramitter/receiver which provides improved PC board deity. Ordering Code: Features Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. Logic Symbol IEEE/IEC November 1988 Revised November 1999 I CC and I OZ reduced by 50% 3-STATE outputs drive bus lines or buffer memory address registers Outputs source/sink 24 ma ACT244 has TTL-compatible inputs Order Number Package Number Package Description 74AC244SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, Wide Body 74AC244SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC244MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC244PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, Wide 74ACT244SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, Wide Body 74ACT244SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT244MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ACT244MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT244PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, Wide Pin Descriptio Pin Names OE 1, OE 2 I 0 I 7 O 0 O 7 Description 3-STATE Output Enable Inputs Inputs Outputs 74AC244 74ACT244 Octal Buffer/Line Driver with 3-STATE Outputs Truth Tables Connection Diagram Inputs Outputs OE 1 I n (Pi 12, 14, 16, 18) L L L L H H H X Z Inputs Outputs OE 2 I n (Pi 3, 5, 7, 9) L L L L H H H X Z X = Immaterial Z = High Impedance FACT is a trademark of Fairchild Semiconductor Corporation Fairchild Semiconductor Corporation DS
2 Absolute Maximum Ratings(Note 1) Supply Voltage (V CC ) 0.5V to +7.0V DC Input Diode Current (I IK ) V I = 0.5V 20 ma V I = V CC + 0.5V +20 ma DC Input Voltage (V I ) 0.5V to V CC + 0.5V DC Output Diode Current (I OK ) V O = 0.5V 20 ma V O = V CC + 0.5V +20 ma DC Output Voltage (V O ) 0.5V to V CC + 0.5V DC Output Source or Sink Current (I O ) ±50 ma DC V CC or Ground Current per Output Pin (I CC or I GND ) ±50 ma Storage Temperature (T STG ) 65 C to +150 C Junction Temperature (T J ) PDIP 140 C DC Electrical Characteristics for AC Recommended Operating Conditio Supply Voltage (V CC ) AC 2.0V to 6.0V ACT 4.5V to 5.5V Input Voltage (V I ) 0V to V CC Output Voltage (V O ) 0V to V CC Operating Temperature (T A ) 40 C to +85 C Minimum Input Edge Rate ( V/ t) AC Devices V IN from 30% to 70% of V CC V 3.3V, 4.5V, 5.5V 125 mv/ Minimum Input Edge Rate ( V/ t) ACT Devices V IN from 0.8V to 2.0V V 4.5V, 5.5V 125 mv/ Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specificatio should be met, without exception, to eure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specificatio. Symbol Parameter V CC T A = +25 C T A = 55 C to+125 C T A = 40 C to+85 C Units Conditio (V) Typ Guaranteed Limits V IH Minimum HIGH Level V OUT = 0.1V Input Voltage V or V CC 0.1V V IL Maximum LOW Level V OUT = 0.1V Input Voltage V or V CC 0.1V V OH Minimum HIGH Level Output Voltage V I OUT = 50 µa I OH = 12 ma V I OH = 24 ma I OH = 24 ma (Note 2) V OL Maximum LOW Level Output Voltage V I OUT = 50 µa I OL = 12 ma V I OL = 24 ma I OL = 24 ma (Note 2) I IN Maximum Input (Note 4) Leakage Current 5.5 ±0.1 ±1.0 ±1.0 µa V I = V CC, GND I OZ Maximum V I (OE) = V IL, V IH 3-STATE 5.5 ±0.25 ±5.0 ±2.5 µa V I = V CC, V GND Current V O = V CC, GND I OLD Minimum Dynamic ma V OLD = 1.65V Max I OHD Output Current (Note 3) ma V OHD = 3.85V Min I CC Maximum Quiescent V IN = V CC µa (Note 4) Supply Current or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: I IN and I 3.0V are guaranteed to be less than or equal to the respective 5.5V V CC. 2
3 DC Electrical Characteristics for ACT Symbol Parameter V CC T A = +25 C T A = 55 C to+125 C T A = 40 C to+85 C Units Conditio (V) Typ Guaranteed Limits V IH Minimum HIGH Level V OUT = 0.1V V Input Voltage or V CC 0.1V V IL Maximum LOW Level V OUT = 0.1V V Input Voltage or V CC 0.1V V OH Minimum HIGH Level Output Voltage V I OUT = 50 µa I OH = V I OH = 24 ma I OH = 24 ma (Note 5) V OL Maximum LOW Level Output Voltage V I OUT = 50 µa I OL = 12 ma V I OL = 24 ma I OL = 24 ma (Note 5) I IN Maximum Input Leakage Current 5.5 ±0.1 ±1.0 ±1.0 µa V I = V CC, GND I OZ Maximum 3-STATE 5.5 ±0.25 ±5.0 ±2.5 µa V I = V IL, V IH Current V O = V CC, GND I CCT Maximum I CC /Input ma V I = V CC 2.1V I OLD Minimum Dynamic ma V OLD = 1.65V Max I OHD Output Current (Note 6) ma V OHD = 3.85V Min I CC Maximum Quiescent µa V IN = V CC Supply Current or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. 74AC244 74ACT
4 AC Electrical Characteristics for AC V CC T A = +25 C T A = 55 C to +125 C T A = 40 C to +85 C Symbol Parameter (V) C L = 50 pf C L = 50 pf C L = 50 pf (Note 7) Min Typ Max Min Max Min Max t PLH Propagation Delay Data to Output t PHL Propagation Delay Data to Output t PZH Output Enable Time t PZL Output Enable Time t PHZ Output Disable Time t PLZ Output Disable Time Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V Units AC Electrical Characteristics for ACT V CC T A = +25 C T A = 55 C to +125 C T A = 40 C to +85 C Symbol Parameter (V) C L = 50 pf C L = 50 pf C L = 50 pf Units (Note 8) Min Typ Max Min Max Min Max t PLH Propagation Delay Data to Output t PHL Propagation Delay Data to Output t PZH Output Enable Time t PZL Output Enable Time t PHZ Output Disable Time t PLZ Output Disable Time Note 8: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol Parameter Typ Units Conditio C IN Input Capacitance 4.5 pf V CC = OPEN C PD Power Dissipation Capacitance 45.0 pf V CC = 5.0V 4
5 Physical Dimeio inches (millimeters) unless otherwise noted 74AC244 74ACT Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, Wide Body Package Number M20B 5
6 Physical Dimeio inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 6
7 Physical Dimeio inches (millimeters) unless otherwise noted (Continued) 74AC244 74ACT Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20 7
8 Physical Dimeio inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 8
9 Physical Dimeio inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, Wide Package Number N20A 74AC244 74ACT244 Octal Buffer/Line Driver with 3-STATE Outputs Fairchild does not assume any respoibility for use of any circuitry described, no circuit patent licees are implied and Fairchild reserves the right at any time without notice to change said circuitry and specificatio. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with itructio for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness
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