MM74HC86 Quad 2-Input Exclusive OR Gate
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1 MM74HC86 Quad 2-Input Exclusive OR Gate Features Typical Propagation Delay: 9ns Wide Operating oltage Range: 2 6 Low Input Current: 1mA Maximum Low Quiescent Current: 20mA Max. (74 Series) Output Drive Capability: 10 LS-TTL Loads Description May 2012 The MM74HC86 exclusive OR gate utilizes advanced silicon-gate CMOS technology to achieve operating speeds similar to equivalent LS-TTL gates, while maintaining the low power consumption and high noise immunity characteristic of standard CMOS integrated circuits. These gates are fully buffered and have a fanout of 10 LS-TTL loads. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to CC and ground. Table 1. Truth Table Inputs Outputs A B Y (1) L L L L H H H L H H H L 1. Y A B AB AB Figure 1. Pin Assignments (Top iew) Ordering Information Part Number MM74HC86M MM74HC86MX MM74HC86MTC MM74HC86MTCX Operating Temperature Range -40 to +85 C 2. Pb-Free package per JEDEC J-STD-020B. Package 14-Lead, Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead, Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Packing Method Tube Tape & Reel Tube Tape & Reel MM74HC86 Rev
2 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. Absolute maximum ratings are stress ratings only. Unless otherwise specified, all voltages are referenced to ground. Symbol Parameter Min. Max. Unit CC Supply oltage IN DC Input oltage -1.5 CC +1.5 OUT DC Output oltage -0.5 CC +0.5 I IK, I OK Clamp Diode Current ±20 ma I OUT DC Output Current, per Pin ±25 ma I CC DC CC or GND Current, per Pin ±50 ma T STG Storage Temperature Range C T L Lead Temperature (Soldering, 10 Seconds) 260 C P D Power Dissipation (3, 4) 600 mw 3. Power dissipation temperature derating plastic N package: -12 mw/ C from 65 C to 85 C. 4. S.O. package only 500mW. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Conditions Min. Max. Unit CC Supply oltage 2 6 IN, OUT DC Input or Output oltage 0 CC T A Operating Temperature Range C t R, t F Input Rise or Fall Times CC = CC = CC = ns MM74HC86 Rev
3 DC Electrical Characteristics (5) Symbol Parameter Condition CC () IH IL OH Minimum HIGH Level Input oltage Maximum LOW Level Input oltage Minimum HIGH Level Output oltage I OUT 20µA I OUT 4.0mA I OUT 5.2mA Typ. T A =25 C T A =-40 to +85 C Guaranteed Limit T A =-55 to +125 C Units OL Maximum LOW Level Output oltage I OUT 20µA I OUT 4.0mA I OUT 5.2mA I IN Maximum Input Current IN = CC or GND 6.0 ±0.1 ±1.0 ±1.0 ma I CC Maximum Quiescent Supply Current IN = CC or GND, I OUT = 0mA ma 5. For a power supply of 5 ±10%, the worst-case output voltages ( OH and OL ) occur for HC at 4.5. Thus, the 4.5 values should be used when designing with this supply. Worst-case IH and IL occur at CC = 5.5 and 4.5, respectively. (The IH values at 5 and 5.5 are 3.5 and 3.85, respectively.) The worst-case leakage current (I IN, I CC, and I OZ ) occurs for CMOS at the higher voltage, so the 6.0 values should be used. MM74HC86 Rev
4 AC Electrical Characteristics Symbol Parameter Conditions CC t PHL, t PLH Maximum Propagation Delay C L = 15pF, t R = t F = 6ns t PHL, t PLH Maximum Propagation Delay t TLH, t THL Maximum Output Rise and Fall Time C L = 50pF, t R = t F = 6ns Typ. T A =25 C T A =-40 to +85 C Guaranteed Limit T A =-55 to +125 C Unit s ns ns ns C PD Power Dissipation (6) 25 pf Capacitance (per Gate) C IN Maximum Input Capacitance pf 6. C PD determines the no-load dynamic power consumption, P D = C PD CC 2 f + I CC CC, and the no load dynamic current consumption, I S = C PD CC f + I CC. MM74HC86 Rev
5 Physical Dimensions 6.00 PIN ONE INDICATOR (0.33) 8 7 A B M C B A LAND PATTERN RECOMMENDATION 1.75 MAX C SEE DETAIL A C R0.10 R X 45 GAGE PLANE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, ARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14ARE (1.04) DETAIL A SCALE: 20:1 SEATING PLANE Figure Lead, Small-Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: MM74HC86 Rev
6 Physical Dimensions 0.43 TYP TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, ARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14RE R0.09min Figure Lead, Thin-Shrink Small-Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: MM74HC86 Rev
7 MM74HC86 Rev
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September 2013 NC7SZ66 Low Voltage Single SPST Normally Open Bus Switch Features Broad V CC Operating Range: 1.65 V to 5.5 V Rail-to-Rail Signal Handling Power Down High-Impedance Inputs/Outputs 5 Ω Switch
NC7WZ17 TinyLogic UHS Dual Buffer with Schmitt Trigger Inputs
January 2012 NC7WZ17 TinyLogic UHS Dual Buffer with Schmitt Trigger Inputs Features Ultra-High Speed: t PD 3.6ns (Typical) into 50pF at 5 CC High Output Drive: ±24m at 3 CC Broad CC Operating Range: 1.65
NC7S08 TinyLogic HS 2-Input AND Gate
NC7S08 TinyLogic HS 2-Input AND Gate Features Space saving SOT23 or SC70 5-lead package Ultra small MicroPak Pb-Free leadless package High Speed; t PD 3.5ns typ Low Quiescent Power; I CC < 1µA Balanced
NC7S04 TinyLogic HS Inverter
NC7S04 TinyLogic HS Inverter General Description The NC7S04 is a single high performance CMOS Inverter. Advanced Silicon Gate CMOS fabrication assures high speed and low power circuit operation over a
FSA4159 Low-Voltage, 1Ω SPDT Analog Switch with Power-Off Isolation
December 2013 FSA4159 Low-Voltage, 1Ω SPDT Analog Switch with Power-Off Isolation Features Low I CC When the S Input is Lower Than V CC Power-Off Isolation (V CC=0 V) 1 Ω On Resistance (R ON) for 4.5 V
FSAV433 High-Bandwidth (550MHz), 3-Channel, 3:1 Video Switch
January 2011 FSAV433 High-Bandwidth (550MHz), 3-Channel, 3:1 Video Switch Features Ground between Channels to Optimize Isolation and Reduce Hostile Crosstalk -70dB Non-Adjacent Channel Crosstalk at 30MHz
FSAV MHz, 4-Channel, 2:1 Video Switch
Features -50dB Off Isolation at 30MHz -80dB Non-Adjacent Channel Crosstalk at 30MHz 3dB Bandwidth: 800MHz On Resistance: 4 (Typical) Low Power Consumption: 1µA (Maximum) Control Input TTL Compatible Applications
74ALVC Low Voltage 16-Bit Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in A Port Outputs
74ALVC162245 Low Voltage 16-Bit Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in A Port Outputs General Description The ALVC162245 contains sixteen non-inverting
Obsolete Product(s) - Obsolete Product(s)
QUAD 2-INPUT NAND GATE HIGH SPEED: t PD = 8ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 1µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
74LVT2245, 74LVTH2245 Low Voltage Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs and 25Ω Series Resistors in the B Port Outputs
January 2008 74LVT2245, 74LVTH2245 Low Voltage Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs and 25Ω Series Resistors in the B Port Outputs Features Input and output interface capability
INTEGRATED CIRCUITS. 74LVC00A Quad 2-input NAND gate. Product specification Supersedes data of 1997 Aug 11 IC24 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1997 Aug 11 IC24 Data Handbook 1998 Apr 28 FEATURES Wide supply range of 1.2V to 3.6V Complies with JEDEC standard no. 8-1A Inputs accept voltages up to 5.5V CMOS
NC7ST00 TinyLogic HST 2-Input NAND Gate
TinyLogic HST 2-Input NAND Gate General Description The is a single 2-Input high performance CMOS NAND Gate, with TTL-compatible inputs. Advanced Silicon Gate CMOS fabrication assures high speed and low
74LVT573, 74LVTH573 Low Voltage Octal Transparent Latch with 3-STATE Outputs
January 2008 74LVT573, 74LVTH573 Low Voltage Octal Transparent Latch with 3-STATE Outputs Features Input and output interface capability to systems at 5V V CC Bushold data inputs eliminate the need for
74AC244 74ACT244 Octal Buffer/Line Driver with 3-STATE Outputs
74AC244 74ACT244 Octal Buffer/Line Driver with 3-STATE Outputs General Description The AC/ACT244 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and
M74HCT244TTR OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (NON INVERTED)
OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (NON INVERTED) HIGH SPEED: t PD = 15 ns (TYP.) at V CC = 4.5V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS : V IH = 2V (MIN.) V
74LVT245, 74LVTH245 Low Voltage Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs
February 2008 74LVT245, 74LVTH245 Low Voltage Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs Features Input and output interface capability to systems at 5V V CC Bushold data inputs eliminate