SN74ACT CLOCKED FIRST-IN, FIRST-OUT MEMORY

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1 Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized to ndependent System Clocks nput-ready Flag Synchronized to Write Clock Output-Ready Flag Synchronized to Read Clock 248 Words by 9 Bits Low-Power Advanced CMOS Technology Programmable Almost-Full/Almost-Empty Flag SN74ACT CLOCKED FST-N, FST-OUT MEMY SCAS2D JANUARY 99 REVSED APRL 998 nput-ready, Output-Ready, and Half-Full Flags Cascadable in Word Width and/or Word Depth Fast Access Times of 2 ns With a 5-pF Load Data Rates up to 67 MHz 3-State Outputs Package Options nclude 44-Pin Plastic Leaded Chip Carrier (FN) and 64-Pin Thin Quad Flat (PAG, PM) Packages description The SN74ACT787 is a 248-word by 9-bit FFO with high speed and fast access times. t processes data at rates up to 67 MHz and access times of 2 ns in a bit-parallel format. Data outputs are noninverting with respect to the data inputs. Expansion is easily accomplished in both word width and word depth. The write-clock () and read-clock () inputs should be free running and can be asynchronous or coincident. Data is written to memory on the rising edge of when the write-enable (WRTEN/DP9, ) inputs are high and the input-ready () flag output is high. Data is read from memory on the rising edge of when the read-enable (RDEN, ) and output-enable () inputs are high and the output-ready () flag output is high. The first word written to memory is clocked through to the output buffer regardless of the levels on RDEN,, and. The flag indicates that valid data is present on the output buffer. The FFO can be reset asynchronous to and. must be asserted while at least four and four cycles occur to clear the synchronizing registers. Resetting the FFO initializes the,, and half-full (HF) flags low and the almost-full/almost-empty () flag high. The FFO must be reset upon power up. The SN74ACT787 is characterized for operation from C to 7 C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas nstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTON DATA information is current as of publication date. Products conform to specifications per the terms of Texas nstruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 998, Texas nstruments ncorporated POST OFFCE BOX DALLAS, TEXAS 75265

2 SN74ACT CLOCKED FST-N, FST-OUT MEMY SCAS2D JANUARY 99 REVSED APRL 998 FN PACKAGE (TOP VEW) HF Q D D D2 D3 D4 D5 D6 D7 D Q Q2 Q3 Q4 Q5 Q6 Q7 D D D2 D3 D4 D5 D8 Q Q2 Q3 Q4 Q5 Q6 Q7 WRTEN/DP9 RDEN Q8 PAG PM PACKAGE (TOP VEW) Q HF Q8 RDEN WRTEN/DP9 D6 D7 No internal connection 2 POST OFFCE BOX DALLAS, TEXAS 75265

3 logic symbol SN74ACT CLOCKED FST-N, FST-OUT MEMY SCAS2D JANUARY 99 REVSED APRL 998 WRTEN/DP9 RDEN & EN & WRTEN RDEN Φ FFO SN74ACT787 PROGRAM ENABLE N RDY HALF FULL ALMOST FULL/EMPTY OUT RDY HF D D D2 D3 D4 D5 D6 D7 D Data Data Q Q Q2 Q3 Q4 Q5 Q6 Q7 Q8 This symbol is in accordance with ANS/EEE Std and EC Publication Pin numbers shown are for the FN package. POST OFFCE BOX DALLAS, TEXAS

4 SN74ACT CLOCKED FST-N, FST-OUT MEMY SCAS2D JANUARY 99 REVSED APRL 998 functional block diagram D D8 RDEN Synchronous Read Control Read Pointer Location Location RAM WRTEN/DP9 Synchronous Write Control Write Pointer Location 247 Location 248 Register Q Q8 Reset Logic Status- Flag Logic HF 4 POST OFFCE BOX DALLAS, TEXAS 75265

5 Terminal Functions SN74ACT CLOCKED FST-N, FST-OUT MEMY SCAS2D JANUARY 99 REVSED APRL 998 TERMNAL NAME /O DESCRPTON O Almost-full/almost-empty flag. Depth offset values can be programmed for or the default value of 256 can be used for both the almost-empty offset (X) and the almost-full offset (Y). is high when memory contains X or fewer words or (248 Y) or more words. is high after reset. D D8 Nine-bit data input port HF O Half-full flag. HF is high when the FFO memory contains 24 or more words. HF is low after reset. O nput-ready flag. is synchronized to the low-to-high transition of. When is low, the FFO is full and writes are disabled. is low during reset and goes high on the second low-to-high transition of after reset. Output enable. When, RDEN, and are high, data is read from the FFO on a low-to-high transition of. When is low, reads are disabled and the data outputs are in the high-impedance state. O Output-ready flag. is synchronized to the low-to-high transition of. When is low, the FFO is empty and reads are disabled. Ready data is present on Q Q7 when is high. is low during reset and goes high on the third low-to-high transition of after the first word is loaded to empty memory. Program enable. After reset and before the first word is written to the FFO, the binary value on D D8 and DP9 is latched as an offset value when is low and is high. Q Q8 O Nine-bit data output port. After the first valid write to empty memory, the first word is output on Q Q8 on the third rising edge of. also is asserted high at this time to indicate ready data. When is low, the last word read from the FFO is present on Q Q8. Read clock. is a continuous clock and can be asynchronous or coincident to. A low-to-high transition of reads data from memory when RDEN,,, and are high. is synchronous to the low-to-high transition of. RDEN WRTEN/DP9 Read enables. When RDEN,,, and are high, data is read from the FFO on the low-to-high transition of. Reset. To reset the FFO, four low-to-high transitions of and four low-to-high transitions of must occur while is low. This sets HF,, and low and high. Write clock. is a continuous clock and can be asynchronous or coincident to. A low-to-high transition of writes data to memory when WRTEN/DP9,, and are high. is synchronous to the low-to-high transition of. Write enable/data pin 9. When WRTEN/DP9,, and are high, data is written to the FFO on a low-to-high transition of. When programming an offset value, WRTEN/DP9 is used as the most-significant data bit. Write enable. When WRTEN/DP9,, and are high, data is written to the FFO on a low-to-high transition of. POST OFFCE BOX DALLAS, TEXAS

6 SN74ACT CLOCKED FST-N, FST-OUT MEMY SCAS2D JANUARY 99 REVSED APRL 998 offset values for The flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset value (Y). They can be programmed after the FFO is reset and before the first word is written to memory. f the offsets are not programmed, the default values of X = Y = 256 are used. The flag is high when the FFO contains X or fewer words or (248 Y) or more words. Program enable () should be held high throughout the reset cycle. can be brought low only when is high and is low. On the following low-to-high transition of, the binary value on D D8 and WRTEN/DP9 is stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding low for another low-to-high transition of reprograms Y to the binary value on D D8 and WRTEN/DP9 at the time of the second low-to-high transition. While the offsets are programmed, data is not written to the FFO memory, regardless of the state of the write enables (WRTEN/DP9, ). A maximum value of 23 can be programmed for either X or Y (see Figure ). To use the default values of X = Y = 256, must be held high. 3 4 ÏÏÏÏÏÏÏÏ D D8 ÎÎÎÎÎÎÎÎÎÎÎ X and Y Y Word ÎÎÎÎÎ WRTEN/DP9 ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ X and Y MSB YMSB ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ Figure. Programming X and Y Separately 6 POST OFFCE BOX DALLAS, TEXAS 75265

7 SN74ACT CLOCKED FST-N, FST-OUT MEMY SCAS2D JANUARY 99 REVSED APRL WRTEN/DP9 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ D D8 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RDEN ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Q Q8 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ HF ÎÎÎÎÎÎÎÎÎÎÎ nvalid Figure 2. Reset Cycle Define the Flag Using the Default Value of X = Y = 256 POST OFFCE BOX DALLAS, TEXAS

8 SN74ACT CLOCKED FST-N, FST-OUT MEMY SCAS2D JANUARY 99 REVSED APRL 998 WRTEN/DP9 D D8 W W2 W3 W4 W(X+2) W25 W(249 Y) W RDEN Q Q8 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ nvalid W HF Figure 3. Write Cycle 8 POST OFFCE BOX DALLAS, TEXAS 75265

9 SN74ACT CLOCKED FST-N, FST-OUT MEMY SCAS2D JANUARY 99 REVSED APRL WRTEN/ DP9 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ D D8 W249 RDEN Q Q8 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ W W2 W3 W(Y+) W(Y+2) W25 W26 W(248 X) W(249 X) W248 W249 HF Figure 4. Read Cycle POST OFFCE BOX DALLAS, TEXAS

10 SN74ACT CLOCKED FST-N, FST-OUT MEMY SCAS2D JANUARY 99 REVSED APRL 998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V to 7 V nput voltage range, V V to 7 V Voltage range applied to a disabled 3-state output V to 5.5 V Package thermal impedance, θ JA (see Note ): FN package C/W PAG package C/W PM package C/W Storage temperature range, T stg C to 5 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE : The package thermal impedance is calculated in accordance with JESD 5. recommended operating conditions ACT787-5 ACT787-2 ACT ACT787-4 UNT MN MAX MN MAX MN MAX MN MAX VCC Supply voltage V VH High-level input voltage V VL Low-level input voltage V OH High-level output current Q outputs, flags ma OL Low-level output current Q outputs Flags TA Operating free-air temperature C ma electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDTONS MN TYP MAX UNT VOH VCC = 4.5 V, OH = 8 ma 2.4 V VOL Flags VCC = 4.5 V, OL = 8 ma.5 Q outputs VCC = 4.5 V, OL = 6 ma.5 VCC = 5.5 V, V = VCC or ±5 µa OZ VCC = 5.5 V, VO = VCC or ±5 µa CC VCC = 5.5 V, V = VCC.2 V or 4 µa CC WRTEN/DP9 Other inputs VCC =55V 5.5 V, One input at 3.4 V, Other inputs at VCC or Ci V =, f = MHz 4 pf Co VO =, f = MHz 8 pf All typical values are at VCC = 5 V, TA = 25 C. This is the supply current for each input that is at one of the specified TTL voltage levels rather V or VCC. 2 V ma POST OFFCE BOX DALLAS, TEXAS 75265

11 SN74ACT CLOCKED FST-N, FST-OUT MEMY SCAS2D JANUARY 99 REVSED APRL 998 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures through 5) ACT787-5 ACT787-2 ACT ACT787-4 MN MAX MN MAX MN MAX MN MAX fclock Clock frequency MHz high or low tw Pulse duration high or low ns tsu thh Setup time Hold time low D D8 before WRTEN, before, RDEN, before UNT ns Reset: low before first and before D D8 after WRTEN, after, RDEN, after Reset: low after fourth and To permit the clock pulse to be utilized for reset purposes high after low after switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C L = 5 pf (unless otherwise noted) (see Figure 5) PARAMETER FROM TO ACT787-5 ACT787-2 ACT ACT787-4 (NPUT) (OUTPUT) MN TYP MAX MN MAX MN MAX MN MAX fmax or MHz tpd Any Q ns tpd Any Q 8 ns tpd tplh HF ns tphl HF ns tplh low ns tphl low HF ns ten Any Q ns tdis Any Q ns All typical values are at VCC = 5 V, TA = 25 C. This parameter is measured with CL = 3 pf (see Figure 6). ns UNT ns POST OFFCE BOX DALLAS, TEXAS 75265

12 SN74ACT CLOCKED FST-N, FST-OUT MEMY SCAS2D JANUARY 99 REVSED APRL 998 operating characteristics, = 5 V, T A = 25 C PARAMETER TEST CONDTONS TYP UNT Cpd Power dissipation capacitance per FFO channel Outputs enabled CL = 5 pf, f = 5 MHz 9 pf PARAMETER MEASUREMENT NFMATON 7 V From Output Under Test CL = 5 pf (see Note A) S 5 Ω 5 Ω Test Point PARAMETER ten tdis tpd tpzh tpzl tphz tplz tplh tphl S Open Closed Open Closed Open Open LOAD CCUT tw 3 V Timing nput tsu.5 V th 3 V V nput.5 V.5 V VOLTAGE WAVEFMS PULSE DURATON V Data nput.5 V.5 V VOLTAGE WAVEFMS SETUP AND HOLD TMES 3 V V Output Control tpzl.5 V tplz.5 V 3 V V nput tplh.5 V.5 V tphl 3 V V Output Waveform S at 7 V tpzh.5 V tphz 3.5 V VOL +.3 V VOL Output.5 V.5 V VOH VOL Output Waveform 2 S at Open.5 V VOH VOH.3 V V VOLTAGE WAVEFMS PROPAGATON DELAY TMES VOLTAGE WAVEFMS ENABLE AND DSABLE TMES NOTE A: CL includes probe and jig capacitance. Figure 5. Load Circuit and Voltage Waveforms 2 POST OFFCE BOX DALLAS, TEXAS 75265

13 TYPCAL CHARACTERSTCS SN74ACT CLOCKED FST-N, FST-OUT MEMY SCAS2D JANUARY 99 REVSED APRL 998 t pd Propagation Delay Time ns typ + 8 typ + 6 typ + 4 typ + 2 typ PROPAGATON DELAY TME vs LOAD CAPACTAE VCC = 5 V RL = 5 Ω TA = 25 C CC(f) Active CC ma TA = 25 C ACTVE CC vs FREQUEY VCC = 5 V VCC = 5.5 V VCC = 4.5 V 2 typ CL Load Capacitance pf f Frequency MHz Figure 6 Figure VCC = 4.5 V VCC = 5 V VCC = 5.5 V TA = 25 CC() dle CC ma Slope = f Frequency MHz 7 Figure 8. SN74ACT787 dle CC With Switching, Other nputs at or.2 V and Outputs Disconnected POST OFFCE BOX DALLAS, TEXAS

14 SN74ACT CLOCKED FST-N, FST-OUT MEMY SCAS2D JANUARY 99 REVSED APRL 998 CLOCK APPLCATON NFMATON WRTEN SN74ACT787 WRTEN/DP9 SN74ACT787 WRTEN/DP9 RDEN RDEN RDEN 5 V D D8 D D8 Q Q8 D D8 Q Q8 Q Q8 Figure 9. Word-Depth Expansion: Bits WRTEN SN74ACT787 WRTEN/DP9 RDEN RDEN D9 D7 D D8 Q Q8 Q9 Q7 SN74ACT787 WRTEN/DP9 RDEN D D8 D D8 Q Q8 Q Q8 Figure. Word-Width Expansion: Bits 4 POST OFFCE BOX DALLAS, TEXAS 75265

15 MPTANT NOTCE Texas nstruments and its subsidiaries (T) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. T warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with T s standard warranty. Testing and other quality control techniques are utilized to the extent T deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAN APPLCATONS USNG SEMCONDUCT PRODUCTS MAY NVOLVE POTENTAL RSKS OF DEATH, PERSONAL NJURY, SEVERE PROPERTY ENVONMENTAL DAMAGE ( CRTCAL APPLCATONS ). T SEMCONDUCT PRODUCTS ARE NOT DESGNED, AUTHZED, WARRANTED TO BE SUTABLE F USE N LFE-SUPPT DEVCES SYSTEMS OTHER CRTCAL APPLCATONS. LUSON OF T PRODUCTS N SUCH APPLCATONS S UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RSK. n order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. T assumes no liability for applications assistance or customer product design. T does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of T covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. T s publication of information regarding any third party s products or services does not constitute T s approval, warranty or endorsement thereof. Copyright 999, Texas nstruments ncorporated

SN74ACT STROBED FIRST-IN, FIRST-OUT MEMORY

SN74ACT STROBED FIRST-IN, FIRST-OUT MEMORY Member of the Texas Itruments idebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 256 ords by 18 Bits Low-Power Advanced CMOS Technology Full, Empty, and Half-Full Flags Programmable