3.3V/5V 2.5GHz PROGRAMMABLE DELAY

Transcription

1 3.3V/5V 2.5GHz PROGRAMMABLE DELAY FEATURES Pin-for-pin, plug-in compatible to the ON Semiconductor MCEP95 Maximum frequency > 2.5GHz Programmable range: 2.2ns to 2.2ns ps increments PECL mode operating range: V CC = 3.V to 5.5V with V EE = V NECL mode operating range: V CC = V with V EE = 3.V to 5.5V Open input default state Safety clamp on inputs A logic high on the /EN pin will force to logic low D[:] can accept either ECL, CMOS, or TTL inputs V BB output reference voltage Available in a 32-pin TFP package APPLICATIONS DESCRIPTION The is a programmable delay line, varying the time a logic signal takes to traverse from to. This delay can vary from about 2.2ns to about 2.2ns. The input can be PECL, LVPECL, NECL, or LVNECL. The delay varies in discrete steps based on a control word presented to. The -bit width of this latched control register allows for delay increments of approximately ps. An eleventh control bit allows the cascading of multiple devices, for a wider delay range. Each additional effectively doubles the delay range available. For maximum flexibility, the control register interface accepts CMOS or TTL level signals, as well as the input level at the ± pins. All support documentation can be found on Micrel s web site at: CROSS REFERENCE TABLE Clock de-skewing Timing adjustment Aperture centering Micrel Semiconductor TI TITR ON Semiconductor MCEP95FA MCEP95FAR2 TYPICAL APPLICATIONS CIRCUIT TYPICAL PERFORMANCE Data Signal of Unknown Phase CLOCK+ D + Flip-Flop CK 2 Delay vs. Tap CLOCK / / D[9:] CONTROL LOGIC DELAY (ps) TAP (DIGITAL WORD) ECL Pro is a registered trademark of Micrel, Inc. Rev.: D Amendment: / Issue Date: December 25

2 PACKAGE/ORDERG FORMATION D7 D6 D5 D4 VEE D3 D2 D Ordering Information () D8 D9 D / VBB VEF VCF VEE LEN SETM SETMAX VCC /CASCADE CASCADE /EN VEE D VCC / VCC VCC NC Package Operating Package Lead Part Number Type Range Marking Finish TI T32- Industrial Sn-Pb TITR (2) T32- Industrial Sn-Pb TG (3) T32- Industrial with Pb-Free Pb-Free bar-line indicator NiPdAu TGTR (2, 3) T32- Industrial with Pb-Free Pb-Free bar-line indicator NiPdAu Notes:. Contact factory for die availability. Dice are guaranteed at T A = 25 C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. 32-Pin TFP (T32-) FUNCTIONAL BLOCK DIAGRAM / /EN D[9:] LEN SETM SETMAX -bit Latch / D[] Latch CASCADE /CASCADE V BB V CF V EF 2

3 P DESCRIPTION Pin Number Pin Name Pin Function 23, 25, 26, 27, 29, D[:9] CMOS, ECL, or TTL Select Inputs: These digital control signals adjust the amount of 3, 3, 32,, 2 delay from to. Please refer to the Ac Electrical Table (page 7) and Table 7 (page 7) for delay values. Figure 9 shows how to interface these inputs to various logic family standards. These inputs default to logic low when left unconnected. Bit is the least significant bit, and bit 9 is the most significant bit. 3 D[] CMOS, ECL, or TTL Select Input: This input latches just like D[:9] does. It drives the CASCADE, /CASCADE differential pair. Use only when cascading two or more to extend the range of delays required. 4, 5, / ECL Input: This is the signal to be delayed. If this input pair is left unconnected, this is equivalent to a logic low input. 6 VBB Voltage Output: When using a single-ended logic source for and /, connect the unused input of the differential pair to this pin. This pin can also re-bias AC-coupled inputs to and /. When used, de-couple this pin to V CC through an.µf capacitor. Limit current sinking or sourcing to.5ma or less. 7 VEF Voltage Output: Connect this pin to VCF when the D inputs are ECL. Refer to the Digital Control Logic Standard section of the Functional Description to interface the D inputs to CMOS or TTL. 8 VCF Voltage Input: The voltage at this pin sets the logic transition threshold for the D inputs. 9, 24, 28 VEE Most Negative Supply: Supply ground for PECL systems. LEN ECL Control Input: When logic low, the D inputs flow through. Any changes to the D inputs reflect in the delay between, / and, /. When logic high, the logic values at D are latched, and these latched bits determine the delay. SETM ECL Control Input: When logic high, the contents of the D register are reset. This sets the delay to the minimum possible, equivalent to D[:9] being set to. When logic low, the value of the D register, or the logic value of SETMAX determines the delay from, / to, /. This input defaults to logic low when left unconnected. 2 SETMAX ECL Control Input: When logic high and SETM is logic low, the contents of the D register are set high, and the delay is set to one step greater than the maximum possible with D[:9] set to. When logic low, the value of the D register, or the logic value of SETM determines the delay from, / to, /. This input defaults to logic low when left unconnected. 3, 8, 9, 22 VCC Most Positive Supply: Supply ground for NECL systems. Bypass to V EE with.µf and.µf low ESR capacitors. 5, 4 CASCADE, ECL Outputs: These outputs are used when cascading two or more to /CASCADE extend the delay range required. 6 /EN ECL Control Input: When set active low,, / are a delayed version of, /. When set inactive high,, / are gated such that, / become a differential logic low. This input defaults to logic low when left unconnected. 2, 2, / k ECL Outputs: This signal pair is the delayed version of, /. 7 NC No Connect: Leave this pin unconnected. 3

4 Absolute Maximum Ratings () Supply Voltage (V CC ) PECL Mode (V EE =V)....5V to +6.V Supply Voltage (V EE ) NECL Mode (V CC =V) V to 6.V Any Input Voltage (V ) PECL Mode....5V to V CC +.5V NECL Mode V to V EE.5V ECL Output Current (I OUT ) Continuous... 5mA Surge... ma I BB Sink/Source Current... ±.5mA Lead Temperature (soldering, 2 sec.) C Storage Temperature (T S ) C to +5 C ESD Rating (3)... >.5kV Operating Ratings (2) Supply Voltage (V CC ) PECL Mode (V EE =V) V to +5.5V Supply Voltage (V EE ) NECL Mode (V CC =V)... 3.V to 5.5V Ambient Temperature (T A )... 4 C to +85 C Package Thermal Resistance TFP-32 (θ JA ) Still-air... 5 C/W 5lfpm C/W TFP-32 (θ JC )... 2 C/W DC ELECTRICAL CHARACTERISTICS T A = 4 C to +85 C. Symbol Parameter Condition Min Typ Max Units V CC Power Supply Voltage (PECL) V V V EE Power Supply Voltage (NECL) V V I EE Power Supply Current (4) No load, over supply voltage 5 75 ma Notes:. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Devices are ESD sensitive. Handling precautions recommended. 4. Required 5lfpm air flow when using +5V or 5V power supply. 4

5 LVPECL DC ELECTRICAL CHARACTERISTICS (kep) V CC = 3.3V, V EE = V; T A = 4 C to +85 C. (5, 6) Symbol Parameter Condition Min Typ Max Units V OH Output HIGH Voltage Figures 2, 3, mv V OL Output LOW Voltage Figures 2, 3, mv V IH Input HIGH Voltage Figures, 4 PECL mv CMOS 85 mv TTL 2 mv V IL Input LOW Voltage Figures, 4 PECL mv CMOS 485 mv TTL 8 mv V BB Output Voltage Reference mv V CF Input Select Voltage mv V EF Mode Connection mv V IHCMR Input HIGH Voltage Common Figure V Mode Range (7) I IH Input HIGH Current 5 µa I IL Input LOW Current.5 µa / 5 µa Notes: 5. Device is guaranteed to meet the DC specifications, shown in the table below, after thermal equilibrium has been established. The device is tested in a socket such that transverse airflow of 5lfpm is maintained. 6. Input and output parameters vary : with V CC. V EE can vary +.3V to 2.2V. 7. V IHCMR maximum varies : with V CC. The V IHCMR range is referenced to the most positive side of the differential input signal. 5

6 PECL DC ELECTRICAL CHARACTERISTICS (kep) V CC = 5.V, V EE = V; T A = 4 C to +85 C. (8, 9) Symbol Parameter Condition Min Typ Max Units V OH Output HIGH Voltage Figures 2, 3, mv V OL Output LOW Voltage Figures 2, 3, mv V IH Input HIGH Voltage Figures, 4 PECL mv CMOS 275 mv TTL 2 mv V IL Input LOW Voltage Figures, 4 PECL mv CMOS 225 mv TTL 8 mv V BB Output Voltage Reference mv V IHCMR Input HIGH Voltage Common Figure V Mode Range () I IH Input HIGH Current 5 µa I IL Input LOW Current.5 µa / 5 µa NECL DC ELECTRICAL CHARACTERISTICS (kep) V CC = V, V EE = 5.5V to 3.V; T A = 4 C to +85 C. (8) Symbol Parameter Condition Min Typ Max Units V OH Output HIGH Voltage Figures 2, mv V OL Output LOW Voltage Figures 2, mv V IH Input HIGH Voltage NECL Figures, mv V IL Input LOW Voltage NECL Figures, mv V BB Output Voltage Reference mv V IHCMR Input HIGH Voltage Common Figure 5 V EE +2.. V Mode Range () I IH Input HIGH Current 5 µa I IL Input LOW Current.5 µa / 5 µa Notes: 8. Device is guaranteed to meet the DC specifications, shown in the table above, after thermal equilibrium has been established. The device is tested in a socket such that transverse airflow of 5lfpm is maintained. 9. Input and output parameters vary : with V CC. V EE can vary +2.V to.5v.. V IHCMR maximum varies : with V CC. The V IHCMR range is referenced to the most positive side of the differential input signal.. V IHCMR minimum varies : with V EE. The V IHCMR range is referenced to the most positive side of the differential input signal. 6

7 AC ELECTRICAL CHARACTERISTICS V CC = 3. to 5.5V, V EE = V or V CC = V, V EE = 3. to 5.5V; T A = 4 C to +85 C. (2, 3) T A = 4 C T A = +25 C T A = +85 C Symbol Parameter Min Typ Max Min Typ Max Min Typ Max Unit t Step Delay f MAX Maximum Frequency (4) GHz t PD Propagation Delay to ; D[-]= ps to ; D[-]= ps /EN to : D[-]= ps D to CASCADE ps t RANGE Programmable Range tpd(max)-tpd(min) ps (5) D High 9 ps D High ps D2 High ps D3 High ps D4 High ps D5 High ps D6 High ps D7 High ps D8 High ps D9 High ps Lin Linearity (6) ± ± ± %LSB t SKEW Duty Cycle Skew (7) t PHL-t PLH 25 ps t S Setup Time D to LEN ps D to (8) ps /EN to (9) ps t H Hold Time LEN to D ps to /EN (2) ps t R Release Time /EN to (2) 5 ps SETMAX to LEN ps SETM to LEN ps t JIT Cycle-to-Cycle Jitter (22).2 <.2 <.2 < ps RMS V PP Input Voltage Swing (Differential) mv t r Output Rise/Fall Time t f 2% to 8% () ps 2% to 8% (CASCADE) ps Notes: 2. AC characteristics are guaranteed by design and characterization. 3. Measured using 75mV source, 5% duty cycle clock source, R L = 5Ω to V CC 2V. 4. Refer to Typical Operating Characteristics for output swing performance. 5. The delays of the individual bits are cumulative. 6. Linearity is the deviation from the ideal delay. 7. Duty cycle skew guaranteed only for differential operation measured from the crosspoint of the input edge to the crosspoint of the corresponding output edge. 8. Setup time defines the amount of time prior to an edge on, / that the D[:9] bits must be set to guarantee the new delay will occur for that edge. 9. Setup time is the minimum that /EN must be asserted prior to the next transition of, / to prevent an output response greater than ±75mV to that, / transition. 2. Hold time is the minimum time that /EN must remain asserted after a negative going or a positive going / to prevent an output response greater than ±75mV to that, / transition. 2. Release time is the minimum time that /EN must be deasserted prior to the next, / transition to ensure an output response that meets the specified to propagation delay and transition times. 22. This is the amount of generated jitter added to an otherwise jitter free clock signal, going from, / to, /, where the clock may be any frequency between. and 2.5GHz. 7

8 TYPICAL OPERATG CHARACTERISTICS OUTPUT SWG (mv) , / Output Swing vs. Frequency FREUENCY (MHz) I EE (ma) Supply Current vs. Temperature 8 6 V CC = 5.5V V CC = 3.3V 4 2 V CC = 5.V V CC = 3.V TEMPERATURE ( C) 8

9 V CC V CC 5;-2'#8 75k9, CASCADE /, /CASCADE / 75k9 75k9 Figure a. Differential Input Structure Figure 2. Emitter Output Structure V CC /EN LEN SETM SETMAX D[:] V BB / CASCADE /CASCADE V OL V OH Figure 3a. Output Levels, PECL, LVPECL V 75k9 Figure b. Single-Ended Input Structure / CASCADE /CASCADE V OL V V OH Figure 3b. Output Levels, NECL 9

10 V CC Invalid V Invalid V IH(MAX) V IH(MAX) Logic High Logic High V IH(M) V IL(MAX) Invalid V IH(M) V IL(MAX) Invalid Logic Low Logic Low V IL(M) V Invalid V IL(M) V EE Invalid Figure 4a. Input Levels, PECL Figure 4c. Input Levels, NECL V CC Invalid V IHCMR Logic High V IH(M) V IL(MAX) V Invalid Logic Low Invalid / Figure 5a. Input Common Mode, PECL, LVPECL V Figure 4b. Input Levels, CMOS, TTL V V IHCMR / V IHCMR Figure 5b. Input Common Mode, NECL

11 TERMATG PECL Z O = 5Ω R 3Ω R 3Ω Z O = 5Ω R2 82Ω R2 82Ω V t = V CC 2V Note:. For +5.V systems: R = 82Ω, R2 = 3Ω. Figure 6a. Parallel Termination Thevenin Equivalent Z = 5Ω Z = 5Ω Source 5Ω 5Ω Destination 5Ω R b C (optional).µf Figure 6b. Three-Resistor Y-Termination Notes:. Power-saving alternative to Thevenin termination. 2. Place termination resistors as close to destination inputs as possible. 3. R b resistor sets the DC bias voltage, equal to V t. For systems R b = 46Ω to 5Ω. For +5V systems, R b = Ω. / R 3Ω R2 82Ω Z O = 5Ω V t = V CC 2V R 3Ω R2 82Ω 5Ω.µF V BB Figure 6c. Terminating Unused I/O Notes:. Unused output (/) must be terminated to balance the output. 2. Micrel's differential I/O logic devices include a V BB reference pin. 3. Connect unused input through 5Ω to V BB. Bypass with a.µf capacitor to V CC, not GND, as PECL is referenced to V CC.

12 V CC V CC PECL Output.µF LVPECL Signals D[:] V CF / V EF 5;-2'#8 V BB V EE V Figure 7a. Interfacing to a Single-Ended PECL Signal Figure 9b. Connecting LVPECL Signals to the D Inputs V CC V CC or +5.V.µF CMOS Inputs D[:] PECL Output / NC NC V CF V EF 5;-2'#8 V BB 5;-2'#8 Figure 7b. Interfacing to and Inverting a Single-Ended PECL Signal V EE V Figure 9c. Connecting CMOS Signals to the D Inputs Note: V CF and V EF are not connected. V CC V CC /.µf 5 5 V BB TTL Inputs D[:] 5;-2'#8 Figure 8. Re-Biasing an AC-Coupled Signal.5k9 NC V CF V EF V V EE V PECL Signals V CC +5.V D[:] Figure 9d. Connecting TTL Signals to the D Inputs, with V CC = 3.3V V CF V CC +5.V V EF 5;-2'#8 TTL Inputs D[:] V EE V V CF Figure 9a. Connecting PECL Signals to the D Inputs 59 NC V EF 5;-2'#8 V V EE V Figure 9e. Connecting TTL Signals to the D Inputs, with V CC = 5.V 2

13 FUNCTIONAL DESCRIPTION is a programmable delay line, varying the delay of a PECL or NECL input signal by any amount between about 2.2ns and 2.2ns. A -bit digital control register affords delay steps of approximately ps. implements the delay using a multiplexer chain and a set of fixed delay elements. Under digital control, various subsets of the delay elements are included in the signal chain. To simplify interfacing, the -bit digital delay control word interfaces to PECL, CMOS, or TTL interface standards. Since multiplexers must appear in the delay path, has a minimum delay of about 2.2ns. Delays below this value are not possible. In addition, when cascading multiple to extend the delay range, the minimum delay is about 2.2ns times the number of in cascade. An eleventh control bit, D[], along with the CASCADE and /CASCADE outputs and the SETM and SETMAX inputs, simplifies the task of cascading. Signal Path Logic Standard The signal path, from, / to, /, interfaces to PECL, LVPECL, or NECL signals, as shown in Table 6. The choice of signal path logic standard may limit possible choices for the delay control inputs, D. Input Enable The /EN input gates the signal at, /. When disabled, the input is effectively gated out, just as if a logic low was being provided to. /EN Value at, / L H Table. /EN Truth Table, / Delayed Logic Low Delayed Digital Control Latch can capture the digital delay control word into its internal -bit latch, bits for D[:9], and an extra bit for the D[] cascade control. The LEN input controls the action of this latch, as per Table 2. Note that the LEN input is always PECL, LVPECL, or NECL, the same as the, / signal pair. The -bit delay control word, however, may also be CMOS or TTL. LEN L H Latch Action Pass Through D[:] Latch D[:] Digital Control Logic Standard When used in systems where V EE connects to ground, may interface either to PECL, CMOS, or TTL on its D[:] inputs. To this end, the V CF pin sets the threshold at which the D inputs switch between logic low and logic high. As shown in Table 3, connecting V CF to V EF sets the threshold to PECL (if V CC is 5V) or LVPECL (if V CC is 3.3V). Leaving V CF and V EF open yields a threshold suitable for detecting CMOS output logic levels. Leaving V EF open and connecting V CF to a.5v source allows the D inputs to accept TTL signals. Logic Standard ECL, PECL CMOS TTL V CF Connection VEF No Connect.5V Source Table 3. Digital Control Standard Truth Table If a.5v source is not available, connecting V CF to V EE through an appropriate resistor will bias V CF at about.5v. The value of this resistor depends on the V CC supply, as indicated in Table 4. V CC Resistor Value 3.3V.5kΩ 5.V 5Ω Table 4. Resistor Values for TTL Input Cascade Logic is designed to ease cascading multiple devices in order to achieve a greater delay range. The SETM and SETMAX pins accomplish this, as set out in the applications section below. SETM and SETMAX override the delay by changing the value in the D latch register. Table 5 lists the action of these pins. SETM SETMAX Nominal Delay (ps) L L As per D Latch L H H L 22 H H Not Allowed Table 5. SETM and SETMAX Action Table 2. LEN Truth Table The nominal delay value is based on the binary value in D[:9], where D[] is the least significant bit, and D[9] is the most significant bit. This delay from, / to, / is about: t 22 value D 9:, ps = + ( [ ]) 3

14 Signal Path Logic Standard V CC V EE Delay Control Input Choices PECL +4.5V to +5.5V V PECL, CMOS, TTL LVPECL +3.V to +3.6V V LVPECL, CMOS, TTL NECL V 3. to 5.5V NECL Table 6. Signal Path Logic Standard 4

15 APPLICATIONS FORMATION For best performance, use good high frequency layout techniques, filter V CC supplies, and keep ground connections short. Use multiple vias where possible. Also, use controlled impedance transmission lines to interface with the data inputs and outputs. V BB Supply The VBB pin is an internally generated supply, and is available for use only by the. When unused, this pin should be left unconnected. The two common uses for V BB are to handle a single-ended PECL input, and to rebias inputs for AC-coupling applications. If, / is driven by a single-ended output, V BB is used to bias the unused input. Please refer to Figures 7. The PECL signal driving may optionally be inverted in this case. When the signal is AC-coupled, V BB is used, as shown in Figure 8, to re-bias, /. This ensures that inputs are within its acceptable common mode range. In all cases, V BB current sinking our sourcing must be limited to.5ma or less. Setting D Input Logic Thresholds As explained earlier, in all designs where the V EE supply is at zero volts, the D inputs may accommodate CMOS and TTL level signals, as well as PECL or LVPECL. Figures 9 show how to connect V CF and V EF for all possible cases. Cascading Two or more may be cascaded, in order to extend the range of delays permitted. Each additional adds about 22ps to the minimum delay, and adds another 24ps to the delay range. Internal cascade circuitry has been included in the. Using this internal circuitry, may be cascaded without any external gating. Examples of cascading 2, 3, or 4 appear in Figures. Table 7 lists the nominal delay for all the cases that appear in Figures. Control Word (bits) C[] C[9:] D[] D[9:] #2 # / / / / SETM /CASCADE SETMAX CASCADE Figure a. Cascading Two Control Word (2bits) C[] D[] #3 #2 C[] C[9:] D[] D[9:] # / / SETM SETMAX / / SETM /CASCADE SETMAX CASCADE / /CASCADE CASCADE / Figure b. Cascading Three 5

16 Control Word (2bits) C[] D[] C[] D[] C[9:] D[9:] / / SETM SETMAX / / SETM SETMAX / / SETM /CASCADE SETMAX CASCADE / /CASCADE CASCADE / Figure c. Cascading Four RELATED PRODUCT AND SUPPORT DOCUMENTATION Part Number Function Data Sheet Link SYEP96VTI 3.3V/5V Programmable Delay Chip with Fine Tune Control SY55856UHI 2.5V/3.3V 2.5GHz Differential 2-Channel Precision CML Delay Line 6

17 Control Inputs Nominal Delay (ps) D[] D[] D[9:] One Chip Two Chips Three Chips Four Chips 2,2 4,4 6,6 8,8 2,2 4,4 6,6 8,8 2,22 4,42 6,62 8,82 2,24 4,44 6,64 8,84 2,28 4,48 6,68 8,88 2,36 4,56 6,76 8,96 2,52 4,72 6,92 9,2 2,84 5,4 7,24 9,44 3,48 5,68 7,88,8 4,76 6,96 9,6,36 7,32 9,52,72 3,92 2,43 4,63 6,83 9,3 4,64 6,84 9,4 4,65 6,85 9,5 4,66 6,86 9,6 4,68 6,88 9,8 4,72 6,92 9,2 4,8 7, 9,2 4,96 7,6 9,36 5,28 7,48 9,68 5,92 8,2 2,32 7,2 9,4 2,6 9,76 2,96 24,6 24,87 27,7 29,27 27,8 29,28 27,9 29,29 27, 29,3 27,2 29,32 27,6 29,36 27,24 29,44 27,4 29,6 27,72 29,92 28,36 3,56 29,64 3,84 32,2 34,4 37,3 39,5 27,8 39,52 27,9 39,53 27, 39,54 27,2 39,56 27,6 39,6 27,24 39,68 27,4 39,84 27,72 4,6 28,36 4,8 29,64 42,8 32,2 44,64 37,3 49,75 Table 7. List of Nominal Delay Values for Cascaded 7

18 32-P TFP (T32-) Rev. MICREL, C. 28 FORTUNE DRIVE SAN JOSE, CA 953 USA TEL + (48) FAX + (48) 474- WEB The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. 25 Micrel, Incorporated. 8