2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux
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1 2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux Features F MAX = 500MHz 10 pairs of differential LVPECL outputs Low additive jitter, <100fs 12k-20MHz Selectable differential input pairs with single ended input option Input CLK accepts: LVPECL, LVDS, CML, SSTL input level Output skew: 35ps (typ) Operating Temperature: -40 o C to 85 o C Core Power supply: 3.3V ±10%, Output Power supply: 2.5V ±5% & 3.3V ±10% Packaging (Pb-free & Green): 32-pin TQFP (FA) Description The is a high-performance low-skew 1-to-10 LVPECL fanout buffer. The features two selectable differential clock inputs and translates to ten LVPECL outputs. The CLK inputs accept LVPECL, LVDS, CML and SSTL signals. is ideal for clock distribution applications such as providing fanout for low noise SaRonix-eCera oscillators. Block Diagram Pin Configuration V DDO /Q2 Q2 /Q1 Q1 /Q0 Q0 Q3 /Q3 Q4 /Q4 Q5 /Q5 Q6 /Q Q7 /Q7 Q8 /Q8 Q9 /Q9 VDD CLK_SEL CLK0 /CLK0 NC CLK1 /CLK1 VEE Rev B 1 March 2017
2 Pin Description (1) Name Pin # Type Description V EE 8 P Connect to negative power supply CLK_SEL 2 I Clock select input. When high, selects CLK1 input. When low, selects CLK0 input. LVCMOS/LVTTL level with 50kΩ pull down. CLK0 3 I Differential LVPECL clock input with 75kΩ pull-down /CLK0 4 I Inverting differential LVPECL clock input. Defaults to VDD/2 if left floating. CLK1 6 I Differential LVPECL clock input with 75kΩ pull-down /CLK1 7 I Inverting differential LVPECL clock input. Defaults to VDD/2 if left floating. NC 5 No Connect V DDO 9,16, 25,32 P Output Power pin V DD 1 P Core Power Supply Q3, / Q3 24,23 O Differential output pair, LVPECL interface level. Q2, / Q2 27,26 O Differential output pair, LVPECL interface level. Q1, / Q1 29,28 O Differential output pair, LVPECL interface level. Q0, / Q0 31,30 O Differential output pair, LVPECL interface level. Q9, / Q9 11,10 O Differential output pair, LVPECL interface level. Q8, / Q8 13,12 O Differential output pair, LVPECL interface level. Q7, / Q7 15,14 O Differential output pair, LVPECL interface level. Q6, / Q6 18,17 O Differential output pair, LVPECL interface level. Q5, / Q5 20,19 O Differential output pair, LVPECL interface level. Q4, / Q4 22,21 O Differential output pair, LVPECL interface level. Note: 1. I = Input, O = Output, P = Power supply connection. Pin Characteristics Symbol Parameter Conditions Min. Typ. Max. Units R Input Pullup/Pulldown Resistance 50 kω Control Input Function Table Inputs Outputs 0 CLK0 1 CLK1 2
3 Absolute Maximum Ratings (1) V DD Supply voltage Referenced to GND 4.6 V V IN Input voltage Referenced to GND -0.5 V DD +0.5V V IOUT Surge Current 100 ma T STG Storage temperature o C V BB Smk/source Current, I BB ma T J Junction Temperature 125 C Note: 1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These ratings are stress specifications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Operating Conditions V DD Power Supply Voltage V V DDO Output Power Supply Voltage V T A Ambient Temperature o C LVCMOS/LVTTL DC Characteristics (T A = -40 o C to +85 o C, V DD = 3.3V ±5%, V DDO = 2.5V ±5% to 3.3V ±10%) V IH Input High Voltage CLK_SEL 2 V DD +0.3 V V IL Input Low Voltage CLK_SEL I IH Input High Current CLK_SEL V IN = V DD = 3.6V 150 μa I IL Input Low Current CLK_SEL V IN = 0V, V DD = 3.6V -5 μa 3
4 LVPECL DC Characteristics (T A = -40 o C to +85 o C, V DD = 3.3V ±10%, V DDO = 2.5V ±5% to 3.3V ±10%) AC Characteristics (T A = -40 o C to +85 o C, V DD = 3.3V ±10%, V DDO = 2.5V ±5% to 3.3V ±10%) I IH I IL f max Output Frequency 500 MHz t pd Propagation Delay (1) 4 ns Tsk Output-to-output Skew (2) ps t r /t f Output Rise/Fall time 20% - 80% ps odc Output duty cycle f 400 MHz % J add Input High Current Input Low Current Additive jitter CLK0, CLK1 V IN = V DD = 3.6V 150 µa /CLK0, /CLK1 V IN = V DD = 3.6V 150 µa CLK0, CLK1 V DD = 3.6V, V IN = 0V -5 µa /CLK0, /CLK1 V DD = 3.6V, V IN = 0V -150 µa V PP Peak-to-peak Voltage V V CMR Common Mode Input Voltage (1) V EE +1.5 V DD V V OH Output High Voltage (2) V DDO = 2.5V or 3.3V V DDO -1.4 V DDO -0.9 V V OL Output Low Voltage (2) V DDO = 2.5V or 3.3V V DDO -2.0 V DDO -1.7 V V SWING Peak-to-peak Output Voltage Swing V I EE Power Supply 400 MHz ma 1. For single-ended applications, the maximum input voltage for CLK and /CLK is V DD +0.3V 2. Outputs terminated with 50Ω to V DD -2.0V V DD = V DDO = 2.5V or 3.3V 75 fs 1. Measured from the differential input to the differential output crossing point 2 Defined as skew between outputs at the same supply voltage and with equal loads. Measured at the output differential crossing point Additive Jitter Calculation The additive jitter is measured at 12KHz to 20MHz standard noise band with the LVPECL differential input clock at MHz. additive jitter = jitter_out2 - jitter_in2 Summary of Phase Jitter (Diff. Input and Diff. Output) Input Output Additive Jitter Unit V DD = 3.3V, 12kHz-20MHz fs RMS V DD = 2.5V, 12kHz-20MHz fs RMS 4
5 Packaging Mechanical: 32-pin TQFP (FA) 9.00 BSC.354 Square DOCUMENT CONTROL NO. PD REVISION: C DATE: 03/09/05 1 Square BSC.276 Max REF mm GAUGE PLANE Seating Plane BSC X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS 1. Controlling dimensions in millimeters 2. Ref.: JEDEC MS-026D/ABA 3. Package Outline Exclusive of Mold Flash and Metal Burr Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA DESCRIPTION: 32-Pin, Thin Quad Flat Package, TQFP PACKAGE CODE: FA Ordering Information (1,2,3) Ordering Code Package Code Package Description FAE FA Pb-free & Green, 32-pin TQFP FAEX FAE+CWX FA FA Pb-free & Green, 32-pin TQFP, pin 1 orientation on top right in tape and reel Pb-free & Green, 32-pin TQFP, pin 1 orientation on top left in tape and reel 1. Thermal characteristics can be found on the company web site at 2. E = Pb-free & Green 3. X suffix = Tape/Reel Pericom Semiconductor Corporation
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BLOCK DIAGRAM PIN ASSIGNMENTS. 8302I-01 Datasheet. Low Skew, 1-to-2 LVCMOS / LVTTL Fanout Buffer W/ Complementary Output
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ULTRA PRECISION DIFFERENTIAL CML 4:1 MUX WITH 1:2 FANOUT AND INTERNAL I/O TERMINATION
ULTRA PRECISION DIFFERENTIAL CML 4:1 MUX WITH 1:2 FANOUT AND TERNAL I/O TERMATION FEATURES Selects 1 of 4 differential inputs Provides two copies of the selected input Guaranteed AC performance over temperature
PI6C
PIC0 2345789023457890234578902234578902345789023457890223457890234578902345789022345789023457890234578902234578902 Product Features Four synchronous outputs Selectable divider/multiplier Output Enable
PI3C V/3.3V, High Bandwidth, Hot Insertion 10-Bit, 2-Port, Bus Switch
2.5V/3., High Bandwidth, Hot Insertion Features Near-Zero propagation delay 5-ohm switches connect inputs to outputs High Bandwidth (>400 MHz) Permits Hot Insertion. Rail-to-Rail, 3. or 2.5V ing 5V I/O
IDT5V60014 LOW PHASE NOISE ZERO DELAY BUFFER. Description. Features. Block Diagram DATASHEET
DATASHEET IDT5V60014 Description The IDT5V60014 is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates IDT s proprietary analog/digital Phase Locked Loop (PLL) techniques.
3.3V/5V 3GHz PECL/ECL 2:1 MULTIPLEXER
3.3V/5V 3GHz PECL/ECL 2:1 MULTIPLEXER FEATURES 2:1 PECL/ECL multiplexer Guaranteed AC performance over temperature/voltage >3GHz f MAX (toggle)
Description. This Clock Multiplier is the most cost-effective way to Input crystal frequency of 5-40 MHz
PT7C4512 Features Description Zero ppm multiplication error This Clock Multiplier is the most cost-effective way to Input crystal frequency of 5-40 MHz generate a high quality, high frequency clock outputs
ULTRA PRECISION 8:1 MUX WITH INTERNAL TERMINATION AND 1:2 400mV LVPECL FANOUT BUFFER
ULTRA PRECISION 8:1 MUX WITH INTERNAL TERMINATION AND 1:2 400mV LVPECL FANOUT BUFFER FEATURES Selects between 1 of 8 inputs, and provides 2 precision, low skew LVPECL output copies Guaranteed AC performance
NOT RECOMMENDED FOR NEW DESIGNS
NOT RECOMMENDED FOR NEW DESIGNS ULTRA PRECISION 8:1 MUX WITH INTERNAL TERMINATION AND 1:2 400mV LVPECL FANOUT BUFFER FEATURES - Selects between 1 of 8 inputs, and provides 2 precision, low skew LVPECL
Programmable Low Voltage 1:10 LVDS Clock Driver ADN4670
Data Sheet Programmable Low Voltage 1:10 LVDS Clock Driver FEATURES FUNCTIONAL BLOCK DIAGRAM Low output skew
PT7C4511. PLL Clock Multiplier. Features. Description. Pin Configuration. Pin Description
Features Zero ppm multiplication error Input crystal frequency of 5-30 MHz Input clock frequency of - 50 MHz Output clock frequencies up to 200 MHz Peak to Peak Jitter less than 200ps over 200ns interval
4/ 5 Differential-to-3.3V LVPECL Clock Generator
4/ 5 Differential-to- LVPECL Clock Generator 87354 DATASHEET GENERAL DESCRIPTION The 87354 is a high performance 4/ 5 Differential-to- LVPECL Clock Generator. The, n pair can accept most standard differential
ICS571 LOW PHASE NOISE ZERO DELAY BUFFER. Description. Features. Block Diagram DATASHEET
DATASHEET Description The is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates IDT s proprietary analog/digital Phase Locked Loop (PLL) techniques. IDT introduced
Low Skew, 1-to-4 Differential-to-3.3V LVPECL Fanout Buffer
Low Skew, 1-to-4 Differential-to- LVPECL Fanout Buffer 8533I-01 DATA SHEET GENERAL DESCRIPTION The 8533I-01 is a low skew, high performance 1-to-4 Differential-to- LVPECL Fanout Buffer. The 8533I-01 has
100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator
3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator General Description The is a LVTTL/LVCMOS to differential LVPECL translator operating from a single +3.3V supply. Both outputs of a differential
ICS QUAD PLL CLOCK SYNTHESIZER. Description. Features. Block Diagram PRELIMINARY DATASHEET
PRELIMINARY DATASHEET ICS348-22 Description The ICS348-22 synthesizer generates up to 9 high-quality, high-frequency clock outputs including multiple reference clocks from a low frequency crystal or clock
1:2 LVCMOS/LVTTL-to-LVCMOS/LVTTL Zero Delay Buffer for Audio
1: LVCMOS/LVTTL-to-LVCMOS/LVTTL Zero Delay Buffer for Audio ICS8700-05 DATA SHEET General Description The ICS8700-05 is a 1: LVCMOS/LVTTL low phase ICS noise Zero Delay Buffer and is optimized for audio
Low Skew, 1-To-4, Crystal Oscillator/LVCMOS-To-3.3V LVPECL Fanout Buffer
Low Skew, 1-To-4, Crystal Oscillator/LVCMOS-To-3.3V LVPECL Fanout Buffer ICS8535I-31 General Description The ICS8535I-31 is a low skew, high performance ICS 1-to-4 3.3V Crystal Oscillator/LVCMOS-to-3.3V
Features. Applications. Markets
Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with /EN 3.2Gbps, 3.2GHz General Description The is a fully differential, low voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with active-low Enable (/EN).
SY89540U. General Description. Features. Typical Performance. Applications. Precision Low Jitter 4x4 LVDS Crosspoint Switch with Internal Termination
Precision Low Jitter 4x4 LVDS Crosspoint Switch with Internal Termination General Description The is a low-jitter, low skew, high-speed 4x4 crosspoint switch optimized for precision telecom and enterprise
PI74LPT V, 16-Bit Buffer/Line Driver. Features. Description. Block Diagram
Features Compatible with LCX and LVT families of products Supports 5V Tolerant Mixed Signal Mode Operation Input can be 3V or 5V Output can be 3V or connected to 5V bus Advanced Low Power CMOS Operation
Features. Applications. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)
Flexible Ultra-Low Jitter Clock Synthesizer Clockworks FLEX General Description The SM802xxx series is a member of the ClockWorks family of devices from Micrel and provide an extremely low-noise timing
ICS NETWORKING AND PCI CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET Description The is a low cost frequency generator designed to support networking and PCI applications. Using analog/digital Phase Locked-Loop (PLL) techniques, the device uses a standard fundamental
ICS LOW EMI CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET
DATASHEET ICS180-51 Description The ICS180-51 generates a low EMI output clock from a clock or crystal input. The device uses IDT s proprietary mix of analog and digital Phase-Locked Loop (PLL) technology
Features. Applications. Markets
3.2Gbps Precision, LVDS 2:1 MUX with Internal Termination and Fail Safe Input General Description The is a 2.5V, high-speed, fully differential LVDS 2:1 MUX capable of processing clocks up to 2.5GHz and
ICS2304NZ-1 LOW SKEW PCI/PCI-X BUFFER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS2304NZ-1 Description The ICS2304NZ-1 is a high-performance, low skew, low jitter PCI/PCI-X clock driver. It is designed to distribute high-speed signals in PCI/PCI-X applications operating
Features. Applications. Markets
Precision Low-Power Dual 2:1 LVPECL MUX with Internal Termination General Description The features two, low jitter 2:1 differential multiplexers with 100K LVPECL (800mV) compatible outputs, capable of
7GHz, 1:2 CML FANOUT BUFFER/TRANSLATOR WITH INTERNAL I/O TERMINATION
7GHz, 1:2 CML FANOUT BUFFER/TRANSLATOR WITH TERNAL I/O TERMATION Precision Edge FEATURES - Precision 1:2, 400mV CML fanout buffer - Low jitter performance: 49fs RMS phase jitter (typ) - Guaranteed AC performance
Features. Truth Table (1)
3.3V/5V, 4GHz PECL/ECL 2 Clock Generator Precision Edge General Description The is an integrated 2 divider with differential clock inputs. It is functionally equivalent to the SY100EP32V but in an ultra-small
NOT RECOMMENDED FOR NEW DESIGNS. Features. Applications. Markets
NOT RECOMMENDED FOR NEW DESIGNS Low Voltage 1.2V/1.8V/2.5V CML 2x2 Crosspoint Switch 6.4Gbps with Equalization General Description The is a fully-differential, low-voltage 1.2V/1.8V/2.5V CML 2x2 crosspoint
SY89841U. General Description. Features. Applications. Markets. Precision LVDS Runt Pulse Eliminator 2:1 Multiplexer
SY89841U Precision LVDS Runt Pulse Eliminator 2:1 Multiplexer General Description The SY89841U is a low jitter LVDS, 2:1 input multiplexer (MUX) optimized for redundant source switchover applications.