PI90LV031A PI90LV027A PI90LV017A. 3V LVDS High-Speed Differential Line Drivers. Description. Features PI90LV027A PI90LV031A PI90LV017A
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1 PI90LV03A PI90LV027A PI90LV07A 3V LVDS High-Speed Differential Line Drivers Features Signaling Rates >400Mbps (200 MHz) Single 3.3V Power Supply Design ±30mV Differential Swing Maximum Differential Skew of 0.4ns Maximum Propagation Delay of 2.0ns Maximum Power Dissipation: 200 MHz/driver Low Voltage TTL (LVTTL) Inputs Industrial Temperature Operating Range: -40 C to 8 C Meets or Exceeds IEEE 96.3 SCI LVDS Standard Meets or Exceeds ANSI/TIA/EIA-644 LVDS Standard Packaging (Pb-free & Green available): PI90LV07A & PI90LV027A - 8-pin SOIC (W) - 8-pin MSOP (U) PI90LV03A - 6-pin SOIC (W) - 6-pin TSSOP (L) Description The PI90LV03A, PI90LV027A, and PI90LV07A are differential line drivers that use low-voltage differential signaling (LVDS) to support data rates in excess of 400 Mbps. These products are designed for applications requiring high-speed, low-power consumption and low noise generation. A low voltage TTL/CMOS input level is translated by the device into a low-voltage (30mV) differential output signal. Exclusive to the PI90LV03A quad driver is a power-down mode that 3-states the outputs and places the device in a low-power idle state (3mW typical). Applications Applications include point-to-point and multidrop baseband data transmission over controlled impedance media of approximately 00 ohms. The transmission media can be printed circuit board traces, backplanes, or cables. The PI90LV03A, PI90LV027A, PI90LV07A and companion line receivers (PI90LV032A, PI90LV028A, and PI90LV08A) provide new alternatives to RS-232, PECL, and ECL devices for high-speed, point-to-point interface applications. PI90LV027A PI90LV03A DIN D DOUT+ DOUT- VCC DIN DIN2 GND Pin U,W DOUT- DOUT+ DOUT2+ DOUT2- DIN DIN2 D D2 DOUT+ DOUT- DOUT2+ DOUT2- EN DOUT3- DOUT3+ DIN3 DIN DOUT+ DOUT- DOUT2- DOUT2+ DIN2 GND Pin L,W EN* VCC DIN4 DOUT4+ DOUT4- DIN2 DIN3 DIN4 EN EN* D2 D3 D4 DOUT2+ DOUT2- DOUT3+ DOUT3- DOUT4+ DOUT4- PI90LV07A VCC DIN NC GND Pin U,W DOUT- DOUT+ NC NC DIN D DOUT+ DOUT-
2 Function Tables PI90LV03A Enables Input Outputs EN EN D OUT H X H H L H X L L H X L H H L Pin Descriptions Name D O+ D O GND Description TTL/CMOS driver input pins Non-inverting driver output pins Inverting driver output pins Ground pin X L L L H V CC Positive power supply pin, +3.3V ±0% L H X Z Z PI90LV027A Input Outputs Recommended Operating Conditions Min. Typ. Max. Units H H L L L H PI90LV07A Input Outputs Supply Voltage (V CC ) Operating Free Air Temperature V C H H L L L H Absolute Maximum Ratings (see Note, Page 4) Supply Voltage (V CC ) V to +4.0V Input Voltage ( ) V to (V CC +0.3V) Enable Input Voltage (EN, EN*) V to (V CC +0.3V) Output Voltage (, ) V to +3.9V Short Circuit Duration (, )...Continuous S Package... 70mW Derate S Package...8.mW/ C above +2 C Storage Temperature Range...-6 C to +0 C Lead Temperature Range Soldering (4s) C Maximum Junction Temperature...+0 C ESD Rating... 6kV Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2
3 Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 2,3,4) PI90LV03A / PI90LV027A / PI90LV07A Symbol Parameter Conditions Pin Min. Typ. Max. Units V OD Differential Output Voltage mv DV OD Change in Magnitude of V OD for Complementary Output States R L = 00W (Fig.) 4 3 ImVI V OS Offset Voltage V DV OS Change in Magnitude of V OS for Complementary Output States 2 ImVI V OH Output Voltage High.38.6 V V OL Output Voltage Low V IH Input Voltage High EN 2.0 V CC EN* V IL Input Voltage Low GND 0.8 I IH Input Current V IN = V CC or 2.V -0 ± +0 ma I IL Input Current V IN = GND or 0.4V -0 ± +0 V CL Input Clamp Voltage I CL = -8mA V I OS Output Short Circuit Current ENABLED, (0) = V CC, = 0V or = GND, = 0V ma I OSD Differential Output Short Circuit Current ENABLED, V OD = 0V (0) I OFF Power-off Leakage V OUT = 0V or 3.6V, V CC = 0V or Open -20 ± +20 ma I OZ Output Three-State Current EN = 0.8V and EN* = 2.0V V OUT = 0V or V CC -0 ± +0 I CC I CCL No Load Supply Current Drivers Enable Loaded Supply Current Drivers Enabled = V CC or GND R L = 00W All Channels, = V CC or GND (all inputs) V CC ma I CCZ No Load Supply Current Drivers Disabled = V CC or GND, EN = GND, EN* = V CC
4 Switching Characteristics V CC = +3.3V ±0%, T A = -40 C to +8 C (Notes 3,9,) Symbol Parameter Conditions Min. Typ. Max. Units tphld tplhd Differential Propagation Delay High to Low Differential Propagation Delay Low to High Rl = 00W, Cl = 0pF (Figures 2 & 3) tskd Differential Pulse Skew Itphld - tplhdi () ns tskd2 Channel-to-Channel Skew (6) tskd3 Differential Part-to-Part Skew (7) 0.0 tskd4 Differential Part-to-Part Skew (8) 0.2 ttlh Rise Time tthl Fall Time tphz Disable Time High to Z Rl = 00W, tplz Disable Time Low to Z Cl = 0pF (Figures 4 & ) tpzh Enable Time Z to High 7 tpzl Enable Time Z to Low 7 tmax Maximum Operating Frequency (3) MHz Notes:. Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics specifies conditions of device operation. 2. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: V OD and V OD. 3. All typicals are given for: V CC = +3.3V, T A = +2 C. 4. The PI90LV03A/PI90LV027A/PI90LV07A are current mode devices and only functions within datasheet specifications when a resistive load is applied to the driver outputs typical range is (90Ω to 0Ω).. tskd, Itphld - tplhdi is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. 6. tskd2 is the Differential Channel-to-Channel Skew of any event on the same device. 7. tskd3, Differential Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same Vcc and with C of each other within the operating temperature range. 8. tskd4, Part-to-Part Skew, is the differential Channel-to-Channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tskd4 is defined as IMax - MinI differential propagation delay. 9. Generator waveform for all tests unless otherwise specified: f = MHz, Zo = 0Ω, tr ns, and t f ns. 0. Output short circuit current (I OS ) is specified as magnitude only, minus sign indicates direction only.. C L includes probe and jig capacitance. 2. All input voltages are for one channel unless otherwise specified. Other inputs are set to GND. 3. fmax generator input conditions: t R = t F < ns, (0% to 00%), 0% duty cycle, 0V to 3V. Output Criteria: duty cycle = 4%/%, V OD > 20mV, all channels switching. 4
5 Parameter Measurement Information R L /2 V CC GND S DIN D R L /2 V OS V OD Driver ENABLED Figure. Driver V OD and V OS Test Circuit C L Generator D R L 0-Ohm Driver ENABLED C L Figure 2. Driver Propagation Delay and Transition Time Test Circuit
6 Figure 3. Driver Propagation Delay and Transition Time Waveforms Figure 4. Driver Three-State Delay Test Circuit 6
7 Figure. Driver 3-State Delay Waveform Figure 6. Point-to-Point Application 7
8 Packaging Mechanical: 6-Pin SOIC (W) DATE: 06//2 DESCRIPTION: 6-Pin, 0mil Wide SOIC PACKAGE CODE: W DOCUMENT CONTROL #: PD-004 REVISION: F
9 Packaging Mechanical: 8-Pin SOIC (W) 8 DOCUMENT CONTROL NO. PD REVISION: F DATE: 03/09/ x REF SEATING PLANE BSC X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS Notes: ) Controlling dimensions in millimeters. 2) Ref: JEDEC MS-02D/AA Pericom Semiconductor Corporation 34 N. st Street, San Jose, CA DESCRIPTION: 8-Pin, 0-Mil Wide, SOIC PACKAGE CODE: W 9
10 Packaging Mechanical: 6-Pin TSSOP (L) DATE: 0/03/2 Notes:. Refer JEDEC MO-3F/AB 2. Controlling dimensions in millimeters 3. Package outline exclusive of mold flash and metal burr DESCRIPTION: 6-Pin, 73mil Wide TSSOP PACKAGE CODE: L DOCUMENT CONTROL #: PD-30 REVISION: F 0
11 Packaging Mechanical: 8-pin MSOP (U) Gauge Plane Max DOCUMENT CONTROL NO. PD - 26 REVISION: E DATE: 03/09/ Max REF Detail A MAX Detail A MAX Pericom Semiconductor Corporation 34 N. st Street, San Jose, CA Notes: ) Controlling Dimensions inmillimeters 2) Ref. JEDEC MO-87E/AA DESCRIPTION: 8-Pin Mini Small Outline Package, MSOP PACKAGE CODE: U Ordering Information Ordering Code Package Code Package Description PI90LV07AWE W Pb-free & Green, 8-pin SOIC PI90LV07AUE U Pb-free & Green, 8-pin MSOP PI90LV027AWE W Pb-free & Green, 8-pin SOIC PI90LV027AUE U Pb-free & Green, 8-pin MSOP PI90LV03AWE W Pb-free & Green, 6-pin SOIC PI90LV03ALE L Pb-free & Green, 6-pin TSSOP Notes:. Thermal characteristics can be found on the company web site at Pericom Semiconductor Corporation
PI90LV031A. 3V LVDS High-Speed Differential Line Drivers. Description. Features. Applications PI90LV027A PI90LV031A PI90LV017A
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Fast CMOS 3.3V 8-Bit Buffer/Line Driver Features Compatible with LCX and LVT families of products Supports 5V Tolerant Mixed Signal Mode Operation Input can be 3V or 5V Output can be 3V or connected to
PI6C V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux /Q4 /Q5 /Q6 /Q3
LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux Features ÎÎF MAX < 1.5GHz ÎÎ10 pairs of differential LVPECL outputs ÎÎLow additive jitter, < 0.03ps (typ) ÎÎSelectable differential input pairs
Single/Dual LVDS Line Receivers with In-Path Fail-Safe
9-2578; Rev 2; 6/07 Single/Dual LVDS Line Receivers with General Description The single/dual low-voltage differential signaling (LVDS) receivers are designed for high-speed applications requiring minimum
PI2PCIE V, PCI Express Gen2 Compliant, 4-Differential Channel, 2:1 Mux/DeMux Switch
Features 4 Differential Channel, 2:1 Mux/DeMux PCI Express, Gen 2 Performance, 5.0Gbps Low Bit-to-Bit Skew, 7ps max (between '+' and '-' bits) Low Crosstalk: -23dB@3 GHz Low Off Isolation: -23dB@3 GHz
CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS
Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Distributes One Clock Input to Eight Outputs Four Same-Frequency
! Flow-Through Pinout. ! Guaranteed 500Mbps Data Rate. ! 300ps Pulse Skew (Max) ! Conform to ANSI TIA/EIA-644 LVDS Standards. ! Single +3.
AS1150, AS1151 Quad LVDS Receivers 1 General Description The AS1150 and AS1151 are quad flow-through LVDS (low-voltage differential signaling) receivers which accept LVDS differential inputs and convert
DS96172/DS96174 RS-485/RS-422 Quad Differential Line Drivers
DS96172/DS96174 RS-485/RS-422 Quad Differential Line Drivers General Description The DS96172 and DS96174 are high speed quad differential line drivers designed to meet EIA Standard RS-485. The devices
PI2PCIE2422. PCI Express Gen II Compliant, 8-Differential Channel Switch with 8:4 Mux/DeMux Option. Features. Description. Truth Table.
Features 8 Differential Channel SPST switch with Mux/DeMux option PCI Express Gen II performance Low Bit-to-Bit Skew: 10ps (between +/- signals) Low Crosstalk: -15dB @ 3.0 GHz Low Off Isolation: -26db
UT54LVDS032 Quad Receiver Data Sheet September 2015
Standard Products UT54LVDS032 Quad Receiver Data Sheet September 2015 The most important thing we build is trust FEATURES INTRODUCTION >155.5 Mbps (77.7 MHz) switching rates +340mV nominal differential
PI3V312. Low On-Resistance, 3.3V High-Bandwidth 4-Port, 2:1 Mux/DeMux VideoSwitch. Features. Description. Block Diagram. Pin Configuration S 1 Y A 4
Features Near-Zero propagation delay 5Ω switches connect inputs to outputs High signal passing bandwidth (500MHz) Beyond Rail-to-Rail switching 5V I/O tolerant with 3.3V supply 1.8V, 2.5V and 3.3V supply
Single/Dual LVDS Line Receivers with Ultra-Low Pulse Skew in SOT23
19-1803; Rev 3; 3/09 Single/Dual LVDS Line Receivers with General Description The single/dual low-voltage differential signaling (LVDS) receivers are designed for highspeed applications requiring minimum
PI6ULS5V9509 Level Translating I 2 C-Bus/SMBus Repeater with Tiny Package
Features Bidirectional buffer isolates capacitance and allows 400 pf on port B of the device Port A operating supply voltage range of 1.1 V to V CC(B) - 1.0V Port B operating supply voltage range of 2.5
DS90LV048A 3V LVDS Quad CMOS Differential Line Receiver
3V LVDS Quad CMOS Differential Line Receiver General Description The DS90LV048A is a quad CMOS flow-through differential line receiver designed for applications requiring ultra low power dissipation and
100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator
3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator General Description The is a LVTTL/LVCMOS to differential LVPECL translator operating from a single +3.3V supply. Both outputs of a differential
DS91D180/DS91C180 Multipoint LVDS (M-LVDS) Line Driver/Receiver
Multipoint LVDS (M-LVDS) Line Driver/Receiver General Description The DS91D180 and DS91C180 are high-speed differential M- LVDS single drivers/receivers designed for multipoint applications with multiple
PI3PCIE V, PCI Express Lane, (4-Channel), Differential Mux/Demux with Bypass. Features. Description. Truth Table
3.3V, PCI Express 3.0 2-Lane, (4-Channel), Differential Mux/Demux with Bypass Features ÎÎ8 Differential Channel SPST switch with Mux/DeMux option ÎÎPCIe 3.0 performance ÎÎBi-directional operation ÎÎLow
DS26C31T/DS26C31M CMOS Quad TRI-STATE Differential Line Driver
DS26C31T/DS26C31M CMOS Quad TRI-STATE Differential Line Driver General Description The DS26C31 is a quad differential line driver designed for digital data transmission over balanced lines. The DS26C31T
LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver
19-2392; Rev ; 4/2 LVDS or LVTTL/LVCMOS Input to General Description The 125MHz, 14-port LVTTL/LVCMOS clock driver repeats the selected LVDS or LVTTL/LVCMOS input on two output banks. Each bank consists
Description D2+A D2-A D3+A D3-A D0+B D0-B D1+B D1-B D2+B D2-B D3+B D3-B AUX+ A AUX- A HPD A CAB_DETA/LEDA AUX+ B AUX- B HPD B CAB_DETB/LEDB
High Bandwidth 6-differential Channel, 1:2 Demux Features 4 Differential Channel, 1:2 DeMux that will support 2.7Gbps DP rev 1.1a signals 1-channel 1:2 demux for DP_HPD signal 1-differential channel 1:2
MAX9177EUB -40 C to +85 C 10 µmax IN0+ INO- GND. Maxim Integrated Products 1
19-2757; Rev 0; 1/03 670MHz LVDS-to-LVDS and General Description The are 670MHz, low-jitter, lowskew 2:1 multiplexers ideal for protection switching, loopback, and clock distribution. The devices feature
PI90LV9637. LVDS High-Speed Differential Line Receivers. Features. Description. Applications PI90LV9637
LVDS High-Speed Differenial Line Receivers Feaures Signaling Raes >400Mbps (200 MHz) Single 3.3V Power Supply Design Acceps ±350mV (ypical) Differenial Swing Maximum Differenial Skew of 0.35ns Maximum
NOT RECOMMENDED FOR NEW DESIGNS
NOT RECOMMENDED FOR NEW DESIGNS 3.3V, DUAL DIFFERENTIAL LVPECL-TO-LVTTL TRANSLATOR FEATURES 3.3V power supply 2.0ns typical propagation delay
SP26LV431 HIGH SPEED +3.3V QUAD RS-422 DIFFERENTIAL LINE DRIVER
HIGH SPEED +3.3V QUAD RS-422 DIFFERENTIAL LINE DRIVER JUNE 2011 REV. 1.1.1 GENERAL DESCRIPTION The SP26LV431 is a quad differential line driver that meets the specifications of the EIA standard RS-422
PI5L
Wide Bandwidth Low Voltage LanSwitch Quad 2:1 Mux/Demux Features Replaces mechanical relays High-performance, low-cost solution for switching between different LAN signals Ultra-low quiescent power (0.1
SP3486 and SP V Low Power Quad RS-485/RS-422 Line Drivers
SP and SP RS- or RS- Quad ifferential Line rivers Operates from a single +.V supply Interoperable +.0V logic Tri-state Output Control -V to +V Common-Mode Input Voltage Range Common river Enable Control
Is Now Part of To learn more about ON Semiconductor, please visit our website at
Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC
PI6C V Low Skew 1-to-4 LVTTL/LVCMOS to LVPECL Fanout Buffer. Description. Features. Block Diagram. Pin Configuration
Features Maximum operation frequency: 500 MHz 4 pair of differential LVPECL outputs Selectable CLK 0 and inputs CLK 0, accept LVCMOS, LVTTL input level Output Skew: 80ps (maximum) Part-to-part skew: 50ps
UT54LVDS032LV/E Low Voltage Quad Receiver Data Sheet October, 2017
Standard Products UT54LVDS032LV/E Low Voltage Quad Receiver Data Sheet October, 2017 The most important thing we build is trust FEATURES >400.0 Mbps (200 MHz) switching rates +340mV differential signaling
LVDS/Anything-to-LVPECL/LVDS Dual Translator
19-2809; Rev 1; 10/09 LVDS/Anything-to-LVPECL/LVDS Dual Translator General Description The is a fully differential, high-speed, LVDS/anything-to-LVPECL/LVDS dual translator designed for signal rates up
MC3487 QUADRUPLE DIFFERENTIAL LINE DRIVER
Meets or Exceeds Requirements of ANSI EIA/TIA-422-B and ITU Recommendation V. -State, TTL-Compatible s Fast Transition Times High-Impedance Inputs Single -V Supply Power-Up and Power-Down Protection Designed
PI3CH360 3-Channel 2:1 Mux/DeMux, Enable Low 1.8V/2.5V/3.3V, High-Bandwidth, Hot Plug
1.8V/2.5V/3.3V, High-Bandwidth, Hot Plug Features Near-Zero propagation delay 5-ohm switches connect inputs to outputs High signal passing bandwidth (500 MHz) Beyond Rail-to-Rail switching - 0 to 5V switching
DS90C402 Dual Low Voltage Differential Signaling (LVDS) Receiver
DS90C402 Dual Low Voltage Differential Signaling (LVDS) Receiver General Description The DS90C402 is a dual receiver device optimized for high data rate and low power applications. This device along with
SN65LVDM31 HIGH-SPEED DIFFERENTIAL LINE DRIVER
HIH-SPEED DIFFERENTIAL LINE DRIVER Designed for Signaling Rates Up to 5 Mbps Low-Voltage Differential Signaling With Typical Output Voltage of 7 mv and a -Ω Load Propagation Delay Time of. ns, Typical
DS90LV018A 3V LVDS Single CMOS Differential Line Receiver
3V LVDS Single CMOS Differential Line Receiver General Description The DS90LV018A is a single CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise
SN75150 DUAL LINE DRIVER
Meets or Exceeds the Requirement of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Withstands Sustained Output Short Circuit to Any Low-Impedance Voltage Between 25 V and 25 V 2-µs Max Transition Time
14-Bit Registered Buffer PC2700-/PC3200-Compliant
14-Bit Registered Buffer PC2700-/PC3200-Compliant Features Differential Clock Inputs up to 280 MHz Supports LVTTL switching levels on the RESET pin Output drivers have controlled edge rates, so no external
UT54LVDM055LV Dual Driver and Receiver Data Sheet June, 2016
Standard Products UT54LVDM055LV Dual Driver and Receiver Data Sheet June, 2016 The most important thing we build is trust FEATURES INTRODUCTION Two drivers and two receivers with individual enables >400.0