PI6LC48P25104 Single Output LVPECL Clock Generator
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- Samson Garrison
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1 Features ÎÎSingle differential LPECL output ÎÎOutput frequency range: 145MHz to 187.5MHz ÎÎRMS phase MHz, using a 25MHz crystal (12kHz - 20MHz): 0.3ps (typical) ÎÎFull 3.3 or 2.5 supply modes ÎÎCommercial and industrial operating temperature ÎÎAvailable in lead-free package: 8-TSSOP Description The PI6LC48P25104 is a single output LPECL synthesizer optimized to generate Ethernet reference clock frequencies and is a member of Pericom s HiFlex family of high performance clock solutions. Using a 25MHz, it can generate MHz, or 187.5MHz output. Using other crystal frequencies, it can generate other popular frequencies for networking and server storage systems. The PI6LC48P25104 uses Pericom s proprietary low phase noise PLL technology to achieve ultra low phase jitter, so it is ideal for SATA/SAS or Ethernet interface in all kind of systems. Applications ÎÎNetworking systems ÎÎServers and Storage systems Block Diagram Pin Configuration XTAL_IN XTAL_OUT OSC Freq_SEL PFD /M CO /N CLK CLK# DDA GND XTAL_OUT XTAL_IN DD CLK CLK# Freq_SEL 1
2 Pinout Table Pin No. Pin Name I/O Type Description 1 DDA Power Analog Power Supply 2 GND Power Ground 3, 4 XTAL_OUT, XTAL_IN Crystal 5 Freq_SEL Input Pull Down Crystal Input and Output 6, 7 CLK#, CLK Output Output Clock 8 DD Power Core Power Supply "LOW", output is multiplied by 6.25, "HIGH", output is multiplied by 7.5. Output Frequency Table Xtal Frequency (MHz) Freq_SEL Output Frequency (MHz) Typical Crystal Requirement Parameter Minimum Typical Maximum Units Mode of Oscillation Fundamental Frequency Freq_SEL = Freq_SEL = MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pf Drive Level 1 mw Recomended Crystal Specification Pericom recommends: a) FL , SMD 3.2x2.5(4P), 25MHz, CL=18pF, +/-20ppm b) b) FY , SMD 5x3.2(4P), 25MHz, CL=18pF, +/-30ppm 2
3 Maximum Ratings (Over operating free-air temperature range) Note: Storage Temperature ºC to+155ºc Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This Ambient Temperature with Power Applied...-40ºC to+85ºc is a stress rating only and functional operation of the device 3.3 Analog Supply oltage to +3.6 at these or any other conditions above those indicated in ESD Protection (HBM) the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics Power Supply DC Characterisitcs, ( DD = DDA, T A = -40 to 85ºC) Symbol Parameter Condition Min. Typ Max Units DD, DDA Core, Analog Supply oltage DD, DDA Core, Analog Supply oltage I GND Power Supply Current 70 ma I DDA Analog Supply Current 25 ma LPECL DC Electrical Characteristics Symbol Parameter Condition Min. Typ Max Units OH Output High oltage (1) DD = DD = OL Output Low oltage (1) DD = DD = Note: 1. LPECL Termination: Source 150ohm to GND and 100ohm across CLK and CLK#. LPECL AC Electrical Characteristics LPECL Termination: Source 150ohm to GND and using 0.01uF ac-coupled to 50ohm to GND Symbol Parameter Condition Min.. Typ. Max Units f OUT Output Frequency MHz t jit(ø) RMS Phase Jitter, MHz, (12kHz - 20MHz) 0.30 ps (Random) (1) 187.5MHz, (12kHz - 20MHz) 0.33 ps t R / t F Output Rise/Fall Time 20% to 80% 400 ps o DC Output Duty Cycle % Note: 1. Please refer to the Phase Noise Plots. 3
4 Phase Noise Plots f OUT = MHz f OUT = 187.5MHz LPECL Test Circuit 4
5 Power Supply Filtering Techniques As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The PI6LC48P25104 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. DD and DDA should be individually connected to the power supply plane through vias, and 0.1μF bypass capacitors should be used for each pin. Figure below illustrates this for a generic DD pin and also shows that DDA requires that an additional 10Ω resistor along with a 10μF bypass capacitor be connected to the DDA pin. Crystal Input Interface The clock generator has been characterized with 18pF parallel resonant crystals. The capacitor values shown in the figure below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. 5
6 LCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LCMOS signal through an AC coupling capacitor. A general interface diagram is shown in the figure below. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of the two ways. First, R1 and R2 in parallel should equal the transmission line empedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is quaranteed by using a quartz crystal. Thermal Information Symbol Description Condition Q JA Junction-to-ambient thermal resistance Still air O C/W Q JC Junction-to-case thermal resistance 37.0 O C/W 6
7 Packaging Mechanical: 8-Contact TSSOP (L) DATE: 05/03/12 Notes: 1. Refer JEDEC MO-153F/AA 2. Controlling dimensions in millimeters 3. Package outline exclusive of mold flash and metal burr DESCRIPTION: 8 pin, 173mil wide TSSOP PACKAGE CODE: L DOCUMENT CONTROL #: PD-1308 REISION: F Ordering Information Ordering Code Packaging Type Package Description Operating Temperature PI6LC48P25104LE L Pb-free & Green, 8-pin TSSOP Commercial PI6LC48P25104LIE L Pb-free & Green, 8-pin TSSOP Industrial Notes: Thermal characteristics can be found on the company web site at "E" denotes Pb-free and Green Adding an "X" at the end of the ordering code denotes tape and reel packaging Pericom Semiconductor Corporation
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LVPECL Fanout Buffer with Sync OE Features ÎÎF MAX < 1.5GHz ÎÎ10 pairs of differential LVPECL/ ECL outputs ÎÎLow additive jitter, < 0.03ps (typ) ÎÎSelectable differential input pairs with single ended
PI6CL V/1.5V, 200MHz, 1:4 Networking Clock Buffer. Features. Description. Pin Description
Features High-speed, low-noise, non-inverting 1:4 buffer Maximum Frequency up to 200 MHz Low output skew < 100ps Low propagation delay < 3.5ns Optimized duty cycle 3.3 tolerent input 1.2 or 1.5 supply
MK3727D LOW COST 24 TO 36 MHZ 3.3 VOLT VCXO. Description. Features. Block Diagram DATASHEET
DATASHEET MK3727D Description The MK3727D combines the functions of a VCXO (Voltage Controlled Crystal Oscillator) and PLL (Phase Locked Loop) frequency doubler onto a single chip. Used in conjunction
SM General Description. ClockWorks. Features. Applications. Block Diagram
ClockWorks PCI-e Octal 100MHz/200MHz Ultra-Low Jitter, HCSL Frequency Synthesizer General Description The is a member of the ClockWorks family of devices from Micrel and provides an extremely low-noise
ICS83032I 75MHZ, 3 RD OVERTONE OSCILLATOR W/DUAL LVCMOS/LVTTL OUTPUTS. 75MHZ, 3RD OVERTONE Integrated OSCILLATOR W/DUAL ICS83032I
75MHZ, 3RD OVERTONE OSCILLATOR W/DUAL LVCMOS/LVTTL Systems, OUTPUTS Inc. DATA SHEET GENERAL DESCRIPTION The is a SAS/SATA dual output ICS LVCMOS/LVTTL oscillator and a member of the HiPerClockS HiperClocks
LOCO PLL CLOCK MULTIPLIER. Features
DATASHEET ICS501A Description The ICS501A LOCO TM is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands
FemtoClock Crystal-to-LVDS Clock Generator
FemtoClock Crystal-to-LVDS Clock Generator ICS844201-45 DATA SHEET General Description The ICS844201-45 is a PCI Express TM Clock ICS Generator. The ICS844201-45 can synthesize HiPerClockS 100MHz or 125MHz
ICS558A-02 LVHSTL TO CMOS CLOCK DIVIDER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS558A-02 Description The ICS558A-02 accepts a high-speed LVHSTL input and provides four CMOS low skew outputs from a selectable internal divider (divide by 3, divide by 4). The four outputs
ICS CLOCK MULTIPLIER AND JITTER ATTENUATOR. Description. Features. Block Diagram DATASHEET
DATASHEET ICS2059-02 Description The ICS2059-02 is a VCXO (Voltage Controlled Crystal Oscillator) based clock multiplier and jitter attenuator designed for system clock distribution applications. This
Description. Applications
High Performance HCSL Fanout Buffer Features ÎÎ2 HCSL outputs ÎÎUp to 250MHz output frequency ÎÎUltra low additive phase jitter: < 0.1 ps (typ) ÎÎTwo selectable inputs ÎÎLow delay from input to output
ICS7151A-50 SPREAD SPECTRUM CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET
DATASHEET ICS7151A-50 Description The ICS7151A-50 is a clock generator for EMI (Electromagnetic Interference) reduction. Spectral peaks are attenuated by modulating the system clock frequency. Down or
ICS309 SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH. Description. Features. Block Diagram DATASHEET
DATASHEET ICS309 Description The ICS309 is a versatile serially-programmable, triple PLL with spread spectrum clock source. The ICS309 can generate any frequency from 250kHz to 200 MHz, and up to 6 different
ICS MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER 260MHZ, CRYSTAL-TO-LVCMOS ICS84021
DATA SHEET 260MHZ, CRYSTAL-TO-LCMOS LTTL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION The is a general purpose, Crystal-to- ICS LCMOS/LTTL High Frequency Synthesizer HiPerClockS and a member of the HiPerClockS
MK2705 AUDIO CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET MK2705 Description The MK2705 provides synchronous clock generation for audio sampling clock rates derived from an MPEG stream, or can be used as a standalone clock source with a 27 MHz crystal.
MK VCXO AND SET-TOP CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET MK2771-16 Description The MK2771-16 is a low-cost, low-jitter, high-performance VCXO and clock synthesizer designed for set-top boxes. The on-chip Voltage Controlled Crystal Oscillator accepts
ICS553 LOW SKEW 1 TO 4 CLOCK BUFFER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS553 Description The ICS553 is a low skew, single input to four output, clock buffer. Part of IDT s ClockBlocks TM family, this is our lowest skew, small clock buffer. See the ICS552-02 for
ICS650-40A ETHERNET SWITCH CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DTSHEET ICS650-40 Description The ICS650-40 is a clock chip designed for use as a core clock in Ethernet Switch applications. Using IDT s patented Phase-Locked Loop (PLL) techniques, the device takes a
NB3N853531E. 3.3 V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer
3.3 V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer Description The NB3N853531E is a low skew 3.3 V supply 1:4 clock distribution fanout buffer. An input MUX selects either a Fundamental
SM Features. General Description. Applications. Block Diagram. ClockWorks PCI-e Quad 100MHz Ultra-Low Jitter, HCSL Frequency Synthesizer
ClockWorks PCI-e Quad 100MHz Ultra-Low Jitter, HCSL Frequency Synthesizer General Description The is a member of the ClockWorks family of devices from Micrel and provides an extremely low-noise timing
Clock Generator for PowerQUICC III
MOTOROLA SEMICONDUCTOR TECHNICAL DATA The is a PLL based clock generator specifically designed for Motorola Microprocessor And Microcontroller applications including the PowerQUICC III. This device generates
FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER. Features VDD PLL1 PLL2 GND
DATASHEET ICS252 Description The ICS252 is a low cost, dual-output, field programmable clock synthesizer. The ICS252 can generate two output frequencies from 314 khz to 200 MHz using up to two independently
PI5C3253. Dual 4:1 Mux/DeMux Bus Switch
Features Near-Zero propagation delay 5Ω switches connect inputs to outputs Direct bus connection when switches are ON ESD Protection up to 2kV HBM Ultra Low Quiescent Power (0.2μA typical) Ideally suited
IDT5V60014 LOW PHASE NOISE ZERO DELAY BUFFER. Description. Features. Block Diagram DATASHEET
DATASHEET IDT5V60014 Description The IDT5V60014 is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates IDT s proprietary analog/digital Phase Locked Loop (PLL) techniques.