ICS MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER 260MHZ, CRYSTAL-TO-LVCMOS ICS84021

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1 DATA SHEET 260MHZ, CRYSTAL-TO-LCMOS LTTL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION The is a general purpose, Crystal-to- ICS LCMOS/LTTL High Frequency Synthesizer HiPerClockS and a member of the HiPerClockS family of High Performance Clock Solutions from ICS. The has a selectable TEST_CLK or crystal input. The CO operates at a frequency range of 620MHz to 780MHz. The CO frequency is programmed in ste equal to the value of the input reference or crystal frequency. The CO and output frequency can be programmed using the serial or parallel interface to the configuration logic. BLOCK DIAGRAM 260MHZ, CRYSTAL-TO-LCMOS / LTTL FEATURES 2 LCMOS/LTTL outputs Selectable crystal oscillator interface or LCMOS/LTTL TEST_CLK frequency range: 103.3MHz to 260MHz Crystal input frequency range: 14MHz to 40MHz CO range: 620MHz to 780MHz Parallel or serial interface for programming counter and output dividers RMS period jitter: 4.3 (typical) (N 4, DDO = 3.3 ± 5%) RMS phase jitter at MHz, using a 38.88MHz crystal (12kHz to 20MHz): 2.88 (typical) Phase noise: MHz Offset Noise Power 100Hz dbc/hz 1KHz dbc/hz 10KHz dbc/hz 100KHz dbc/hz Full 3.3 or mixed 3.3 core/2.5 or 1.8 supply voltage 0 C to 70 C ambient operating temperature Industrial temperature information available upon request Lead-Free package fully RoHS compliant PIN ASSIGNMENT OE0 OE1 M4 M3 M2 M1 M0 CO_SEL np_load XTAL_IN CO_SEL XTAL_SEL TEST_CLK XTAL_IN XTAL_OUT MR S_LOAD S_DATA S_CLOCK np_load OSC 0 1 PHASE DETECTOR M PLL CO 0 1 CONFIGURATION INTERFACE LOGIC Q0 Q1 TEST M5 M6 M7 M8 N0 N1 nc GND TEST DD OE1 OE0 DDO Q1 Q0 GND Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top iew XTAL_OUT TEST_CLK XTAL_SEL DDA S_LOAD S_DATA S_CLOCK MR M0:M8 N0:N AY RE. C JUNE 9, 2005 IDT / ICS 260MHZ, CRYSTAL-TO-LCMOS LTTL 1 1

2 260MHZ, CRYSTAL-TO-LCMOS LTTL 260MHZ, CRYSTAL-TO-LCMOS / LTTL FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes operation using a MHz crystal. alid PLL loop divider values for different crystal or input frequencies are defined in the Frequency Characteristics, Table 5, NOTE 1. The features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the onchip oscillator. The output of the oscillator is fed into the phase detector. A MHz crystal provides a MHz phase detector reference frequency. The CO of the PLL operates over a range of 620MHz to 780MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the CO output frequency to be M times the reference frequency by adjusting the CO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the CO is scaled by a divider prior to being sent to each of the LCMOS output buffers. The divider provides a 50% output duty cycle. The programmable features of the support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the np_load input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the np_load input, the data is latched and the M divider remains loaded until the next LOW transition on np_load or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the CO frequency, the crystal frequency and the M divider is defined as follows: fco = fxtal x M The M value and the required values of M0 through M8 are shown in Table 3B, Programmable CO Frequency Function Table. alid M values for which the PLL will achieve lock for a MHz reference are defined as M 31. The frequency out is defined as follows: FOUT = fco = fxtal x M N N Serial operation occurs when np_load is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: T1 T0 TEST 0 0 LOW 0 1 S_DATA, Shift Register 1 0 of M divider 1 1 CMOS Fout SERIAL LOADING S_CLOCK S_DATA T1 T0 *NULL N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M 0 S_LOAD t S t H np_load t S M0:M8, N0:N1 M, N PARALLEL LOADING np_load t S t H S_LOAD Time FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: The NULL timing slot must be observed AY RE. C JUNE 9, 2005 IDT / ICS 260MHZ, CRYSTAL-TO-LCMOS LTTL 2 2

3 260MHZ, CRYSTAL-TO-LCMOS LTTL 260MHZ, CRYSTAL-TO-LCMOS / LTTL TABLE 1. PIN DESCRIPTIONS Number Name 1 M5 2, 3, 4, M6, M7, M8, 28, 29, M0, M1, 30, 31, 32 M2, M3, M4 5, 6 N0, N1 7 nc 8, 16 GND 9 TEST 10 DD 11, 12 OE1, OE0 13 DDO 14, 15 Q0, Q1 17 MR 18 S_CLOCK 19 S_DAT A 20 S_LOAD 21 DDA 22 XTAL_SEL 23 TEST_CLK 24, NOTE: XTAL_OUT, XTAL_IN 26 np_load 27 CO_SEL Type Pullup Pulldown Description M divider inputs. Data latched on LOW-to-HIGH transition of np_load input. LCMOS / LTTL interface levels. Pulldown Determines output divider value as defined in Table 3C, Function Table. LCMOS / LTTL interface levels. U nused No connect. P ower Power supply ground. Test output which is ACTIE in the serial mode of operation. driven LOW in parallel mode. LCMOS / LTTL interface levels. P ower Core supply pin. enable. When logic HIGH, the outputs are enabled (default). Pullup When logic LOW, the outputs are in Tri-State. See Table 3E, OE Function Table. LCMOS / LTTL interface levels. P ower supply pin. O utput Clock outputs. LCMOS / LTTL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the outputs to go low. When logic LOW, the Pulldown internal dividers and the outputs are enabled. Assertion of MR does not effect loaded M, N, and T values. LCMOS / LTTL interface levels. Pulldown Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LCMOS / LTTL interface levels. Pulldown Shift register serial input. Data sampled on the rising edge of S_CLOCK. LCMOS / LTTL interface levels. Pulldown Controls transition of data from shift register into the dividers. LCMOS / LTTL interface levels. P ower Analog supply pin. Selects between crystal or test inputs as the PLL reference source. Pullup Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LCMOS / LTTL interface levels P ulldown Test clock input. LCMOS / LTTL interface levels. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Parallel load input. Determines when data present at M8:M0 is Pulldown loaded into M divider, and when data present at N1:N0 sets the N output divider value. LCMOS / LTTL interface levels. Pullup Determines whether synthesizer is in PLL or bypass mode. LCMOS / LTTL interface levels. Pullup and P ulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values AY RE. C JUNE 9, 2005 IDT / ICS 260MHZ, CRYSTAL-TO-LCMOS LTTL 3 3

4 260MHZ, CRYSTAL-TO-LCMOS LTTL 260MHZ, CRYSTAL-TO-LCMOS / LTTL TABLE 2. PIN CHARACTERISTICS Symbol C IN C PD R R R PULLUP PULLDOWN OUT Parameter Test Typical Capacitance 4 pf Power Dissipation (per output) Capacitance DD,, DDA DDO DD, = 3.465, DDA DDO DD, = 3.465, DDA DDO Units = pf = pf = pf Pullup Resistor 51 kω Pulldown Resistor 51 kω Impedance D DO D DO D DO = Ω = Ω = Ω TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE MR s np_load M N S_LOAD S_CLOCK S_DAT A H X X X X X X Reset. Forces outputs LOW. L L Data L Data Data X X X Data L X X L H X X L Data L H X X L Data Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. L H X X L D ata M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. L H X X H D ata S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition TABLE 3B. PROGRAMMABLE CO FREQUENCY FUNCTION TABLE (NOTE 1) CO Frequency (MHz) M Divide M8 M7 M6 M5 M4 M3 M2 M1 M NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of MHz AY RE. C JUNE 9, 2005 IDT / ICS 260MHZ, CRYSTAL-TO-LCMOS LTTL 4 4

5 260MHZ, CRYSTAL-TO-LCMOS LTTL 260MHZ, CRYSTAL-TO-LCMOS / LTTL TABLE 3C. PROGRAMMABLE OUTPUT DIIDER FUNCTION TABLE (PLL ENABLED) s N1 N0 N Divider alue Frequency (MHz) TABLE 3D. COMMONLY USED CONFIGURATION FUNCTION TABLE Crystal (MHz) M Divider alue N Divider alue Frequency (MHz) TABLE 3E. OUTPUT ENABLE & CLOCK ENABLE FUNCTION TABLE Control s OE0 OE1 Q0 Q1 0 0 Hi-Z 0 1 Hi-Z 1 0 Enabled 1 1 Enabled Hi-Z Enabled Hi-Z Enabled 84021AY RE. C JUNE 9, 2005 IDT / ICS 260MHZ, CRYSTAL-TO-LCMOS LTTL 5 5

6 260MHZ, CRYSTAL-TO-LCMOS LTTL 260MHZ, CRYSTAL-TO-LCMOS / LTTL ABSOLUTE MAXIMUM RATINGS Supply oltage, DD 4.6 s, I -0.5 to DD s, O -0.5 to DDO Package Thermal Impedance, θ JA 47.9 C/W (0 lfpm) Storage Temperature, T STG -65 C to 150 C NOTE: Stresses beyond those listed under Absolute Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, DD = DDA =3.3±5%, DDO =3.3±5%, 2.5±5% OR 1.8±5%, TA=0 C TO 70 C Symbol DD DDA DDO I DD I DDA I DDO Parameter Test Typical Core Supply oltage Analog Supply oltage Supply oltage Units Power Supply Current 140 ma Analog Supply Current ma Supply Current 5 ma 84021AY RE. C JUNE 9, 2005 IDT / ICS 260MHZ, CRYSTAL-TO-LCMOS LTTL 6 6

7 260MHZ, CRYSTAL-TO-LCMOS LTTL TABLE 4B. LCMOS / LTTL DC CHARACTERISTICS, DD = DDA =3.3±5%, Symbol IH IL I IH I IL Parameter High oltage Low oltage High Current Low Current 260MHZ, CRYSTAL-TO-LCMOS / LTTL DDO =3.3±5%, 2.5±5% OR 1.8±5%, TA=0 C TO 70 C Test Typical Units CO_SEL, XTAL_SEL, MR, S_LOAD, np_load, S_DATA, 2 S_CLOCK, OE0, OE1, DD N0:N1, M0:M8 TEST_CLK 2 DD CO_SEL, XTAL_SEL, MR, S_LOAD, np_load, S_DATA, S_CLOCK, OE0, OE1, N0:N1, M0:M8 TEST_CLK M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, DD = IN = µ A S_DATA, S_LOAD, np_load M5, OE0, OE1, XTAL_SEL, CO_SEL DD = IN = µ A M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, D D = 3.465, S_DATA, S_LOAD, np_load IN = 0-5 µ A M5, OE0, OE1, XTAL_SEL, CO_SEL OH High oltage; NOTE 1 OL Low oltage; NOTE 1 D D = 3.465, IN = 0 D DO 3.3 ± 5% D DO 2.5 ± 5% D DO 1.8 ± 5% D DO 3.3 ± 5% D DO 2.5 ± 5% -150 µ A = 2. 6 = 1. 8 = DDO = 0. 5 = 0. 5 D DO 1.8 ± 5% = 0. 4 NOTE 1: s terminated with 50Ω to DDO /2. See Parameter Measurement Section, Load Test Diagrams. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, DD = DDA = DDO = 3.3±5%, TA = 0 C TO 70 C Symbol f IN Parameter Frequency Test Typical Units TEST_CLK; NOTE MHz XTAL_IN, NOTE 1 XTAL_OUT; MHz S_CLOCK 50 MHz NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the CO to operate within the 620MHz to 780MHz range. Using the minimum input frequency of 14MHz, valid values of M are 45 M 55. Using the maximum frequency of 40MHz, valid values of M are 16 M 19. TABLE 6. CRYSTAL CHARACTERISTICS Parameter Mode of Oscillation Test Typical Fundamental 84021AY RE. C JUNE 9, 2005 Units Frequency MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance (C ) 7 pf O Drive Level 1 mw IDT / ICS 260MHZ, CRYSTAL-TO-LCMOS LTTL 7 7

8 260MHZ, CRYSTAL-TO-LCMOS LTTL 260MHZ, CRYSTAL-TO-LCMOS / LTTL TABLE 7A. AC CHARACTERISTICS, DD = DDA = DDO = 3.3±5%, TA = 0 C TO 70 C Symbol F OUT Parameter Test Typical Units Frequency MHz t jit(per) Period Jitter, RMS; NOTE 1 N N N N t sk(o) Skew; NOTE 2, t R t S t H / t O utput Rise/Fall Time 20% to 80% F odc Setup Time Hold Time M, N to np_load S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to np_load S_DATA to S_CLOCK S_CLOCK to S_LOAD Duty Cycle % t PLL Lock Time 1 ms LOCK See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at /2 DO NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. D. TABLE 7B. AC CHARACTERISTICS, DD = DDA = 3.3±5%, DDO = 2.5±5%, TA = 0 C TO 70 C Symbol F OUT Parameter Test Typical Units Frequency MHz t jit(per) Period Jitter, RMS; NOTE 1 N N N N t sk(o) Skew; NOTE 2, 3 90 t R t S t H / t O utput Rise/Fall Time 20% to 80% F odc Setup Time Hold Time M, N to np_load S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to np_load S_DATA to S_CLOCK S_CLOCK to S_LOAD Duty Cycle % t PLL Lock Time 1 ms LOCK See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at /2 DO NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. D AY RE. C JUNE 9, 2005 IDT / ICS 260MHZ, CRYSTAL-TO-LCMOS LTTL 8 8

9 260MHZ, CRYSTAL-TO-LCMOS LTTL 260MHZ, CRYSTAL-TO-LCMOS / LTTL TABLE 7C. AC CHARACTERISTICS, DD = DDA = 3.3±5%, DDO = 1.8±5%, TA = 0 C TO 70 C Symbol F OUT Parameter Test Typical Units Frequency MHz t jit(per) Period Jitter, RMS; NOTE 1 N N N N t sk(o) Skew; NOTE 2, t R t S t H / t O utput Rise/Fall Time 20% to 80% F odc Setup Time Hold Time M, N to np_load S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to np_load S_DATA to S_CLOCK S_CLOCK to S_LOAD Duty Cycle % t PLL Lock Time 1 ms LOCK See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at /2 DO NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. D AY RE. C JUNE 9, 2005 IDT / ICS 260MHZ, CRYSTAL-TO-LCMOS LTTL 9 9

10 260MHZ, CRYSTAL-TO-LCMOS LTTL 260MHZ, CRYSTAL-TO-LCMOS / LTTL PARAMETER MEASUREMENT INFORMATION 1.65±5% 2.05±5% 1.±5% DD, DDA, DDO LCMOS GND Qx SCOPE DD, DDA LCMOS GND DDO Qx SCOPE -1.65±5% -1.±5% 3.3 OUTPUT LOAD AC TEST CIRCUIT 2.4±5% 0.9±5% 3.3/2.5 OUTPUT LOAD AC TEST CIRCUIT OH DD, DDA SCOPE REF LCMOS GND DDO -0.9±5% Qx 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains % of all measurements 6σ contains ( x10-7 )% of all measurements Reference Point (Trigger Edge) Histogram Mean Period (First edge after trigger) OL 3.3/1.8 OUTPUT LOAD AC TEST CIRCUIT PERIOD JITTER Qx DDO 2 80% 80% Qy DDO 2 tsk(o) 20% Clock s t R t F 20% OUTPUT SKEW OUTPUT RISE/FALL TIME DDO Q0, Q1 2 t PW t PERIOD odc = t PW t PERIOD x 100% OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 84021AY RE. C JUNE 9, 2005 IDT / ICS 260MHZ, CRYSTAL-TO-LCMOS LTTL 10 10

11 260MHZ, CRYSTAL-TO-LCMOS LTTL 260MHZ, CRYSTAL-TO-LCMOS / LTTL APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. DD, DDA, and DDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 24Ω resistor along with a 10μF and a.01μf bypass capacitor should be connected to each DDA pin. DD DDA μF 24Ω.01μF 10μF FIGURE 2. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 3 below were determined using a MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. C1 22p XTAL_OUT X1 18pF Parallel Crystal C2 22p XTAL_IN Figure 3. CRYSTAL INPUt INTERFACE 84021AY RE. C JUNE 9, 2005 IDT / ICS 260MHZ, CRYSTAL-TO-LCMOS LTTL 11 11

12 260MHZ, CRYSTAL-TO-LCMOS LTTL 260MHZ, CRYSTAL-TO-LCMOS / LTTL APPLICATION SCHEMATIC EXAMPLE Figure 4 shows a schematic example of the. In this example, a series termination is shown. Additional LCMOS termination approaches are shown in the LCMOS Termination Application Note. In this example, an 18pF parallel resonant crystal is used. The C1=22pF and C2=22pF are approximate values for frequency accuracy. The C1 and C2 may be slightly adjusted for optimizing frequency accuracy. C1 X1 C2 22p 18pF 22p U M5 M6 M7 M8 N0 N1 nc GND M4 M3 M2 M1 M0 CO_SEL np_load X_IN X_OUT T_CLK nxtal_sel DDA S_LOAD S_DATA S_CLOCK MR DDA C u DD R7 24 C16 10u DD=3.3 DDO=3.3, 2.5 or 1.8 TEST DD OE1 OE0 DDO Q1 Q0 GND Logic Pin Examples C14 0.1u DD DDO R1 43 Zo = 50 Ohm DD RU1 1K Set Logic to '1' DD Set Logic to '0' RU2 Not Install C15 0.1u R2 43 Zo = 50 Ohm To Logic pins RD1 Not Install RD2 1K To Logic pins FIGURE 4. APPLICATION SCHEMATIC EXAMPLE 84021AY RE. C JUNE 9, 2005 IDT / ICS 260MHZ, CRYSTAL-TO-LCMOS LTTL 12 12

13 260MHZ, CRYSTAL-TO-LCMOS LTTL 260MHZ, CRYSTAL-TO-LCMOS / LTTL RELIABILITY INFORMATION TABLE 8. θ JA S. AIR FLOW TABLE FOR 32 LEAD LQFP θ JA by elocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards 67.8 C/W 55.9 C/W 50.1 C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9 C/W 42.1 C/W 39.4 C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for is: AY RE. C JUNE 9, 2005 IDT / ICS 260MHZ, CRYSTAL-TO-LCMOS LTTL 13 13

14 260MHZ, CRYSTAL-TO-LCMOS LTTL 260MHZ, CRYSTAL-TO-LCMOS / LTTL PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 9. PACKAGE DIMENSIONS SYMBOL JEDEC ARIATION ALL DIMENSIONS IN MILLIMETERS MINIMUM Reference Document: JEDEC Publication 95, MS AY RE. C JUNE 9, 2005 BBA NOMINAL N 32 MAXIMUM A A A b c D D BASIC 7.00 BASIC D Ref. E E BASIC 7.00 BASIC E Ref. e 0.80 BASIC L θ ccc IDT / ICS 260MHZ, CRYSTAL-TO-LCMOS LTTL 14 14

15 260MHZ, CRYSTAL-TO-LCMOS LTTL 260MHZ, CRYSTAL-TO-LCMOS / LTTL TABLE 10. ORDERING INFORMATION Part/Order NOTE: Parts Number Marking 84021AY AY 84021AYT AY 84021AYLF AYLF 84021AYLFT AYLF Package Shipping Packaging 32 Lead LQFP tray Temperature 0 C to 70 C 32 Lead LQFP 1000 tape & reel 0 C to 70 C 32 Lead "Lead-Free" LQFP tray 0 C to 70 C 32 Lead "Lead-Free" LQFP 1000 tape & reel 0 C to 70 C that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments AY RE. C JUNE 9, 2005 IDT / ICS 260MHZ, CRYSTAL-TO-LCMOS LTTL 15 15

16 260MHZ, CRYSTAL-TO-LCMOS LTTL 260MHZ, CRYSTAL-TO-LCMOS / LTTL REISION HISTORY SHEET Rev B C Table Page T T6 T Description of Change Pin Characteristics Table - added R rows. O UT Added Schematic Layout. Changed XTAL naming convention to XTAL_IN/XTAL_OUT throughout the data sheet. Features Section - added Lead-Free bullet. Updated Parallel & Serial Load Operations Diagram. Crystal Characteristics Table - added Drive Level. Ordering Information Table - added Lead-Free package. Date 1/5/04 6/9/ AY RE. C JUNE 9, 2005 IDT / ICS 260MHZ, CRYSTAL-TO-LCMOS LTTL 16 16

17 ICS2 ICS650-40A FIELD ETHERNET 260MHZ, PROGRAMMABLE CRYSTAL-TO-LCMOS SWITCH CLOCK DUAL SOURCE OUTPUT LTTL FREQUENCY SS ERSACLOCK SYNTHESIZER SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: For Sales Fax: For Tech Support Corporate Headquarters Device Technology, Inc Silver Creek alley Road San Jose, CA United States (outside U.S.) Asia Pacific and Japan Device Technology Singapore (1997) Pte. Ltd. Reg. No G 435 Orchard Road #20-03 Wisma Atria Singapore Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Device Technology, Inc. Accelerated Thinking is a service mark of Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA XX-XXXX-XXXXX

ICS83032I 75MHZ, 3 RD OVERTONE OSCILLATOR W/DUAL LVCMOS/LVTTL OUTPUTS. 75MHZ, 3RD OVERTONE Integrated OSCILLATOR W/DUAL ICS83032I

ICS83032I 75MHZ, 3 RD OVERTONE OSCILLATOR W/DUAL LVCMOS/LVTTL OUTPUTS. 75MHZ, 3RD OVERTONE Integrated OSCILLATOR W/DUAL ICS83032I 75MHZ, 3RD OVERTONE OSCILLATOR W/DUAL LVCMOS/LVTTL Systems, OUTPUTS Inc. DATA SHEET GENERAL DESCRIPTION The is a SAS/SATA dual output ICS LVCMOS/LVTTL oscillator and a member of the HiPerClockS HiperClocks