PIN ASSIGNMENT. Q0 nq0. Q1 nq1. Q2 nq2. Q3 nq3

Transcription

1 DIFFERENTIAL-TO-HSTL FANOUT BUFFER DATA SHEET GENERAL DESCRIPTION The is a low skew, high performance 1-to-4 Differential-to-HSTL fanout buffer ICS and a member of the family of High Performance Clock Solutions from ICS. The has two selectable clock inputs. The, pair can accept most standard differential input levels. The, pair can accept LPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the ideal for those applications demanding well defined performance and repeatability. FEATURES 4 differential HSTL compatible outputs Selectable diffferential, or LPECL clock inputs, pair can accept the following differential input levels: LDS, LPECL, HSTL, SSTL, HCSL, supports the following input types: LPECL, CML, SSTL Maximum output frequency: 6MHz Translates any single-ended input signal to HSTL levels with resistor bias on input Output skew: ps (maximum) Part-to-part skew: 2ps (maximum) Propagation delay: 1.6ns (maximum) core, 1.8 output operating supply Lead-Free package available -40 C to 85 C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT _EN _SEL 0 1 D LE Q Q0 nq0 Q1 nq1 Q2 nq2 Q3 nq3 GND _EN _SEL nc nc DD Q0 nq0 DDO Q1 nq1 Q2 nq2 DDO Q3 nq3 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm body package G Package Top iew IDT / ICS 1 1

2 TABLE 1. PIN DESCRIPTIONS Number Name 1 GND 2 _EN 3 _SEL , 9 nc 10 11, 12 nq3, Q3 13, 18 O 14, 15 nq2, Q2 16, 17 nq1, Q1 19, 20 nq0, Q0 NOTE: Pullup a nd Type Description P ower Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follow clock Pullup input. When LOW, Q outputs are forced low, nq outputs are forced high. LCMOS / LTTL interface levels. Clock select input. When HIGH, selects differential, Pulldown inputs. When LOW, selects, inputs. LCMOS / LTTL interface levels. P ulldown Non-inverting differential clock input. P ullup Inverting differential clock input. P ulldown Non-inverting differential LPECL clock input. P ullup Inverting differential LPECL clock input. U nused No connect. P ower Core supply pin. O utput Differential output pair. HSTL interface levels. P ower Output supply pins. O utput Differential output pair. HSTL interface levels. O utput Differential output pair. HSTL interface levels. O utput Differential output pair. HSTL interface levels. P ulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol C IN R R PULLUP PULLDOWN Parameter Test Conditions Minimum Typical Maximum Capacitance 4 pf Pullup Resistor 51 KΩ Pulldown Resistor 51 KΩ Units IDT / ICS 2 2

3 TABLE 3A. CONTROL INPUT FUNCTION TABLE _EN s _SEL 0 0, 0 1, 1 0, Outputs Selected Source Q0:Q3 nq0:nq3 Disabled; LOW Disabled; LOW Enabled Disabled; HIGH Disabled; HIGH Enabled 1 1, Enabled Enabled After _EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the, and, inputs as described in Table 3B.,, Disabled Enabled _EN nq0:nq3 Q0:Q3 FIGURE 1. _EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE or s Outputs or Q0:Q3 nq0:nq3 0 0 LOW 1 1 HIGH 0 Biased; NOTE 1 1 Biased; NOTE 1 LOW HIGH Biased; NOTE 1 0 HIGH Biased; NOTE 1 1 LOW NOTE 1: Please HIGH LOW HIGH LOW LOW HIGH to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inverting Non Inverting Non Inverting Non Inverting Inverting Inverting refer to the Application Information section, "Wiring the Differential to Accept Single Ended Levels". IDT / ICS 3 3

4 ABSOLUTE MAXIMUM RATINGS Supply oltage, 4.6 s, I -0.5 to Outputs, I O Continuous Current ma Surge Current 100mA Package Thermal Impedance, θ JA 73.2 C/W (0 lfpm) Storage Temperature, T STG -65 C to 1 C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, = ±5%, O = 1.8±0.2, TA = 0 C TO 70 C Symbol DDO I DD Parameter Test Conditions Minimum Typical Maximum Core Power Supply oltage Output Power Supply oltage Power Supply Current 55 ma Units TABLE 4B. LCMOS / LTTL DC CHARACTERISTICS, = ±5%, O = 1.8±0.2, TA = 0 C TO 70 C Symbol IH IL I IH I IL Parameter High oltage Low oltage High Current Low Current Test Conditions Minimum Typical Maximum _EN, _SEL _EN, _SEL _EN _SEL _EN _SEL = IN = IN Units = µ A = µ A = 3.465, = 0-1 µ A IN 3.465, = 0-5 µ A = IN TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, = ±5%, O = 1.8±0.2, TA = 0 C TO 70 C Symbol I IH I IL PP Parameter High Current Low Current Test Conditions = IN = IN Minimum Typical Maximum Units = µ A = µ A = 3.465, = 0-1 µ A IN 3.465, = 0-5 µ A = IN Peak-to-Peak oltage Common Mode oltage; C MR 0.5 NOTE 1, 2 DD NOTE 1: For single ended applications the maximum input voltage for and is D D NOTE 2: Common mode voltage is defined as. I H IDT / ICS 4 4

5 TABLE 4D. LPECL DC CHARACTERISTICS, = ±5%, O = 1.8±0.2, TA = 0 C TO 70 C Symbol I IH I IL PP Parameter High Current Low Current Test Conditions = IN = IN Minimum Typical Maximum = Units 1 µ A = µ A = 3.465, = 0-5 µ A IN 3.465, = 0-1 µ A = IN Peak-to-Peak oltage CMR Common Mode oltage; NOTE 1, NOTE 1: Common mode voltage is defined as. I H NOTE 2: For single ended applications the maximum input voltage for and is D D TABLE 4D. HSTL DC CHARACTERISTICS, = ±5%, O = 1.8±0.2, TA = 0 C TO 70 C Symbol Parameter Output High oltage NOTE 1 Output Low oltage NOTE 1 ; O H ; O L OX Test Conditions Minimum Typical Maximum Units O utput Crossover oltage 40% x ( OH - O L ) + OL 60% x ( - ) + OH OL OL Peak-to-Peak SWING Output oltage Swing NOTE 1: Outputs terminated with Ω to ground. TABLE 5. AC CHARACTERISTICS, = ±5%, O = 1.8±0.2, TA = 0 C TO 70 C Symbol f Parameter Test Conditions Minimum Typical Maximum Units Output Frequency 6 MHz MAX t PD ropagation Delay; NOTE 1 P ƒ 6MHz ns t sk(o) Output Skew; NOTE 2, 4 ps t sk(pp) Part-to-Part Skew; NOTE 3, 4 2 ps t R t F Output Rise Time Output Fall Time 20% to MHz ps 20% to MHz ps odc Output Duty Cycle % All parameters measured at 0MHz unless noted otherwise. The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDT / ICS 5 5

6 PARAMETER MEASUREMENT INFORMATION ±5% 1.8±0.2 O Qx SCOPE, HSTL nqx, PP Cross Points CMR GND GND = 0 /1.8 OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEEL nqx Qx Qx PART 1 nqx nqy Qy tsk(o) Qy PART 2 nqy tsk(pp) OUTPUT SKEW PART-TO-PART SKEW Clock Outputs 20% 80% 80% t R t F 20% SWING,, nq0:nq3 Q0:Q3 t PD OUTPUT RISE/FALL TIME PROPAGATION DELAY nq0:nq3 Q0:Q3 Pulse Width t PERIOD odc = t PW t PERIOD odc & t PERIOD IDT / ICS 6 6

7 APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage _REF = /2 is generated by the bias resistors, and C1. This bias circuit should be located as close as possible to the input pin. The ratio of and might need to be adjusted to position the _REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5 and =, _REF should be 1.25 and / = _IN 1K _REF + - C1 0.1uF 1K FIGURE 2. SINGLE ENDED SIGNAL DRIING DIFFERENTIAL INPUT IDT / ICS 7 7

8 DIFFERENTIAL CLOCK INPUT INTERFACE The / accepts LDS, LPECL, HSTL, SSTL, HCSL and other differential signals. Both SWING and OH must meet the PP and CMR input requirements. Figures 3A to 3E show interface examples for the / input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HSTL drivers. If you are using an HSTL driver from another vendor, use their termination recommendation. 1.8 LHSTL ICS LHSTL Driver LPECL R3 FIGURE 3A. HIPERCLOCKS /N INPUT DRIEN BY ICS HIPERCLOCKS HSTL DRIER FIGURE 3B. HIPERCLOCKS /N INPUT DRIEN BY LPECL DRIER LPECL R3 125 R4 125 LDS_Driv er 100 Receiver FIGURE 3C. HIPERCLOCKS /N INPUT DRIEN BY LPECL DRIER FIGURE 3D. HIPERCLOCKS /N INPUT DRIEN BY LDS DRIER LPECL C1 R3 125 R4 125 C2 R R R5,R6 locate near the driver pin. FIGURE 3E. HIPERCLOCKS /N INPUT DRIEN BY LPECL DRIER WITH AC COUPLE IDT / ICS 8 8

9 LPECL CLOCK INPUT INTERFACE The / accepts LPECL, CML, SSTL and other differential signals. Both SWING and OH must meet the PP and CMR input requirements. Figures 4A to 4F show interface examples for the / input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. CML / CML Built-In Pullup 100 / FIGURE 4A. HIPERCLOCKS / INPUT DRIEN BY AN OPEN COLLECTOR CML DRIER FIGURE 4B. HIPERCLOCKS / INPUT DRIEN BY A BUILT-IN PULLUP CML DRIER R3 125 R4 125 LPECL C1 R3 84 R4 84 LPECL R R C / FIGURE 4C. HIPERCLOCKS / INPUT DRIEN BY A LPECL DRIER FIGURE 4D. HIPERCLOCKS / INPUT DRIEN BY A LPECL DRIER WITH AC COUPLE SSTL Zo = 60 Ohm Zo = 60 Ohm R3 120 R4 120 / LDS R5 100 C1 C2 R3 1K R4 1K / K 1K FIGURE 4E. HIPERCLOCKS / INPUT DRIEN BY AN SSTL DRIER FIGURE 4F. HIPERCLOCKS / INPUT DRIEN BY A LDS DRIER IDT / ICS 9 9

10 SCHEMATIC EXAMPLE Figure 5 shows a schematic example of the. In this example, the input is driven by an ICS HSTL driver. The decoupling capacitors should be physically located near the power pin. For, the unused clock outputs can be left floating. Zo = + Zo = LHSTL Driver R K 2 1K U GND Q _EN nq _SEL DDO 17 5 Q nq Q nq NC DDO NC Q3 11 DD nq3 C1 0.1u Zo = Zo = Zo = R4 R C2 0.1u C3 0.1u Zo = R6 R5 - Zo = + Zo = - R8 R7 FIGURE 5. HSTL BUFFER SCHEMATIC EXAMPLE IDT / ICS 10 10

11 POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for = + 5% = 3.465, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Power (core) MAX = _MAX * I DD_MAX = * 55mA = 190.6mW Power (outputs) MAX = 32.6mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 32.6mW = 130.4mW Total Power _MAX (3.465, with all outputs switching) = 190.6mW mW = 321mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for TM devices is 125 C. The equation for Tj is as follows: Tj = θ JA * Pd_total + T A Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6 C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85 C with all outputs switching is: 85 C W * 66.6 C/W = C. This is well below the limit of 125 C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θ JA FOR 20-PIN TSSOP, FORCED CONECTION θ JA by elocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards C/W 98.0 C/W 88.0 C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2 C/W 66.6 C/W 63.5 C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. IDT / ICS 11 11

12 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 6. O Q1 OUT RL Ω FIGURE 6. HSTL DRIER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = ( /R ) * ( - ) OH_MIN L DDO_MAX OH_MIN Pd_L = ( /R ) * ( - ) OL_MAX L DDO_MAX OL_MAX Pd_H = (0.9/Ω) * (2-0.9) = 19.8mW Pd_L = (0.4/Ω) * (2-0.4) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.6mW IDT / ICS 12 12

13 RELIABILITY INFORMATION TABLE 7. θ JA S. AIR FLOW TABLE FOR 20 LEAD TSSOP θ JA by elocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards C/W 98.0 C/W 88.0 C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2 C/W 66.6 C/W 63.5 C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for is: 472 IDT / ICS 13 13

14 PACKAGE OUTLINE - G SUFFIX FOR 20 LEADP TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Minimum Millimeters N 20 Maximum A A A b c D E 6.40 BASIC E e 0.65 BASIC L α 0 8 aaa Reference Document: JEDEC Publication 95, MS-153 IDT / ICS 14 14

15 TABLE 9. ORDERING INFORMATION Part/Order Number ICS8523BGI ICS8523BGIT ICS8523BGILF ICS8523BGILFT Marking ICS8523BGI ICS8523BGI ICS8523BGILF ICS8523BGILF Package Count Temperature 20 lead TSSOP 72 per tube -40 C to 85 C 20 lead TSSOP on Tape and Reel C to 85 C 20 lead "Lead-Free" TSSOP 72 per tube -40 C to 85 C 20 lead "Lead-Free" TSSOP on Tape and Reel C to 85 C The aforementioned trademark, is a trademark of or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. IDT / ICS 15 15

16 Rev Table Page B T5 5 AC Characteristics table. REISION HISTORY SHEET Description of Change t P D ow, changed Min. from 1.2ns to 1.0ns. Date r 1/11/02 B 1 Revised Features section, Bullet 1,6 - took out 1.8 5/6/02 B 8-10 In the Application Information section, added Schematic Examples 10/28/02 T2 2 Pin Characteristics Table - changed C 4pF max. to 4pF typical. I N 4 Absolute Maximum Ratings - changed Output rating. C T4D 5 HSTL DC Characteristics Table - changed 1 min. to 0.9 min. O H 6/23/ Power Considerations - changed Total Power Dissipation to reflect change. O H Calculations changed due to new Total Power Dissipation. Changed LHSTL to HSTL throughout data sheet. C 1 9 Added Lead-Free bullet to Features section. Updated LPECL Clock Interface section. 9/16/04 T9 15 Added Lead-Free Part Number to Ordering Information TAble. IDT / ICS 16 16

17 ICS8521 ICS ICS ICS1522 ICS8705 ICS1893BF Frequency User-Programmable ZERO 3.3- LOW SKEW, 10Base-T/100Base-TX DELAY, Generator 1-TO-9 1-TO-4 DIFFERENTIAL-TO-LCMOS/LTTL LCMOS/LTTL-TO- DIFFERENTIAL-TO-HSTL ideo & Clock Generator/ Buffers PHYceiver for Line-Locked LPECL FANOUT PENTIUM/Pro CLOCK FANOUT BUFFER Clock GENERATOR BUFFER Regenerator Innovate with IDT and accelerate your future networks. Contact: For Sales Fax: For Tech Support Corporate Headquarters Device Technology, Inc Silver Creek alley Road San Jose, CA United States (outside U.S.) Asia Pacific and Japan Device Technology Singapore (1997) Pte. Ltd. Reg. No G 435 Orchard Road #20-03 Wisma Atria Singapore Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Device Technology, Inc. Accelerated Thinking is a service mark of Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA XX-XXXX-XXXXX