FEATURES 2:1 single-ended multiplexer Q nominal output impedance: 15Ω (V DDO BLOCK DIAGRAM PIN ASSIGNMENT 2:1, SINGLE-ENDED MULTIPLEXER ICS83052I

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1 ICS8305I GENERAL DESCRIPTION The ICS8305I is a low skew, :1, Single-ended ICS Multiplexer and a member of the HiPerClockS family of High Performance Clock Solutions from IDT HiPerClockS The ICS8305I has two selectable single-ended clock inputs and one single-ended clock ouut The ouut has a pin which may be set at 33, 5, or 18, making the device ideal for use in voltage trans-lation applications An ouut enable pin places the ouut in a high impedance state which may be useful for testing or debug The device operates up to 50MHz and is packaged in an 8 TSSOP FEATURES :1 single-ended multiplexer Q nominal ouut impedance: 15Ω ( = 33) ouut frequency: 50MHz Propagation delay: 7ns (maximum), ( = = 33) Input skew: 160 (maximum), ( = = 33) Part-to-part skew: 490 (maximum), ( = = 33) Additive phase jitter, RMS at 1555MHz (1kHz - 0MHz): 018 (typical), ( = = 33) Operating supply modes: / 33/33 33/5 33/18 5/5 5/18-40 C to 85 C ambient operating temperature Available in standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT CLK0 CLK1 SEL0 OE Q DDO GND CLK1 DD Q SEL0 CLK0 OE ICS8305I 8-Lead TSSOP 440mm x 30mm x 095mm package body G Package Top iew IDT / ICS 1 ICS8305AGI RE B JUNE 5, 008

2 TABLE 1 PIN DESCRIPTIONS NOTE: Number Name 1 GND 3, 6 CLK1, CLK0 4 5 OE 7 SEL0 Type ower ower Description Ouut supply pin Power supply ground P ulldown Single-ended clock inputs LCMOS/LTTL interface levels Positive supply pin Ouut enable When LOW, ouuts are in HIGH impedance P P Input ower P Input Pullup state When HIGH, ouuts are active LCMOS / LTTL interface levels Input Pulldown C lock select input See Table 3 Control Input Function Table LCMOS / LTTL interface levels O Single-ended clock ouut LCMOS/LTTL interface levels P ulldown refer to internal input resistors See Table, Pin Characteristics, for typical values 8 Q uut Pullup a nd TABLE PIN CHARACTERISTICS C IN R R PULLUP PULLDOWN C PD R OUT nput Capacitance nput Pullup Resistor nput Pulldown Resistor p I 4 F I 51 kω I 51 kω = pf Power Dissipation Capacitance (per ouut) DDO = pf = pf Ouut Impedance 15 Ω TABLE 3 CONTROL INPUT FUNCTION TABLE Control Inputs Input Selected to Q SEL0 0 CLK0 1 CLK1 IDT / ICS ICS8305AGI RE B JUNE 5, 008

3 ABSOLUTE MAXIMUM RATINGS Supply oltage, 46 Inputs, I -05 to + 05 Ouuts, O -05 to + 05 Package Thermal Impedance, θ JA 1017 C/W (0 m) Storage Temperature, T STG -65 C to 150 C NOTE: Stresses beyond those listed under Absolute Ratings may cause permanent damage to the device These ratings are stress specifications only Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied Exposure to absolute maximum rating conditions for extended periods may affect product reliability TABLE 4A POWER SUPPLY DC CHARACTERISTICS, = 33±5%, = 33±5%, 5±5% OR 18±5%,TA = -40 C TO 85 C DDO I DD I DDO ore Supply C oltage Ouut Supply oltage Power Supply Current 40 ma Ouut Supply Current 5 ma TABLE 4B POWER SUPPLY DC CHARACTERISTICS, = 5±5%, = 5±5% OR 18±5%, TA = -40 C TO 85 C DDO I DD I DDO ore Supply C oltage Ouut Supply oltage Power Supply Current 36 ma Ouut Supply Current 5 ma IDT / ICS 3 ICS8305AGI RE B JUNE 5, 008

4 TABLE 4C LCMOS/LTTL DC CHARACTERISTICS, TA = -40 C TO 85 C IH IL I IH I IL OH OL Input High oltage Input Low oltage Input High Current Input Low Current Ouut Higholtage Ouut Low oltage CLK0, SEL0 OE CLK0, SEL0 OE CLK1, CLK1, : Ouuts terminated with 50Ω to D D 33 ± 5% D D 5 ± 5% D D 33 ± 5% 5 ± 5 D 0 3 D 0 3 = D + = 1 7 D + = = D D % D D 33 or 5 ± 5% = 150 µ A D D 33 or 5 ± 5% = 5 µ A D D 33 or 5 ± 5% = -5 µ A D D = 33 or 5 ± 5% -150 µ A = 33 ± 5%; 6 = 5 ± 5%; 1 8 = 18 ± 5%; = 33 ± 5%; 0 5 = 5 ± 5%; 045 = 18 ± 5%; 035 / See Measurement section, "Load Circuit" diagrams TABLE 5A AC CHARACTERISTICS, = = 33 ± 5%, TA = -40 C TO 85 C f MAX LH HL uut Frequency Propagation Delay, Low to High; Propagation Delay, High to Low; nput Skew; NOTE art-to-part Skew; NOTE, Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 uut Rise/Fall Tim uut Duty Cycle 5 MH O 0 z ns ns t sk(i) I t sk(pp) P MHz, tjit Integration Range: 018 1kHz - 0MHz t R / tf O e 0% to 80% odc O % MUXISOLATION MUX Isolation 45 db : Measured from / of the input to / of the ouut DD NOTE : Defined as skew between ouuts on different devices operating a the same supply voltages and with equal load conditions Using the same type of input on each device, the ouut is measured at / NOTE 3: Driving only one input clock NOTE 4: This parameter is defined in accordance with JEDEC Standard 65 IDT / ICS 4 ICS8305AGI RE B JUNE 5, 008

5 TABLE 5B AC CHARACTERISTICS, = 33 ± 5%, = 5 ± 5%, TA = -40 C TO 85 C f MAX LH HL uut Frequency Propagation Delay, Low to High; Propagation Delay, High to Low; nput Skew; NOTE art-to-part Skew; NOTE, Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 uut Rise/Fall Tim uut Duty Cycle 5 MH O 0 z ns ns t sk(i) I t sk(pp) P MHz, tjit Integration Range: 014 1kHz - 0MHz t R / tf O e 0% to 80% odc O % MUXISOLATION MUX Isolation 45 db : Measured from / of the input to / of the ouut DD NOTE : Defined as skew between ouuts on different devices operating a the same supply voltages and with equal load conditions Using the same type of input on each device, the ouut is measured at / NOTE 3: Driving only one input clock NOTE 4: This parameter is defined in accordance with JEDEC Standard 65 TABLE 5C AC CHARACTERISTICS, = 33 ± 5%, = 18 ± 5%, TA = -40 C TO 85 C f MAX LH HL uut Frequency Propagation Delay, Low to High; Propagation Delay, High to Low; nput Skew; NOTE art-to-part Skew; NOTE, Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 uut Rise/Fall Tim uut Duty Cycle 5 MH O 0 z ns ns t sk(i) I t sk(pp) P MHz, tjit Integration Range: 016 1kHz - 0MHz t R / tf O e 0% to 80% odc O % MUXISOLATION MUX Isolation 45 db : Measured from / of the input to / of the ouut DD NOTE : Defined as skew between ouuts on different devices operating a the same supply voltages and with equal load conditions Using the same type of input on each device, the ouut is measured at / NOTE 3: Driving only one input clock NOTE 4: This parameter is defined in accordance with JEDEC Standard 65 IDT / ICS 5 ICS8305AGI RE B JUNE 5, 008

6 TABLE 5D AC CHARACTERISTICS, = = 5 ± 5%, TA = -40 C TO 85 C f MAX LH HL uut Frequency Propagation Delay, Low to High; Propagation Delay, High to Low; nput Skew; NOTE art-to-part Skew; NOTE, Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 uut Rise/Fall Tim uut Duty Cycle 5 MH O 0 z 7 3 ns 7 3 ns t sk(i) I t sk(pp) P MHz, tjit Integration Range: 0 1kHz - 0MHz t R / tf O e 0% to 80% odc O % MUXISOLATION MUX Isolation 45 db : Measured from / of the input to / of the ouut DD NOTE : Defined as skew between ouuts on different devices operating a the same supply voltages and with equal load conditions Using the same type of input on each device, the ouut is measured at / NOTE 3: Driving only one input clock NOTE 4: This parameter is defined in accordance with JEDEC Standard 65 TABLE 5E AC CHARACTERISTICS, = 5 ± 5%, = 18 ± 5%, TA = -40 C TO 85 C f MAX LH HL uut Frequency Propagation Delay, Low to High; Propagation Delay, High to Low; nput Skew; NOTE art-to-part Skew; NOTE, Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 uut Rise/Fall Tim uut Duty Cycle 5 MH O 0 z ns ns t sk(i) I t sk(pp) P MHz, tjit Integration Range: 019 1kHz - 0MHz t R / tf O e 0% to 80% odc O % MUXISOLATION MUX Isolation 45 db : Measured from / of the input to / of the ouut DD NOTE : Defined as skew between ouuts on different devices operating a the same supply voltages and with equal load conditions Using the same type of input on each device, the ouut is measured at / NOTE 3: Driving only one input clock NOTE 4: This parameter is defined in accordance with JEDEC Standard 65 IDT / ICS 6 ICS8305AGI RE B JUNE 5, 008

7 ADDITIE PHASE JITTER The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc Phase Noise This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental This ratio is expressed in decibels (dbm) or a ratio of the power in the 1Hz band to the power in the fundamental When the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal It is mathematically possible to calculate an expected bit error rate given a phase noise plot SSB PHASE NOISE dbc/hz Additive Phase Jitter (Random) at 1555MHz (1kHz - 0MHz) = 018 (typical) 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues The primary issue relates to the limitations of the equipment Often the noise floor of the equipment is higher than the noise floor of the device This is illustrated above The device meets the noise floor of what is shown, but can actually be lower The phase noise is dependant on the input source and measurement equipment IDT / ICS 7 ICS8305AGI RE B JUNE 5, 008

8 PARAMETER MEASUREMENT INFORMATION 165±5% 15±5% SCOPE,, Qx LCMOS LCMOS Qx SCOPE GND GND -165±5% -15±5% 33 CORE/33 OUTPUT LOAD AC TEST CIRCUIT 5 CORE/5 OUTPUT LOAD AC TEST CIRCUIT 05±5% 15±5% 4±5% 09±5% SCOPE SCOPE Qx Qx LCMOS GND LCMOS GND -15±5% -09±5% 33 CORE/5 OUTPUT LOAD AC TEST CIRCUIT 33 CORE/18 OUTPUT LOAD AC TEST CIRCUIT 16±5% 09±5% SCOPE Part 1 Qx Qx LCMOS GND Part Qy tsk(pp) -09±5% 5 CORE/18 OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW IDT / ICS 8 ICS8305AGI RE B JUNE 5, 008

9 CLK0, CLK1 80% 80% Q 0% Clock Ouuts t R t F 0% LH HL PROPAGATION DELAY OUTPUT RISE/FALL TIME CLKx Q Q t PW t PD1 t PERIOD odc = t PW t PERIOD x 100% CLKy Q t PD tsk(i) = t PD t PD1 INPUT SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT / ICS 9 ICS8305AGI RE B JUNE 5, 008

10 APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS: CLK INPUT: For applications not requiring the use of the test clock, it can be left floating Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground CONTROL PINS: All control pins have internal pull-u or pull-downs; additional resistance is not required but can be added for additional protection A 1kΩ resistor can be used RELIABILITY INFORMATION TABLE 6 θ JA S AIR FLOW TABLE FOR 8 LEAD TSSOP θ JA by elocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Boards 1017 C/W 905 C/W 898 C/W TRANSISTOR COUNT The transistor count for ICS8305I is: 967 IDT / ICS 10 ICS8305AGI RE B JUNE 5, 008

11 PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 7 PACKAGE DIMENSIONS SYMBOL Millimeters N 8 A A A b c D E 640 BASIC E e 065 BASIC L α 0 8 aaa Reference Document: JEDEC Publication 95, MO-153 IDT / ICS 11 ICS8305AGI RE B JUNE 5, 008

12 TABLE 8 ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 8305AGI 05AI 8 lead TSSOP tube -40 C to 85 C 8305AGIT 05AI 8 lead TSSOP 500 tape & reel -40 C to 85 C 8305AGILF 5AIL 8 lead "Lead-Free" TSSOP tube -40 C to 85 C 8305AGILFT 5AIL 8 lead "Lead-Free" TSSOP 500 tape & reel -40 C to 85 C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use No other circuits, patents, or licenses are implied This product is intended for use in normal commercial and industrial applications Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT IDT reserves the right to change any circuitry or specifications without notice IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments IDT / ICS 1 ICS8305AGI RE B JUNE 5, 008

13 Rev B Table 4A, 4B T8 REISION HISTORY SHEET Page Description of Change Date 3 Power Supply Tables - corrected min/max 8/7/06 1 Ordering Information Table - added lead-free marking 1 Ordering Information Table - corrected lead-free marking 3/16/07 T4B 3 5 Power Supply Table - corrected units for I & I 6/5/08 DD B T8 B IDT / ICS 13 ICS8305AGI RE B JUNE 5, 008

14 Innovate with IDT and accelerate your future networks Contact: wwwidtcom For Sales (inside USA) (outside USA) Fax: wwwidtcom/go/contactidt For Tech Support Corporate Headquarters Integrated Device Technology, Inc 604 Silver Creek alley Road San Jose, CA United States (inside USA) (outside USA) 008 Integrated Device Technology, Inc All rights reserved Product specifications subject to change without notice IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc Accelerated Thinking is a service mark of Integrated Device Technology, Inc All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners Printed in USA

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