BLOCK DIAGRAM PIN ASSIGNMENT. 8432I-101 Data Sheet. 700MHz, Differential-to-3.3V LVPECL Frequency Synthesizer ICS8432I-101

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1 700MHz, Differential-to-3.3 LPECL Frequency Synthesizer 8432I-101 Data Sheet GENERAL DESCRIPTION The 8432I-101 is a general purpose, dual output Differential-to-3.3 LPECL high frequency synthesizer and a member of the family of High Performance Clock Solutions from IDT. The 8432I-101 has a selectable TEST_CLK or CLK, nclk inputs. The TEST_CLK input accepts LCMOS or LTTL input levels and translates them to 3.3 LPECL levels. The CLK, nclk pair can accept most standard differential input levels. The CO operates at a frequency range of 250MHz to 700MHz. The CO frequency is programmed in steps equal to the value of the input differential or single ended reference frequency. The CO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The low phase noise characteristics of the 8432I-101 makes it an ideal clock source for Gigabit Ethernet and SONET applications. FEATURES Dual differential 3.3 LPECL outputs Selectable CLK, nclk or LCMOS/LTTL TEST_CLK TEST_CLK can accept the following input levels: LCMOS or LTTL CLK, nclk pair can accept the following differential input levels: LPECL, LDS, LHSTL, SSTL, HCSL CLK, nclk or TEST_CLK maximum input frequency: 40MHz Output frequency range: 25MHz to 700MHz CO range: 250MHz to 700MHz Accepts any single-ended input signal on CLK input with resistor bias on nclk input Parallel interface for programming counter and output dividers RMS period jitter: 5ps (maximum) Cycle-to-cycle jitter: 25ps (maximum) 3.3 supply voltage -40 C to 85 C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM P ASSIGNMENT nclk np_load CO_SEL M0 M1 M2 M3 M M5 M6 M7 M8 N0 N1 nc ICS8432I CLK TEST_CLK CLK_SEL A S_LOAD S_DATA S_CLOCK EE MR EE nfout0 FOUT0 O nfout1 FOUT1 TEST 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top iew 2016 Integrated Device Technology, Inc 1

2 FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes operation using a 25MHz clock input. alid PLL loop divider values for different input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. The 8432I-101 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A differential clock input is used as the input to the 8432I This input is fed into the phase detector. A 25MHz clock input provides a 25MHz phase detector reference frequency. The CO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the CO output frequency to be M times the reference frequency by adjusting the CO control voltage. Note, that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the CO is scaled by a divider prior to being sent to each of the LPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the 8432I-101 support two input modes to program the PLL M divider and N output divider. The two input operational modes are parallel and serial. Figure1 shows the timing diagram for each mode. In parallel mode, the np_load input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the np_load input, the data is latched and the M divider remains loaded until the next LOW transition on np_load or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specifi c default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the CO frequency, the input frequency and the M divider is defi ned as follows: fco = f x M The M value and the required values of M0 through M8 are shown in Table 3B, Programmable CO Frequency Function Table. alid M values for which the PLL will achieve lock for a 25MHz reference are defi ned as 8 M 28. The frequency out is defi ned as follows: fout = fco = f x M N N Serial operation occurs when np_load is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: T1 T0 TEST Output 0 0 LOW 0 1 S_Data, Shift Register Input 1 0 Output of M divider 1 1 CMOS Fout FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: The NULL timing slot must be observed Integrated Device Technology, Inc 2

3 TABLE 1. P DESCRIPTIONS Number Name Type Description 1 M5 Input Pullup 2, 3, 4 28, 29 30, 31, 32 M6, M7, M8, M0, M1, M2, M3, M4 Input Pulldown M divider inputs. Data latched on LOW-to-HIGH transistion of np_load input. LCMOS / LTTL interface levels. 5, 6 N0, N1 Input Pulldown Determines output divider value as defi ned in Table 3C, Function Table. LCMOS / LTTL interface levels. 7 nc Unused No connect. 8, 16 EE Power Negative supply pins. 9 TEST Output Test output which is ACTIE in the serial mode of operation. Output driven LOW in parallel mode. LCMOS / LTTL interface levels. 10 Power Core supply pin. 11, 12 FOUT1, nfout1 Output Differential output for the synthesizer. 3.3 LPECL interface levels. 13 O Power Output supply pin. 14, 15 FOUT0, nfout0 Output Differential output for the synthesizer. 3.3 LPECL interface levels. 17 MR Input Pulldown Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inverted outputs nfoutx to go high. When logic LOW, the internal dividers and the outputs are enabled. Assertion of MR does not affect loaded M, N, and T values. LCMOS / LTTL interface levels. 18 S_CLOCK Input Pulldown Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LCMOS / LTTL interface levels. 19 S_DATA Input Pulldown Shift register serial input. Data sampled on the rising edge of S_CLOCK. LCMOS / LTTL interface levels. 20 S_LOAD Input Pulldown Controls transition of data from shift register into the dividers. LC- MOS / LTTL interface levels. 21 A Power Analog supply pin. 22 CLK_SEL Input Pullup Clock select input. Selects between differential clock input or TEST_ CLK input as the PLL reference source. When HIGH, selects CLK, nclk inputs. When LOW, selects TEST_CLK input. LCMOS / LTTL interface levels. 23 TEST_CLK Input Pulldown Test clock input. LCMOS / LTTL interface levels. 24 CLK Input Pulldown Non-inverting differential clock input. 25 nclk Input Pullup Inverting differential clock input. 26 np_load Input Pulldown Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and when data present at N1:N0 sets the N output divider value. LCMOS / LTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. LCMOS 27 CO_SEL Input Pullup / LTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characterisitics, for typical values. TABLE 2. P CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pf R PULLUP Input Pullup Resistor 51 kω R PULLDOWN Input Pulldown Resistor 51 kω 2016 Integrated Device Technology, Inc 3

4 TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE Inputs Conditions MR np_load M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. Forces outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. L H X X L Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. L H X X L Data Contents of the shift register are passed to the M divider and N output divider. L H X X L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial inputs do not affect shift registers. L H X X H Data S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don t care = Rising edge transition = Falling edge transition TABLE 3B. PROGRAMMABLE CO FREQUENCY FUNCTION TABLE CO Frequency M Divide (MHz) M8 M7 M6 M5 M4 M3 M2 M1 M NOTE 1: These M divide values and the resulting frequencies correspond to differential input or TEST_CLK input frequency of 25MHz. TABLE 3C. PROGRAMMABLE OUTPUT DIIDER FUNCTION TABLE Inputs Output Frequency (MHz) N Divider alue N1 N0 Minimum Maximum Integrated Device Technology, Inc 4

5 ABSOLUTE MAXIMUM RATGS Supply oltage, 4.6 Inputs, I -0.5 to Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA 47.9 C/W (0 lfpm) Storage Temperature, T STG -65 C to 150 C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, = A = O = 3.3±5%, TA = -40 C TO 85 C Symbol Parameter Test Conditions Minimum Typical Maximum Units Core Supply oltage A Analog Supply oltage O Output Supply oltage I EE Power Supply Current 120 ma I A Analog Supply Current 15 ma TABLE 4B. LCMOS / LTTL DC CHARACTERISTICS, = A = O = 3.3±5%, TA = -40 C TO 85 C Symbol Parameter Test Conditions Minimum Typical Maximum Units IH IL I IH I IL Input High oltage Input Low oltage Input High Current Input Low Current CO_SEL, CLK_SEL, MR, S_ LOAD, S_DATA, S_CLOCK, np_load, M0:M8, N0:N TEST_CLK CO_SEL, CLK_SEL, MR, S_ LOAD, S_DATA, S_CLOCK, np_load, M0:M8, N0:N TEST_CLK M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_ = = µa DATA, S_LOAD, np_load M5, CLK_SEL, CO_SEL = = µa M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_ DATA, S_LOAD, np_load M5, CLK_SEL, CO_SEL = 3.465, = 0 = 3.465, = 0-5 µa -150 µa OH OL Output High oltage TEST = 3.135, I OH = -36mA Output Low oltage TEST = 3.135, I OL = 36mA Integrated Device Technology, Inc 5

6 TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, = A = O = 3.3±5%, TA = -40 C TO 85 C Symbol Parameter Test Conditions Minimum Typical Maximum Units I IH Input High Current CLK = = µa nclk = = µa I IL Input Low Current CLK = 3.465, = 0-5 µa nclk = 3.465, = µa PP Peak-to-Peak Input oltage CMR Common Mode Input oltage EE NOTE 1: For single ended applications, the maximum input voltage for CLK, nclk is NOTE 2: Common mode voltage is defi ned as IH. TABLE 4D. LPECL DC CHARACTERISTICS, = A = O = 3.3±5%, TA = -40 C TO 85 C Symbol Parameter Test Conditions Minimum Typical Maximum Units OH Output High oltage; NOTE 1 O O OL Output Low oltage; NOTE 1 O O SWG Peak-to-Peak Output oltage Swing NOTE 1: Outputs terminated with 50 Ω to O - 2. TABLE 5. PUT FREQUENCY CHARACTERISTICS, = A = O = 3.3±5%, TA = -40 C TO 85 C Symbol Parameter Test Conditions Minimum Typical Maximum Units TEST_CLK; NOTE MHz f Input Frequency CLK, nclk; NOTE MHz S_CLOCK 25 MHz NOTE 1: For the differential input and TEST_CLK frequency range, the M value must be set for the CO to operate within the 250MHz to 700MHz range. Using the minimum input frequency of 10MHz, valid values of M are 25 M 70. Using the maximum frequency of 25MHz, valid values of M are 10 M 28. TABLE 6. AC CHARACTERISTICS, = A = O = 3.3±5%, TA = -40 C TO 85 C Symbol Parameter Test Conditions Minimum Typical Maximum Units F OUT Output Frequency MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 fco > 350MHz 25 ps tjit(per) Period Jitter, RMS fout > 100MHz 5 ps tsk(o) Output Skew; NOTE 1, 2 15 ps t R / t F Output Rise/Fall Time 20% to 80% ps t S Setup Time M, N to np_load 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns M, N to np_load 5 ns t H Hold Time S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns odc Output Duty Cycle N > % t PW Output Pulse Width N = 1 t PERIOD /2-150 t PERIOD / ps t LOCK PLL Lock Time 1 ms See Parameter Measurement Information section. NOTE 1: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points Integrated Device Technology, Inc 6

7 PARAMETER MEASUREMENT FORMATION 3.3 OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL PUT LEEL PERIOD JITTER CYCLE-TO-CYCLE JITTER OUTPUT SKEW OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 2016 Integrated Device Technology, Inc 7

8 APPLICATION FORMATION STORAGE AREA NETWORKS A variety of technologies are used for interconnection of the elements within a SAN. The tables below list the common application frequencies as well as the 8432I-101 configurations used to generate the appropriate frequency. Table 7. Common SANs Application Frequencies Interconnect Technology Clock Rate Table 8. Configuration Details for SANs Applications Reference Frequency to SERDES (MHz) Crystal Frequency (MHz) Gigabit Ethernet 1.25 GHz 125, 250, , Fibre Channel FC GHz FC GHz , , , 25 Infi niband 2.5 GHz 125, Interconnect Technology Gigabit Ethernet CLK, nclk Input (MHz) 8432I-101 Output Frequency to SERDES (MHz) 8432I-101 M & N Settings M8 M7 M6 M5 M4 M3 M2 M1 M0 N1 N Fiber Channel Fiber Channel Infi niband POWER SUPPLY FILTERG TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 8432I-101 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL., A, and O should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10μF and a.01μf bypass capacitor should be connected to each A pin. A μF 10Ω.01μF 10 μf FIGURE 2. POWER SUPPLY FILTERG 2016 Integrated Device Technology, Inc 8

9 WIRG THE DIFFERENTIAL PUT TO AEPT SGLE ENDED LEELS Figure 3 shows how the differential input can be wired to accept single ended levels. The reference voltage _REF = /2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the _REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5 and = 3.3, _REF should be 1.25 and R2/R1 = Single Ended Clock Input R1 1K CLK _REF nclk C1 0.1u R2 1K FIGURE 3. SGLE ENDED SIGNAL DRIG DIFFERENTIAL PUT RECOMMENDATIONS FOR UNUSED PUT AND OUTPUT PS PUTS: TEST_CLK PUT: For applications not requiring the use of the test clock, it can be left fl oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the TEST_CLK to ground. OUTPUTS: LPECL OUTPUT: All unused LPECL outputs can be left fl oating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left fl oating or terminated. CLK/nCLK PUT: For applications not requiring the use of the differential input, both CLK and nclk can be left fl oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LCMOS CONTROL PS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used Integrated Device Technology, Inc 9

10 DIFFERENTIAL CLOCK PUT TERFACE The CLK /nclk accepts LDS, LPECL, LHSTL, SSTL, HCSL and other differential signals. Both SWG and OH must meet the PP and CMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confi rm the driver termination requirements. For example in Figure 4A, the input termination applies for IDT HiPerClockS LHSTL drivers. If you are using an LHSTL driver from another vendor, use their termination recommendation CLK CLK LHSTL ICS HiPerClockS LHSTL Driver R1 50 R2 50 nclk HiPerClockS Input LPECL R1 50 R3 50 R2 50 nclk HiPerClockS Input FIGURE 4A. HIPERCLOCKS CLK/NCLK PUT DRIEN BY IDT HIPERCLOCKS LHSTL DRIER FIGURE 4B. HIPERCLOCKS CLK/NCLK PUT DRIEN BY 3.3 LPECL DRIER R3 125 R4 125 CLK LDS_Driv er CLK 3.3 LPECL nclk HiPerClockS Input R1 100 nclk Receiver R1 84 R2 84 FIGURE 4C. HIPERCLOCKS CLK/NCLK PUT DRIEN BY 3.3 LPECL DRIER FIGURE 4D. HIPERCLOCKS CLK/NCLK PUT DRIEN BY 3.3 LDS DRIER LPECL C1 R3 125 R CLK C2 nclk HiPerClockS Input R R R1 84 R2 84 R5,R6 locate near the driver pin. FIGURE 4E. HIPERCLOCKS CLK/NCLK PUT DRIEN BY 3.3 LPECL DRIER WITH AC COUPLE 2016 Integrated Device Technology, Inc 10

11 TERMATION FOR LPECL OUTPUTS The clock layout topology shown below is a typical termination for LPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nfout are low impedance follower outputs that generate ECL/LPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FIGURE 5A. LPECL OUTPUT TERMATION FIGURE 5B. LPECL OUTPUT TERMATION 2016 Integrated Device Technology, Inc 11

12 LAYOUT GUIDELE The schematic of the 8432I-101 layout example used in this layout guideline is shown in Figure 6A. The 8432I-101 recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. nclk U CLK R M5 M6 M7 M8 N0 N1 nc EE M4 M3 M2 M1 M0 CO_SEL np_load nclk TEST DD FOUT1/2 nfout1/2 O FOUT nfout EE CLK REF_ nclk_sel DDA S_LOAD S_DATA S_CLOCK MR XTAL_SEL S_LOAD S_DATA S_CLOCK MR A C u C16 10u Termination A 10 Termination B (not shown in the layout) TEST FOUT FOUTN TL1 + R1 125 R C14 0.1u C15 0.1u TL2 - R2 50 R1 50 R2 84 R4 84 R3 50 FIGURE 6A. SCHEMATIC OF RECOMMENDED LAYOUT 2016 Integrated Device Technology, Inc 12

13 The following component footprints are used in this layout example: All the resistors and capacitors are size POWER AND GROUNDG Place the decoupling capacitors C14 and C15 as close as possible to the power pins. If space allows, placing the decoupling capacitor at the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power (ground) plane and the component power (ground) pins. If A shares the same power supply with, insert the RC fi lter R7, C11, and C16 in between. Place this RC fi lter as close to the A as possible. CLOCK TRACES AND TERMATION The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed fi rst and should be locked prior to routing other signal traces. The traces with 50Ω transmission lines TL1 and TL2 at FOUT and nfout should have equal delay and run ad- jacent to each other. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. Keep the clock trace on same layer. Whenever possible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. Make sure no other signal trace is routed between the clock trace pair. The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination schemes can also be used but are not shown in this example. FIGURE 6B. PCB BOARD LAYOUT FOR 8432I Integrated Device Technology, Inc 13

14 POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 8432I-101. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 8432I-101 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for = % = 3.465, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Power (core) MAX = _MAX * I EE_MAX = * 120mA = 416mW Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power _MAX (3.465, with all outputs switching) = 416mW + 60mW = 476mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125 C. The equation for Tj is as follows: Tj = θja * Pd_total + TA Tj = Junction Temperature θja = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θja must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1 C/W per Table 9 below. Therefore, Tj for an ambient temperature of 85 C with all outputs switching is: 85 C W * 42.1 C/W = 105 C. This is well below the limit of 125 C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). TABLE 9. THERMAL RESISTANCE θja FOR 32-P LQFP, FORCED CONECTION θ JA by elocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards 67.8 C/W 55.9 C/W 50.1 C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9 C/W 42.1 C/W 39.4 C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs Integrated Device Technology, Inc 14

15 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LPECL output driver circuit and termination are shown in Figure 7. FIGURE 7. LPECL DRIER CIRCUIT AND TERMATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of O - 2. For logic high, OUT = OH_MAX = O_MAX 0.9 ( O_MAX - OH_MAX ) = 0.9 For logic low, OUT = OL_MAX = 1.7 O_MAX ( O_MAX - OL_MAX ) = 1.7 Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [( ( - 2))/R ] * ( - OH_MAX O_MAX L O_MAX OH_MAX) = [(2 - ( O_MAX - OH_MAX ))/R L ] * ( - O_MAX OH_MAX) = [(2-0.9)/50Ω] * 0.9 = 19.8mW Pd_L = [( ( - 2))/R ] * ( - OL_MAX O_MAX L O_MAX OL_MAX) = [(2 - ( O_MAX - OL_MAX ))/R L ] * ( - O_MAX OL_MAX) = [(2-1.7)/50Ω] * 1.7 = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 2016 Integrated Device Technology, Inc 15

16 RELIABILITY FORMATION TABLE 10. θ JA S. AIR FLOW TABLE FOR 32 LEAD LQFP θ JA by elocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards 67.8 C/W 55.9 C/W 50.1 C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9 C/W 42.1 C/W 39.4 C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for 8432I-101 is: Integrated Device Technology, Inc 16

17 PACKAGE OUTLE - Y SUFFIX FOR 32 LEAD LQFP TABLE 11. PACKAGE DIMENSIONS JEDEC ARIATION ALL DIMENSIONS MILLIMETERS SYMBOL BBA MIMUM NOMAL MAXIMUM N 32 A 1.60 A A b c D D BASIC 7.00 BASIC D E E BASIC 7.00 BASIC E e 0.80 BASIC L θ 0 7 ccc 0.10 Reference Document: JEDEC Publication 95, MS Integrated Device Technology, Inc 17

18 TABLE 12. ORDERG FORMATION Part/Order Number Marking Package Shipping Packaging Temperature 8432DYI-101LF ICS432DI101L 32 Lead Lead-Free LQFP C to 85 C 8432DYI-101LFT ICS432DI101L 32 Lead Lead-Free LQFP tape & reel -40 C to 85 C 2016 Integrated Device Technology, Inc 18

19 REISION HISTORY SHEET Rev Table Page Description of Change Date A B 1 T12 17 T5 6 9 C T4D C C Features Section - added Lead-Free bullet. Ordering Information Table - add Lead-Free parts. Input Frequency Characteristics Table - changed f (TEST_CLK and CLK, nclk) from 14MHz min. to 10MHz min. Added Recommendations for Unused Input and Output Pins. LPECL DC Characteristics Table -corrected OH max. from O to O Power Considerations - corrected power dissipation to refl ect OH max in Table 4D. T12 18 Ordering Information - removed leaded devices. Updated data sheet information. T12 18 Ordering Information - removed ICS from part/order number. Removed 1000 from tape and reel and removed LF note from below the table. Updated headers and footers. 5/23/05 10/26/06 4/10/07 10/23/15 1/8/ Integrated Device Technology, Inc 19

20 Corporate Headquarters 6024 Silver Creek alley Road San Jose, CA USA Sales or Fax: Tech Support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifi cations described herein at any time, without notice, at IDT's sole discretion. Performance specifi cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type defi nitions and a glossary of common terms, visit Copyright 2016 Integrated Device Technology, Inc. All rights reserved.