ICS83032I 75MHZ, 3 RD OVERTONE OSCILLATOR W/DUAL LVCMOS/LVTTL OUTPUTS. 75MHZ, 3RD OVERTONE Integrated OSCILLATOR W/DUAL ICS83032I

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1 75MHZ, 3RD OVERTONE OSCILLATOR W/DUAL LVCMOS/LVTTL Systems, OUTPUTS Inc. DATA SHEET GENERAL DESCRIPTION The is a SAS/SATA dual output ICS LVCMOS/LVTTL oscillator and a member of the HiPerClockS HiperClocks family of high performance devices from ICS. The uses a 3 rd overtone crystal to provide a reference frequency of 75MHz. The has excellent phase jitter performance, over the 900kHz - 7.5MHz integration range. The is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. FEATURES One LVCMOS/LVTTL output, 15Ω output impedence Crystal oscillator interface designed for 3 rd overtone 75MHz crystal frequency range: 53MHz - 80MHz RMS phase 75MHz (900kHz - 7.5MHz): <15fs (typical) 3.3V or.5v operating supply -40 C to 85 C ambient operating temperature Available in both standard and lead-free RoHS-compliant packages BLOCK DIAGRAM PIN ASSIGNMENT Pullup OE 75MHz XTAL_IN XTAL_OUT 3 rd Overtone Crystal Oscillator 75MHz Q0 Q1 OE XTAL_IN XTAL_OUT GND VDD nc Q0 Q1 8-Lead TSSOP 4.40mm x 3.0mm x 0.95mm package body G Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8303AGI REV. B FEBRUARY 13, 006 IDT / ICS 75MHZ, 3RD OVERTONE OSCILLATOR W/DUAL LVCMOS/LVTTL 1 OUTPUTS 1

2 75MHZ, 3RD OVERTONE OSCILLATOR TABLE 1. PIN DESCRIPTIONS Number Name 1 OE, 3 XTAL_IN, XTAL_OUT 4 GND 5, 6 Q1, Q0 7 nc 8 NOTE: Pullup refers to Type Pullup Description enable pin. Standby Function Table. Crystal oscillator interface. XTAL_OUT is the output. Power supply ground P ower. LVCMOS/LVTTL interface levels. See XTAL_IN is the input, Table 3, O utput Single-ended clock outputs. LVCMOS/LVTTL interface levels. U nused No connect. P ower Power and output supply pin. internal input resistors. See Table, Pin Characteristics, for typical values. TABLE. PIN CHARACTERISTICS C IN R R PULLUP OUT Capacitance 4 pf Pullup Resistor 100 kω Impedance = 3.6V 15 Ω =.65V TBD Ω TABLE 3. STANDBY FUNCTION TABLE Control High s OE Q0, Q1 (open) Low fo High Impedance Oscillator Nornal Operation Stopped 8303AGI REV. B FEBRUARY 13, 006 IDT / ICS 75MHZ, 3RD OVERTONE OSCILLATOR

3 75MHZ, 3RD OVERTONE OSCILLATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, 4.6V s, V I -0.5V to V s, V O -0.5V to + 0.5V Package Thermal Impedance, θ JA C/W (0 m) Storage Temperature, T STG -65 C to 150 C NOTE: Stresses beyond those listed under Absolute Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, = 3.3V±0.3V, TA = -40 C TO 85 C I DD ower Supply Voltage Power Supply Current ) D D.. TB. P V OE = V ( output enabled D ma TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, =.5V±5%, TA = -40 C TO 85 C I DD ower Supply Voltage Power Supply Current.37. TB.6 P V OE = V ( output enabled D ma ) D D TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, = 3.3V±0.3V OR.5V±5%, TA = -40 C TO 85 C V IH V IL I IH I IL High Voltage Low Voltage High Current Low Current V OH High Voltage; NOTE 1 V OL Low Voltage; NOTE 1 NOTE 1: s terminated with 50Ω to V " Load " diagrams. = 3.3V V =.5V V = 3.3V V =.5V V = V IN = 3.6V or.65v 5 µ A = 3.6V or.65v, V = 0V IN -150 µ A = 3.6V. 6 V =.65V 1. 8 V = 3.6V or.65v 0. 5 V /. See Measurement Information Section, D D 8303AGI REV. B FEBRUARY 13, IDT / ICS 75MHZ, 3RD OVERTONE OSCILLATOR 3

4 75MHZ, 3RD OVERTONE OSCILLATOR TABLE 5. CRYSTAL CHARACTERISTICS (NOTE 1) Mode of Oscillation 3 rd Overtone MHz Equivalent Series Resistance (ESR) 60 Ω Tolerance ± 30 Stability Over Operating Temperature Range ± 30 Load Capacitance (C ); NOTE L 18 pf Shunt Capacitance (C ) 7 pf O Aging for 5 Years ± 15 Drive Level 1 mw NOTE 1: Using an HC49/US SMD package, the parameters shown above target ±100 accuracy. NOTE : See C rystal Interface in the Application Information Section. TABLE 6A. AC CHARACTERISTICS, = 3.3V±0.3V, TA = -40 C TO 85 C f OUT t jit(ø) MHz RMS Phase Jitter, Random; fout = 75MHz, NOTE 1 (Integration Range: 900kHz-7.5MHz) < 15 fs Deterministic Jitter; NOTE 0. t DJ t RJ andom Jitter; NOTE t RMS R 3 RMS of Total Distribution ( σ ); NOTE 3 Peak-to-Peak Jitter; NOTE 5 Accumulated Jitter ( σ ); NOTE n = to cycles 4 t p-p tacc tsk(o) Skew; NOTE 3, 4 5 Δf/ f O Stability; NOTE 5 ± 10 t OSC t R Oscillation Start Up Time 10 ms / t O utput Rise/Fall Time 0% to 80% 350 F odc Duty Cycle 50 % NOTE 1: Measured using Aeroflex PN9500. NOTE : Measured using Wavecrest SIA NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V /. D D NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This is the frequency error contributed by the oscillator and must be added to the frequency timing error from the crystal to obtain the total frequency stability. See F requency Stability in the Application Information Section. 8303AGI REV. B FEBRUARY 13, IDT / ICS 75MHZ, 3RD OVERTONE OSCILLATOR 4

5 75MHZ, 3RD OVERTONE OSCILLATOR TABLE 6B. AC CHARACTERISTICS, =.5V±5%, TA = -40 C TO 85 C f OUT t jit(ø) MHz RMS Phase Jitter, Random; fout = 75MHz, NOTE 1 (Integration Range: 900kHz-7.5MHz) TBD fs Deterministic Jitter; NOTE 0. t DJ t RJ andom Jitter; NOTE t RMS R 3 RMS of Total Distribution ( σ ); NOTE 3 Peak-to-Peak Jitter; NOTE 5 Accumulated Jitter ( σ ); NOTE n = to cycles 4 t p-p tacc tsk(o) Skew; NOTE 3, 4 Δf/ f O Stability; NOTE 5 ± 10 t OSC t R Oscillation Start Up Time / t O utput Rise/Fall Time 0% to 80% 400 F odc Duty Cycle 50 % NOTE 1: Measured using Aeroflex PN9500. NOTE : Measured using Wavecrest SIA NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V /. D D NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This is the frequency error contributed by the oscillator and must be added to the frequency timing error from the crystal to obtain the total frequency stability. See F requency Stability in the Application Information Section. TBD TBD ms 8303AGI REV. B FEBRUARY 13, IDT / ICS 75MHZ, 3RD OVERTONE OSCILLATOR 5

6 75MHZ, 3RD OVERTONE OSCILLATOR PARAMETER MEASUREMENT INFORMATION 1.65V ± 0.15V Phase Noise Plot LVCMOS Qx SCOPE Noise Power Phase Noise Mask GND Offset f 1 f -1.65V ± 0.15V RMS Jitter = Area Under the Masked Phase Noise Plot 3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER Q0, Q1 80% 80% t PW t PERIOD 0% Clock s t R t F 0% odc = t PW t PERIOD x 100% OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME 8303AGI REV. B FEBRUARY 13, IDT / ICS 75MHZ, 3RD OVERTONE OSCILLATOR 6

7 75MHZ, 3RD OVERTONE OSCILLATOR APPLICATION INFORMATION FREQUENCY STABILITY The table shown below provides a basic guideline in selecting the proper quartz crystal that meets a timing budget of ±100. For more information on selecting the proper crystal, see the application note, Crystal Timing Budget and Accuracy for FemtoClock. Tolerance ± 30 Stability ± 30 Aging for 5 Years ± 15 rd Accuracy of 3 Overtone Oscillator ± 10 Load Capacitance Accuracy ± 3 Total Overall Timing Error ± 88 RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. 8303AGI REV. B FEBRUARY 13, IDT / ICS 75MHZ, 3RD OVERTONE OSCILLATOR 7

8 75MHZ, 3RD OVERTONE OSCILLATOR RELIABILITY INFORMATION TABLE 7. θ JA VS. AIR FLOW TABLE FOR 8 LEAD TSSOP θ JA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Boards C/W 90.5 C/W 89.8 C/W TRANSISTOR COUNT The transistor count for is: AGI REV. B FEBRUARY 13, IDT / ICS 75MHZ, 3RD OVERTONE OSCILLATOR 8

9 75MHZ, 3RD OVERTONE OSCILLATOR PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters N 8 A A A b c D E 6.40 BASIC E e 0.65 BASIC L α 0 8 aaa Reference Document: JEDEC Publication 95, MO AGI REV. B FEBRUARY 13, IDT / ICS 75MHZ, 3RD OVERTONE OSCILLATOR 9

10 75MHZ, 3RD OVERTONE OSCILLATOR TABLE 9. ORDERING INFORMATION Part/Order Number ICS8303AGI ICS8303AGIT ICS8303AGILF ICS8303AGILFT NOTE: Parts Marking Package Shipping Packaging 303AI 8 lead TSSOP tube Temperature -40 C to 85 C 303AI 8 lead TSSOP 500 tape & reel -40 C to 85 C 03AIL 8 lead "Lead-Free" TSSOP tube -40 C to 85 C 03AIL 8 lead "Lead-Free" TSSOP 500 tape & reel -40 C to 85 C that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8303AGI REV. B FEBRUARY 13, IDT / ICS 75MHZ, 3RD OVERTONE OSCILLATOR 10

11 ICS5 ICS650-40A FIELD ETHERNET 75MHZ, PROGRAMMABLE 3RD SWITCH OVERTONE CLOCK OSCILLATOR DUAL SOURCE OUTPUT W/DUAL SS VERSACLOCK LVCMOS/LVTTL SYNTHESIZER OUTPUTS Innovate with IDT and accelerate your future networks. Contact: For Sales Fax: For Tech Support Corporate Headquarters Device Technology, Inc. 604 Silver Creek Valley Road San Jose, CA United States (outside U.S.) Asia Pacific and Japan Device Technology Singapore (1997) Pte. Ltd. Reg. No G 435 Orchard Road #0-03 Wisma Atria Singapore Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT 7DE Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Device Technology, Inc. Accelerated Thinking is a service mark of Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA XX-XXXX-XXXXX

ICS83056I-01. General Description. Features. Block Diagram. Pin Assignment 6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER ICS83056I-01

ICS83056I-01. General Description. Features. Block Diagram. Pin Assignment 6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER ICS83056I-01 ICS83056I-01 General Description The ICS83056I-01 is a 6-bit, :1, Single-ended ICS LVCMOS Multiplexer and a member of the HiPerClockS HiPerClockS family of High Performance Clock Solutions from IDT. The