ICS87008I LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

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1 GENERAL DESCRIPTION The ICS87008I is a low skew, 1:8 LCMOS/LTTL Clock Generator. The device has banks of 4 outputs and each bank can be independently selected for 1 or frequency operation. Each bank also has its own power supply pi so that the banks can operate at the following different voltage levels: 3.3,.5, and 1.8. The low impedance LCMOS/ LTTL outputs are designed to drive 50Ω series or parallel terminated tramission lines. The divide select inputs, DI_SELA and DI_SELB, control the output frequency of each bank. The output banks can be independently selected for 1 or operation. The bank enable inputs, CLK_ENA and CLK_ENB, support enabling and disabling each bank of outputs individually. The CLK_ENA and CLK_ENB circuitry has a synchronizer to prevent runt pulses when enabling or disabling the clock outputs. The master reset input, nmr/oe, resets the 1/ flip flo and also controls the active and high impedance states of all outputs. This pin has an internal pull-up resistor and is normally used only for test purposes or in systems which use low power modes. The ICS87008I is characterized to operate with the core at 3.3 or.5 and the banks at 3.3,.5, or 1.8. Guaranteed bank, output, and part-to-part skew characteristics make the 87008I ideal for those clock applicatio demanding well-defined performance and repeatability. FEATURES Eight LCMOS/LTTL outputs ( banks of 4 outputs) Selectable differential CLK1, nclk1 or LCMOS clock input CLK1, nclk1 pair can accept the following differential input levels: LPECL, LDS, LHSTL, SSTL, HCSL CLK0 supports the following input types: LCMOS, LTTL output frequency: 50MHz Independent bank control for 1 or operation Glitchless, asynchronous clock enable/disable skew: core/3.3 output Bank skew: core/3.3 output 3.3 or.5 core/3.3,.5, or 1.8 output operating supply -40 C to 85 C ambient operating temperature Available in both standard and lead-free RoHS compliant packages BLOCK DIAGRAM PIN ASSIGNMENT nmr/oe DI_SELA CLK1 nclk1 CLK0 CLK_ENA CLK_SEL CLK_ENB DI_SELB LE D LE D 4 4 QA0:QA3 QB0:QB3 CLK1 nclk1 OA QA0 QA1 QA QA3 OA DI_SELA CLK_ENA CLK0 CLK_SEL OB QB0 QB1 QB QB3 OB DI_SELB CLK_ENB nmr/oe ICS87008I 4-Lead TSSOP 4.4mm x 7.8mm x 0.9mm body package G Package Top iew 1

2 TABLE 1. PIN DESCRIPTIONS Number Name 1 CLK1 nclk1 3, 9 OA 4, 5, 7, 8 QA0, QA1, QA, QA3 6, DI_SELA 11 CLK_ENA 1 13 nmr/oe 14 CLK_ENB 15 DI_SELB 16, OB 17, 18, 0, 1 QB3, QB, QB1, QB0 3 CLK_SEL NOTE: 4 CLK0 TABLE. PIN CHARACTERISTICS C IN R R PULLUP PULLDOWN C PD R OUT Type Description P ulldown Non-inverting differential clock input. Pullup/ Pulldown Inverting differential clock input. P ower Bank A supply pi. / default when left floating. D D O utput Bank A outputs. LCMOS / LTTL interface levels. P ower Supply ground. Pullup Controls frequency division for Bank A outputs. LCMOS / LTTL interface levels. Pullup enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive low. LCMOS / LTTL interface levels. P ower Power supply pin. Pullup Master reset. When LOW, resets the 1/ flip flo and sets the outputs to high impedance. LCMOS / LTTL interface levels. Pullup enable for Bank B outputs. Active HIGH. If pin is LOW, outputs drive low. LCMOS / LTTL interface levels. Pullup Controls frequency division for Bank B outputs. LCMOS / LTTL interface levels.. P ower Bank B supply pi. O utput Bank B outputs. LCMOS / LTTL interface levels. Pulldown Clock select input. When HIGH, selects CLK1, nclk1 inputs. When LOW, selects CLK0 input. LCMOS / LTTL interface levels. P ulldown LCMOS / LTTL clock input. Pullup and P ulldown refer to internal input resistors. See Table, Pin Characteristics, for typical values. Conditio Capacitance 4 pf Pullup Resistor 51 kω Pulldown Resistor 51 kω Power Dissipation Capacitance (per output), Ox 3.465; NOTE 1, Ox.65; NOTE 1 = 3.465, Ox.65; NOTE 1 = 3.465, Ox 1.89; NOTE 1 =.65, Ox 1.89; NOTE 1 = 18 pf = 0 pf = 0 pf = 30 pf = 0 pf Impedance 7 Ω NOTE 1: Ox denotes and. OA OB TABLE 3. FUNCTION TABLE nmr/oe s CLK_ENx DI_SELx Bank 0 X X Hi Z X s Qx Frequency N/ A Active fin/ Active 1 0 X Low fin N/ A

3 ABSOLUTE MAXIMUM RATINGS Supply oltage, 4.6 s, I -0.5 to s, O -0.5 to O Package Thermal Impedance, θ JA 70 C/W (0 lfpm) Storage Temperature, T STG -65 C to 150 C NOTE: Stresses beyond those listed under Absolute Ratings may cause permanent damage to the device. These ratings are stress specificatio only. Functional operation of product at these conditio or any conditio beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditio for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, = 3.3±5% OR.5±5%, TA = -40 C TO 85 C Power Supply oltage OA, Supply oltage; NOTE 1 OB I I I utput Supply Current; NOTE OA, OB Conditio Power Supply Current 54 ma O 6. 5 ma 3

4 TABLE 4B. LCMOS/LTTL DC CHARACTERISTICS, = 3.3±5% OR.5±5%, TA = -40 C TO 85 C IH IL High oltage Low oltage Conditio DI_SELA, DI_SELB, CLK_ENA, CLK_ENB, nmr/oe, CLK_SEL CLK DI_SELA, DI_SELB, CLK_ENA, CLK_ENB, nmr/oe, CLK_SEL CLK DI_SELA, DI_SELB, CLK_ENA, CLK_ENB, = I N = 3.465, nmr/oe = IN =.65 5 µ A I IH High Current CLK0, CLK_SEL = I N = 3.465, 150 µ A = IN =.65 DI_SELA, DI_SELB, CLK_ENA, CLK_ENB, = 3.465, = 0 IN -150 µ A I nmr/oe =.65, = 0 IN IL Low Current CLK0, CLK_SEL = 3.465, = 0 IN -5 µ A =.65, = 0 IN Ox = 3.3 ± 5%; NOTE. 6 OH High oltage; NOTE 1 Ox =.5 ± 5%; NOTE 1. 8 Ox = 1.8 ± 5%; NOTE 1. 5 Ox = 3.3 ± 5%; NOTE 0. 5 OL Low oltage; NOTE 1 Ox =.5 ± 5%; NOTE 0. 5 Ox = 1.8 ± 5%; NOTE 0. 4 IOZL Tristate Current Low -5 µ A IOZH Tristate Current High 5 µ A NOTE 1: s terminated with 50Ω to /. See Measurement Information, Load Circuits. NOTE : denotes and D DOx,. OA D DOB TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, = = 3.3±5% OR.5±5%, TA = -40 C TO 85 C I IH I IL High Current Low Current nclk1 CLK1 nclk1 CLK1 IN IN IN IN Conditio IN IN IN IN = = 3.465, D D =.65 = = = 3.465, D D = =.65 = 0, = 3.465, D D 0, =.65 = = 0, = 3.465, D D = 0, =.65 5 µ A 150 µ A -150 µ A -5 µ A PP Peak-to-Peak oltage Common Mode oltage; C MR NOTE 1, N OTE 1: For single ended applicatio, the maximum input voltage for CLK1, nclk1 is D D NOTE : Common mode voltage is defined as. I H 4

5 TABLE 5A. AC CHARACTERISTICS, = OX = 3.3±5%, TA = -40 C TO 85 C f MAX tp LH Conditio Frequency 50 MHz Propagation Low to High Delay, t sk(b) ank Skew; NOTE, 6 CLK0; NOTE 1A CLK1, nclk1; NOTE 1B B 0 t sk(o) Skew; NOTE 3, t sk(pp) Part-to-Part Skew; NOTE 4, / tf O utput Rise/Fall Time 0% to 80% t R odc Duty Cycle f 133MHz % t EN utput Enable Time; NOTE 5 tdis utput Disable Time; NOTE 5 All parameters measured at 50MHz using CLK1, nclk1 unless noted otherwise. NOTE 1A: Measured from the / of the input to / of the output. NOTE 1B: Measured from the differential input crossing point to / of the output. NOTE : Defined as skew within a bank with equal load conditio. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditio. Measured at /. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditio. Using the same type of input on each device, the output is measured at /. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. TABLE 5B. AC CHARACTERISTICS, = OX =.5±5%, TA = -40 C TO 85 C f MAX Conditio Frequency 50 MHz CLK0; NOTE 1A Propagation Delay, tplh Low to High CLK1, nclk1; NOTE 1B t sk(b) Bank Skew; NOTE, 6 35 t sk(o) Skew; NOTE 3, t sk(pp) Part-to-Part Skew; NOTE 4, 6 1 / tf O utput Rise/Fall Time 0% to 80% t R odc Duty Cycle f 15MHz % t EN utput Enable Time; NOTE 5 tdis utput Disable Time; NOTE 5 All parameters measured at 50MHz using CLK1, nclk1 unless noted otherwise. NOTE 1A: Measured from the / of the input to / of the output. NOTE 1B: Measured from the differential input crossing point to / of the output. NOTE : Defined as skew within a bank with equal load conditio. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditio. Measured at /. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditio. Using the same type of input on each device, the output is measured at /. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. 5

6 TABLE 5C. AC CHARACTERISTICS, = 3.3±5%, OX =.5±5%, TA = -40 C TO 85 C f MAX tp LH Conditio Frequency 50 MHz Propagation Low to High Delay, t sk(b) ank Skew; NOTE, 6 CLK0; NOTE 1A CLK1, nclk1; NOTE 1B B 0 t sk(o) Skew; NOTE 3, t sk(pp) Part-to-Part Skew; NOTE 4, / tf O utput Rise/Fall Time 0% to 80% t R odc Duty Cycle f 133MHz % t EN utput Enable Time; NOTE 5 tdis utput Disable Time; NOTE 5 All parameters measured at 50MHz using CLK1, nclk1 unless noted otherwise. NOTE 1A: Measured from the / of the input to / of the output. NOTE 1B: Measured from the differential input crossing point to / of the output. NOTE : Defined as skew within a bank with equal load conditio. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditio. Measured at /. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditio. Using the same type of input on each device, the output is measured at /. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. TABLE 5D. AC CHARACTERISTICS, = 3.3±5%, OX = 1.8±5%, TA = -40 C TO 85 C f MAX tp LH Conditio Frequency 50 MHz Propagation Low to High Delay, t sk(b) ank Skew; NOTE, 6 CLK0; NOTE 1A CLK1, nclk1; NOTE 1B B 5 t sk(o) Skew; NOTE 3, t sk(pp) Part-to-Part Skew; NOTE 4, / tf O utput Rise/Fall Time 0% to 80% t R odc Duty Cycle f 133MHz % t EN utput Enable Time; NOTE 5 tdis utput Disable Time; NOTE 5 All parameters measured at 50MHz using CLK1, nclk1 unless noted otherwise. NOTE 1A: Measured from the / of the input to / of the output. NOTE 1B: Measured from the differential input crossing point to / of the output. NOTE : Defined as skew within a bank with equal load conditio. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditio. Measured at /. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditio. Using the same type of input on each device, the output is measured at /. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. 6

7 TABLE 5E. AC CHARACTERISTICS, =.5±5%, OX = 1.8±5%, TA = -40 C TO 85 C f MAX tp LH Conditio Frequency 50 MHz Propagation Low to High Delay, t sk(b) ank Skew; NOTE, 6 CLK0; NOTE 1A CLK1, nclk1; NOTE 1B B 5 t sk(o) Skew; NOTE 3, t sk(pp) Part-to-Part Skew; NOTE 4, 6 1. / tf O utput Rise/Fall Time 0% to 80% t R odc Duty Cycle f 100MHz % t EN utput Enable Time; NOTE 5 tdis utput Disable Time; NOTE 5 All parameters measured at 50MHz using CLK1, nclk1 unless noted otherwise. NOTE 1A: Measured from the / of the input to / of the output. NOTE 1B: Measured from the differential input crossing point to / of the output. NOTE : Defined as skew within a bank with equal load conditio. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditio. Measured at /. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditio. Using the same type of input on each device, the output is measured at /. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. 7

8 PARAMETER MEASUREMENT INFORMATION 1.65±5% 1.5±5% SCOPE,, OA, OB OA, OB LCMOS Qx LCMOS Qx SCOPE -1.65±5% -1.5±5% 3.3 CORE/3.3 OUTPUT LOAD AC TEST CIRCUIT.5 CORE/.5 OUTPUT LOAD AC TEST CIRCUIT.05±5% 1.5±5%.4±5% +0.9±5% SCOPE SCOPE OA, OB LCMOS Qx OA, OB LCMOS Qx -1.5±5% -0.9±5% 3.3 CORE/.5 OUTPUT LOAD AC TEST CIRCUIT 3.3 CORE/1.8 OUTPUT LOAD AC TEST CIRCUIT 1.6±5% +0.9±5% SCOPE nclk1 OA, OB LCMOS Qx CLK1 PP Cross Points CMR -0.9±5%.5 CORE/1.8 OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEEL 8

9 PART 1 OX OX Qx Qx PART OX OX Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW CLK0 QX0:QX0 OX nclk1 CLK1 QX0:QX0 tsk(b) OX QAx,QBx, QCx, QDx t PD OX BANK SKEW (where X denotes outputs in the same bank) PROPAGATION DELAY 0% Clock s 80% 80% t R t F 0% QAx, QBx, QCx, QDx t PW OX t PERIOD odc = t PW t PERIOD x 100% OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 9

10 APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEELS Figure 1 shows how the differential input can be wired to accept of R1 and R might need to be adjusted to position the _REF in single ended levels. The reference voltage _REF = / is the center of the input voltage swing. For example, if the input generated by the bias resistors R1, R and C1. This bias circuit clock swing is only.5 and = 3.3, _REF should be 1.5 should be located as close as possible to the input pin. The ratio and R/R1 = Single Ended Clock CLK_IN _REF R1 1K CC R1 1K _REF - C1 0.1u R C1 1K R 0.1uF 1K + CLK nclk FIGURE 1. SINGLE ENDED SIGNAL DRIING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK INPUT: LCMOS OUTPUT: For applicatio not requiring the use of a clock input, it can All unused LCMOS output can be left floating. We be left floating. Though not required, but for additional recommend that there is no trace attached. protection, a 1kΩ resistor can be tied from the CLK input to ground. CLK/nCLK INPUT: For applicatio not requiring the use of the differential input, both CLK and nclk can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. PCLK/nPCLK INPUT: For applicatio not requiring the use of a differential input, both the PCLK and npclk pi can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from PCLK to ground. LCMOS CONTROL PINS: All control pi have internal pull-u or pull-dow; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 10

11 DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nclk accepts LDS, LPECL, LHSTL, SSTL, HCSL and other differential signals. Both SWING and OH must meet the PP and CMR input requirements. Figures A to E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please coult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure A, the input termination applies for LHSTL drivers. If you are using an LHSTL driver from another vendor, use their termination recommendation CLK CLK LHSTL ICS HiPerClockS LHSTL Driver R1 50 R 50 nclk HiPerClockS LPECL R1 50 R3 50 R 50 nclk HiPerClockS FIGURE A. CLK/NCLK INPUT DRIEN BY LHSTL DRIER FIGURE B. CLK/NCLK INPUT DRIEN BY 3.3 LPECL DRIER 3.3 LPECL 3.3 R3 15 R4 15 CLK nclk 3.3 HiPerClockS 3.3 LDS_Driv er R CLK nclk Receiver R1 84 R 84 FIGURE C. CLK/NCLK INPUT DRIEN BY 3.3 LPECL DRIER FIGURE D. CLK/NCLK INPUT DRIEN BY 3.3 LDS DRIER LPECL C1 R3 15 R CLK C nclk HiPerClockS R R R1 84 R 84 R5,R6 locate near the driver pin. FIGURE E. CLK/NCLK INPUT DRIEN BY 3.3 LPECL DRIER WITH AC COUPLE 11

12 RELIABILITY INFORMATION TABLE 6. θ JA S. AIR FLOW TABLE FOR 4 LEAD TSSOP θ JA by elocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Boards 70 C/W 63 C/W 60 C/W TRANSISTOR COUNT The traistor count for ICS87008I is: 16 1

13 PACKAGE OUTLINE - G SUFFIX FOR 4 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL N 4 A A A b c D E 6.40 BASIC E e 0.65 BASIC L α 0 8 aaa Reference Document: JEDEC Publication 95, MS

14 TABLE 8. ORDERING INFORMATION Part/Order Number Marking 87008AGI ICS87008AGI 87008AGIT ICS87008AGI 87008AGILF ICS87008AGILF 87008AGILFT ICS87008AGILF NOTE: Parts Package Shipping Packaging 4 Lead TSSOP tray Temperature -40 C to 85 C 4 Lead TSSOP 1000 tape & reel -40 C to 85 C 4 Lead "Lead-Free" TSSOP tray -40 C to 85 C 4 Lead "Lead-Free" TSSOP 1000 tape & reel -40 C to 85 C that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no respoibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licees are implied. This product is intended for use in normal commercial and industrial applicatio. Any other applicatio such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specificatio without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical itruments. 14

15 Rev Table Page REISION HISTORY SHEET Description of Change A T8 14 Ordering Information Table - added "T" (for tape and reel) Part/Order Number. 9/10/04 10 A dded Recommendatio for Unused and Pi. A /1/06 T8 14 Ordering Information Table - added lead-free part number, marking, and note. B T Updated datasheet's header/footer with IDT from ICS. Removed ICS prefix from Part/Order Number column. Added Contact Page. Date 7/31/10 15

We ve Got Your Timing Solution. 604 Silver Creek alley Road San Jose, CA 95138 Sales 800-345-7015 (iide USA) +408-84-800 (outside USA) Fax: 408-84-775 Tech Support netcom@idt.

16 We ve Got Your Timing Solution. 604 Silver Creek alley Road San Jose, CA Sales (iide USA) (outside USA) Fax: Tech Support 010 Integrated Device Technology, Inc. All rights reserved. Product specificatio subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 16

FEATURES 2:1 single-ended multiplexer Q nominal output impedance: 15Ω (V DDO BLOCK DIAGRAM PIN ASSIGNMENT 2:1, SINGLE-ENDED MULTIPLEXER ICS83052I

FEATURES 2:1 single-ended multiplexer Q nominal output impedance: 15Ω (V DDO BLOCK DIAGRAM PIN ASSIGNMENT 2:1, SINGLE-ENDED MULTIPLEXER ICS83052I ICS8305I GENERAL DESCRIPTION The ICS8305I is a low skew, :1, Single-ended ICS Multiplexer and a member of the HiPerClockS family of High Performance Clock Solutions from IDT HiPerClockS The ICS8305I has