GENERAL DESCRIPTION The ICS is a high performance Differential-to-LVDS FEATURES BLOCK DIAGRAM PIN ASSIGNMENT ICS

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1 ICS GENERAL DESCRIPTION The ICS is a high performance Differential-to-LDS Jitter Attenuator designed for ICS HiPerClockS use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS has a bandwidth of 400kHz. The 400kHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. The ICS uses IDT s 3 rd Generation FemtoClock TM PLL technology to achive the lowest possible phase noise. The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. FEATURES Three Differential LDS output pairs One Differential clock input and supports the following input types: LPECL, LDS, LHSTL, SSTL, HCSL Output frequency range: 98MHz - 320MHz frequency range: 98MHz - 128MHz CO range: 490MHz - 640MHz Cycle-to-cycle jitter: 35ps (maximum) Supports PCI-Express Spread-Spectrum Clocking The 400kHz bandwidth mode allows the system designer to make jitter attenuation/tracking skew design trade-offs operating supply 0 C to 70 C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM OEA Pullup Pulldown F_SEL2:0 Pulldown Pullup 3 Phase Detector CO MHz F_SEL[2:0] FUNCTION TABLE s F_SEL2 F_SEL1 _SEL (default) 3 QA0 nqa0 QA1 nqa1 Outputs QA0/nQA0, QA0/nQA QB0/nQB0 F PIN ASSIGNMENT QA1 DDO QA0 nqa0 MR F_SEL0 nc DDA F_SEL1 DD nqa1 DDO QB0 nqb0 F_SEL2 OEB GND OEA MR Pulldown Pullup OEB M = 5 (fixed) (default) QB0 nqb0 ICS Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top iew IDT / ICS 1 ICS874003AG-02 RE A AUGUST 29, 2006

2 TABLE 1. PIN DESCRIPTIONS Number, 20, 19, 4 Name QA1, nqa O 3 QA0, nqa0 5 MR 6, 9, 16 F_SEL0, F_SEL1, F_SEL2 Type utput ower utput Description Differential output pair. LDS interface levels Output supply pins Differential output pair. LDS interface levels Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (nqx) to go low and the inverted outputs (Qx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LCMOS/LTTL interface levels. O. P. O. Pulldown Pulldown Frequency select pin for QAx/nQAx and QBx0/nQB0 outputs. LCMOS/LTTL interface levels. 7 nc U nused No connect. 8 A P ower Analog supply pin. 10 P ower Core supply pin. Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are 11 OEA Pullup active. When LOW, the QAx/nQAx outputs are in a high impedance state. LCMOS/LTTL interface levels. 12 P ulldown Non-inverting differential clock input. 13 P ullup Inverting differential clock input. 14 GND P ower Power supply ground. 15 OEB Pullup Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are active. When LOW, the QBx/nQBx outputs are in a high impedance state. LCMOS/LTTL interface levels. 17, 18 nqb0, QB0 O utput Differential output pair. LDS interface levels. NOTE: Pullup and P ulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol C IN R R P ULLUP P ULLDOWN Parameter nput Capacitance nput Pullup Resistor nput Pulldown Resistor Test Conditions Minimum Typical Maximum Units p I 4 F I 51 kω I 51 kω TABLE 3. OUTPUT ENABLE FUNCTION TABLE OEA s Outputs QA0/nQA0, QA1/nQA QB0/nQB0 OEB HiZ 1 1 Enabled HiZ Enabled IDT / ICS 2 ICS874003AG-02 RE A AUGUST 29, 2006

3 ABSOLUTE MAXIMUM RATINGS Supply oltage, 4.6 s, I -0.5 to Outputs, O -0.5 to O Package Thermal Impedance, θ JA 73.2 C/W (0 lfpm) Storage Temperature, T STG -65 C to 1 C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, = A = O = ±5%, TA = 0 C TO 70 C Symbol D D I DD I I D DA DO DA D DO Parameter Test Conditions Minimum Typical Maximum Units Core Supply oltage Analog Supply oltage Output Supply oltage Power Supply Current 75 ma Analog Supply Current 12 ma Output Supply Current 75 ma TABLE 4B. LCMOS/LTTL DC CHARACTERISTICS, = A = O = ±5%, TA = 0 C TO 70 C Symbol IH IL I IH I IL Parameter nput High oltage nput Low oltage Test Conditions Minimum Typical Maximum D I 2 D + I OEA, OEB = IN = µ A High Current F_SEL0, F_SEL1 F_SEL2, MR DD = IN = µ A Low Current OEA, OEB = 3.465, = 0 IN -1 µ A F_SEL0, F_SEL1 F_SEL2, MR DD = 3.465, = 0 IN -5 µ A Units TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, = A = O = ±5%, TA = 0 C TO 70 C Symbol I IH I IL PP Parameter High Current Low Current oltage oltage; NOTE 1, is defined as. I H the Test Conditions = IN = IN = IN = IN Minimum Typical Maximum 5 = = = = Units µ 1 A 1 µ A Peak-to-Peak CMR Common Mode 2 GND NOTE 1: Common mode voltage NOTE 2: For single ended applications, maximum input voltage for, and FB_IN, nfb_in is D D IDT / ICS 3 ICS874003AG-02 RE A AUGUST 29, 2006

4 TABLE 4D. LDS DC CHARACTERISTICS, = A = O = ±5%, TA = 0 C TO 70 C Symbol OD OD OS OS Parameter ifferential Output Test Conditions Minimum 7 Typical 7 Maximum 8 Units m m D oltage OD Magnitude Change Offset oltage Magnitude Change m OS TABLE 5. AC CHARACTERISTICS, = A = O = ±5%, TA = 0 C TO 70 C Symbol Parameter Test Conditions Minimum Typical Maximum Units fmax Output Frequency MHz t jit(cc) Cycle-to-Cycle Jitter, NOTE 1 35 ps t sk(o) Output Skew; NOTE 2, ps t sk(b) Bank Skew; NOTE 1, 4 Bank A 55 ps t R / tf O utput Rise/Fall Time 20% to 80% ps odc Output Duty Cycle % NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at /2. D DO NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. IDT / ICS 4 ICS874003AG-02 RE A AUGUST 29, 2006

5 PARAMETER MEASUREMENT INFORMATION ±5% POWER SUPPLY + Float GND, O A LDS Qx nqx SCOPE PP Cross Points CMR GND LDS OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEEL nqa0, nqa1, nqb0 nqx QA0, QA1, QB0 Qx tcycle n tcycle n+1 nqy tjit(cc) = tcycle n tcycle n Cycles Qy tsk(o) CYCLE-TO-CYCLE JITTER OUTPUT SKEW nqxx QXx nqa0, nqa1, nqb0 nqxy QXy tsk(b) QA0, QA1, QB0 t PW t PERIOD Where X = A or B t PW odc = x 100% t PERIOD BANK SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT / ICS 5 ICS874003AG-02 RE A AUGUST 29, 2006

6 80% 80% out Clock Outputs 20% t R t F 20% SWING DC LDS out OS / OS OUTPUT RISE/FALL TIME OFFSET OLTAGE SETUP out DC LDS 100 OD / OD out DIFFERENTIAL OUTPUT OLTAGE SETUP IDT / ICS 6 ICS874003AG-02 RE A AUGUST 29, 2006

7 APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL., A, and O should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a.01µf bypass capacitor should be connected to each CCA pin..01µf 10Ω A.01µF 10µF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage _REF = DD /2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the _REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5 and DD =, _REF should be 1.25 and R2/R1 = DD Single Ended Clock R1 1K _REF C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIING DIFFERENTIAL INPUT IDT / ICS 7 ICS874003AG-02 RE A AUGUST 29, 2006

8 DIFFERENTIAL CLOCK INPUT INTERFACE The / accepts LDS, LPECL, LHSTL, SSTL, HCSL and other differential signals. Both SWING and OH must meet the PP and CMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS / input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LHSTL drivers. If you are using an LHSTL driver from another vendor, use their termination recommendation. 1.8 LHSTL ICS HiPerClockS LHSTL Driver R1 R2 HiPerClockS LPECL R1 R3 R2 HiPerClockS FIGURE 3A. HIPERCLOCKS /N INPUT DRIEN BY ICS HIPERCLOCKS LHSTL DRIER FIGURE 3B. HIPERCLOCKS /N INPUT DRIEN BY LPECL DRIER LPECL R3 125 R4 125 HiPerClockS LDS_Driv er R1 100 Receiver R1 84 R2 84 FIGURE 3C. HIPERCLOCKS /N INPUT DRIEN BY LPECL DRIER FIGURE 3D. HIPERCLOCKS /N INPUT DRIEN BY LDS DRIER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: LCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. OUTPUTS: LDS All unused LDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. IDT / ICS 8 ICS874003AG-02 RE A AUGUST 29, 2006

9 LDS DRIER TERMINATION A general LDS inteface is shown in Figure 4. In a 100Ω differential transmission line environment, LDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. LDS_Driv er + R Ohm Differiential Transmission Line FIGURE 4. TYPICAL LDS DRIER TERMINATION IDT / ICS 9 ICS874003AG-02 RE A AUGUST 29, 2006

10 POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for DD = + 5% = 3.465, which gives worst case results. Power (core) MAX = DD_MAX * (I DD_MAX + I DDA_MAX ) = * (75mA + 12mA) = mW Power (outputs) MAX = DDO_MAX * I DDO_MAX = * 75mA = mW Total Power _MAX = mW mW = mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125 C. The equation for Tj is as follows: Tj = θ JA * Pd_total + T A Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6 C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70 C with all outputs switching is: 70 C W * 66.6 C/W = C. This is below the limit of 125 C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θ JA FOR 20-LEAD TSSOP, FORCED CONECTION θ JA by elocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards C/W 98.0 C/W 88.0 C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2 C/W 66.6 C/W 63.5 C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. IDT / ICS 10 ICS874003AG-02 RE A AUGUST 29, 2006

11 RELIABILITY INFORMATION TABLE 6. θ JA S. AIR FLOW TABLE FOR 20 LEAD TSSOP θ JA by elocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards C/W 98.0 C/W 88.0 C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2 C/W 66.6 C/W 63.5 C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS is: 1408 IDT / ICS 11 ICS874003AG-02 RE A AUGUST 29, 2006

12 PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N 20 MAX A A A b c D E 6.40 BASIC E e 0.65 BASIC L α 0 8 aaa Reference Document: JEDEC Publication 95, MO-153 IDT / ICS 12 ICS874003AG-02 RE A AUGUST 29, 2006

13 TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS874003AG A02 20 Lead TSSOP tube 0 C to 70 C ICS874003AG-02T A02 20 Lead TSSOP 20 tape & reel 0 C to 70 C ICS874003AG-02LF 74003A02L 20 Lead "Lead-Free" TSSOP tube 0 C to 70 C ICS874003AG-02LFT 74003A02L 20 Lead "Lead-Free" TSSOP 20 tape & reel 0 C to 70 C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS complaint. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT / ICS 13 ICS874003AG-02 RE A AUGUST 29, 2006

14 Innovate with IDT and accelerate your future networks. Contact: For Sales Fax: For Tech Support Corporate Headquarters Integrated Device Technology, Inc Silver Creek alley Road San Jose, CA United States (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No G 435 Orchard Road #20-03 Wisma Atria Singapore Europe IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) Fax: +44 (0) Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA