ICS83056I-01. General Description. Features. Block Diagram. Pin Assignment 6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER ICS83056I-01
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1 ICS83056I-01 General Description The ICS83056I-01 is a 6-bit, :1, Single-ended ICS LVCMOS Multiplexer and a member of the HiPerClockS HiPerClockS family of High Performance Clock Solutions from IDT. The ICS83056I-01 has two selectable single-ended LVCMOS clock inputs and six single-ended LVCMOS clock outputs. The outputs have a which may be set at 3.3V,.5V, or 1.8V, making the device ideal for use in voltage translation applications. An output enable pin places the output in a high impedance state which may be useful for testing or debug. Possible applications include systems with up to 6 transceivers which need to be independently set for different rates. For example, a board may have six transceivers, each of which need to be independently configured for 1 Gigabit Ethernet or 1 Gigabit Fibre Channel rates. Another possible application may require the ports to be independently set for FEC (Forward Error Correction) or non-fec rates. The device operates up to 50MHz and is packaged in a 0 TSSOP. CLK0 Pulldown 0 Block Diagram Q0 Features 6-Bit, :1 single-ended LVCMOS multiplexer Maximum output frequency: 50MHz Additive phase jitter, RMS at 155.5MHz (1kHz - 0MHz): 0.18ps (typical) Operating supply modes: Core/Output / 3.3V/3.3V 3.3V/.5V 3.3V/1.8V.5V/.5V.5V/1.8V -40 C to 85 C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages CLK1 Pulldown 1 SEL0 Pulldown 0 Q1 Pin Assignment SEL1 SEL SEL3 Pulldown Pulldown Pulldown Q Q3 Q4 SEL5 Q5 GND Q4 SEL4 CLK1 Q3 SEL SEL0 Q0 VDDO GND Q1 SEL1 CLK0 OE ICS83056I-01 Q SEL 0-Lead TSSOP 6.50mm x 4.40mm x 0.95mm package body G Package Top View 1 SEL4 Pulldown 0 Q5 1 SEL5 Pulldown OE Pullup IDT / ICS :1, SINGLE-ENDED LVCMOS MULTIPLEXER 1 ICS83056AGI-01 REV. A JANUARY 9, 009
2 Table 1. Pin Descriptions Number Name Type Description 1, 6 10, 11 15, 0, 5, 9 1, 16, 19 SEL5, SEL4, SEL3, SEL, SEL1, SEL0 Q5, Q4, Q3, Q, Q1, Q0 Input Pulldown Clock select inputs. See Table 3. LVCMOS / LVTTL interface levels. Output Single-ended clock output. LVCMOS/LVTTL interface levels. 3, 18 Power Output supply pins. 4, 17 GND Power Power supply ground. 7, 14 CLK1, CLK0 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. 8 Power Power supply pin. 13 OE Input Pullup Output enable. When LOW, outputs are in a High impedance state. When HIGH, outputs are active. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table, Pin Characteristics, for typical values. Table. Pin Characteristics C IN Input Capacitance 4 pf = = 3.465V 18 pf C PD Power Dissipation Capacitance (per output) = =.65V 19 pf = = V 19 pf R PULLUP Input Pullup Resistor 51 kω R PULLDOWN Input Pulldown Resistor 51 kω = 3.465V 15 Ω R OUT Output Impedance =.65V 17 Ω = V 5 Ω Function Tables Table 3. Control Input Function Table Control Inputs Outputs SELx 0 CLK0 1 CLK1 IDT / ICS :1, SINGLE-ENDED LVCMOS MULTIPLEXER ICS83056AGI-01 REV. A JANUARY 9, 009
3 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, 4.6V Inputs, V I -0.5V to + 0.5V Outputs, V O -0.5V to + 0.5V Package Thermal Impedance, θ JA 91.1 C/W (0 mps) Storage Temperature, T STG -65 C to 150 C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, = 3.3V±5%, = 3.3V ± 5% or.5v±5%, or 1.8V±0.V, T A = -40 C to 85 C Positive Supply Voltage V V Output Supply Voltage V V I DD Power Supply Current 45 ma I DDO Output Supply Current No Load 5 ma Table 4B. Power Supply DC Characteristics, =.5V±5%, =.5V±5% or 1.8V±0.V, T A = -40 C to 85 C Positive Supply Voltage V Output Supply Voltage V V I DD Power Supply Current 40 ma I DDO Output Supply Current No Load 5 ma IDT / ICS :1, SINGLE-ENDED LVCMOS MULTIPLEXER 3 ICS83056AGI-01 REV. A JANUARY 9, 009
4 Table 4C. LVCMOS/LVTTL DC Characteristics, T A = -40 C to 85 C V IH V IL I IH I IL V OH V OL Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage; Output Low Voltage CLK0, CLK1, SEL[0:5] = 3.465V V =.65V V = 3.465V V =.65V V = V IN = 3.465V or.65v 150 µa OE = V IN = 3.465V or.65v 5 µa CLK0, CLK1, SEL[0:5] = 3.465V or.65v, V IN = 0V -5 µa OE = 3.465V or.65v, V IN = 0V -150 µa = 3.3V ± 5%, I OH = -4mA.6 V =.5V ± 5%, I OH = -1mA 1.8 V = 1.8V ± 0.V, I OH = -4mA V = 3.3V ± 5%, I OL = 4mA 0.5 V =.5V ± 5%, I OL = 1mA 0.45 V = 1.8V ± 0.V, I OL = 4mA 0.35 V IDT / ICS :1, SINGLE-ENDED LVCMOS MULTIPLEXER 4 ICS83056AGI-01 REV. A JANUARY 9, 009
5 AC Electrical Characteristics Table 5A. AC Characteristics, = = 3.3V ± 5%, T A = -40 C to 85 C f MAX Output Frequency 50 MHz tp LH Propagation Delay, Low-to-High; ns tp HL Propagation Delay, High-to-Low; ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 155.5MHz, Integration Range: 1kHz 0MHz 0.18 ps tsk(i) Input Skew; NOTE ps tsk(o) Output Skew: NOTE ps tsk(pp) Part-to-Part Skew; NOTE 3, ps t R / t F Output Rise/Fall Time 0% to 80% ps odc Output Duty Cycle f OUT 175MHz % MUX ISOLATION MUX Isolation 100MHz 45 db NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. : Measured from / of the input to / of the output. NOTE : Driving only one input clock. NOTE 3: This parameter is defined according with JEDEC Standard 65. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at /. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. Table 5B. AC Characteristics, = 3.3V ± 5%, =.5V ± 5%, T A = -40 C to 85 C f MAX Output Frequency 50 MHz tp LH Propagation Delay, Low-to-High; ns tp HL Propagation Delay, High-to-Low; ns tjit See notes in Table 5A above. Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 155.5MHz, Integration Range: 1kHz 0MHz 0.14 ps tsk(i) Input Skew; NOTE ps tsk(o) Output Skew: NOTE ps tsk(pp) Part-to-Part Skew; NOTE 3, ps t R / t F Output Rise/Fall Time 0% to 80% ps odc Output Duty Cycle % MUX ISOLATION MUX Isolation 100MHz 45 db IDT / ICS :1, SINGLE-ENDED LVCMOS MULTIPLEXER 5 ICS83056AGI-01 REV. A JANUARY 9, 009
6 Table 5C. AC Characteristics, = 3.3V ± 5%, = 1.8V ± 0.V, T A = -40 C to 85 C f MAX Output Frequency 50 MHz tp LH Propagation Delay, Low-to-High; ns tp HL Propagation Delay, High-to-Low; ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 155.5MHz, Integration Range: 1kHz 0MHz 0.16 ps tsk(i) Input Skew; NOTE ps tsk(o) Output Skew: NOTE ps tsk(pp) Part-to-Part Skew; NOTE 3, ps t R / t F Output Rise/Fall Time 0% to 80% ps odc Output Duty Cycle % MUX ISOLATION MUX Isolation 100MHz 45 db NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. : Measured from / of the input to / of the output. NOTE : Driving only one input clock. NOTE 3: This parameter is defined according with JEDEC Standard 65. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at /. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. Table 5D. AC Characteristics, = =.5V ± 5%, T A = -40 C to 85 C f MAX Output Frequency 50 MHz tp LH Propagation Delay, Low-to-High; ns tp HL Propagation Delay, High-to-Low; ns tjit See notes in Table 5C above. Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 155.5MHz, Integration Range: 1kHz 0MHz 0. ps tsk(i) Input Skew; NOTE ps tsk(o) Output Skew: NOTE 4 15 ps tsk(pp) Part-to-Part Skew; NOTE 3, ps t R / t F Output Rise/Fall Time 0% to 80% ps odc Output Duty Cycle f OUT 175MHz % MUX ISOLATION MUX Isolation 100MHz 45 db IDT / ICS :1, SINGLE-ENDED LVCMOS MULTIPLEXER 6 ICS83056AGI-01 REV. A JANUARY 9, 009
7 Table 5E. AC Characteristics, =.5V ± 5%, = 1.8V ± 0.V, T A = -40 C to 85 C f MAX Output Frequency 50 MHz tp LH Propagation Delay, Low-to-High; ns tp HL Propagation Delay, High-to-Low; ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 155.5MHz, Integration Range: 1kHz 0MHz 0.19 ps tsk(i) Input Skew; NOTE ps tsk(o) Output Skew: NOTE 4 15 ps tsk(pp) Part-to-Part Skew; NOTE 3, ps t R / t F Output Rise/Fall Time 0% to 80% ps odc Output Duty Cycle f OUT 00MHz % MUX ISOLATION MUX Isolation 100MHz 45 db NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. : Measured from / of the input to / of the output. NOTE : Driving only one input clock. NOTE 3: This parameter is defined according with JEDEC Standard 65. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at /. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. IDT / ICS :1, SINGLE-ENDED LVCMOS MULTIPLEXER 7 ICS83056AGI-01 REV. A JANUARY 9, 009
8 Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dbm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase 155.5MHz 1kHz to 0MHz = 0.18ps (typical) SSB Phase Noise dbc/hz Offset Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. IDT / ICS :1, SINGLE-ENDED LVCMOS MULTIPLEXER 8 ICS83056AGI-01 REV. A JANUARY 9, 009
9 Parameter Measurement Information 1.65V±5%.05V±5% 1.5V±5%, SCOPE SCOPE LVCMOS GND LVCMOS GND -1.65V±5% -1.5V±5% 3.3V Output Load AC Test Circuit 3.3V Core/.5V Output Load AC Test Circuit.4V±0.065V 0.9V±0.1V 1.5V±5% SCOPE, SCOPE LVCMOS GND LVCMOS GND -0.9V±0.1V -1.5V±5% 3.3V Core/1.8V Output Load AC Test Circuit.5V Core/.5V Output Load AC Test Circuit 1.6V±0.05V 0.9V±0.1V SCOPE LVCMOS GND Qy tsk(o) -0.9V±0.1V.5V Core/1.8V Output Load AC Test Circuit Output Skew IDT / ICS :1, SINGLE-ENDED LVCMOS MULTIPLEXER 9 ICS83056AGI-01 REV. A JANUARY 9, 009
10 Parameter Measurement Information, continued Part 1 Q[0:5] t PW t PERIOD Part Qy tsk(pp) odc = t PW t PERIOD x 100% Part-to-Part Skew Output Duty Cycle/Pulse Width/Period CLK0, CLK1 80% 80% Q[0:5] Q[0:5] 0% t R t F 0% t PD Propagation Delay Output Rise/Fall Time CLK0 CLK1 Q[0:5] t PD1 t PD tsk (i) tsk(i) = t PD t PD1 Input Skew IDT / ICS :1, SINGLE-ENDED LVCMOS MULTIPLEXER 10 ICS83056AGI-01 REV. A JANUARY 9, 009
11 Parameter Measurement Information, continued Spectrum of Output Signal Q A0 MUX selects active input clock signal Amplitude (db) A1 MUX _ISOL = A0 A1 L or H SEL MUX selects static input Q ƒ (fundamental) Frequency MUX Isolation Application Information Recommendations for Unused Input and Output Pins Inputs: CLK Inputs For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. Outputs: LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT / ICS :1, SINGLE-ENDED LVCMOS MULTIPLEXER 11 ICS83056AGI-01 REV. A JANUARY 9, 009
12 Reliability Information Table 6. θ JA vs. Air Flow Table for a 0 Lead TSSOP θ JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 91.1 C/W 86.7 C/W 84.6 C/W Transistor Count The transistor count for ICS83056I-01 is: 967 Package Outline and Package Dimensions Package Outline - G Suffix for 0 Lead TSSOP Table 7. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 0 A 1.0 A A b c D E 6.40 Basic E e 0.65 Basic L α 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT / ICS :1, SINGLE-ENDED LVCMOS MULTIPLEXER 1 ICS83056AGI-01 REV. A JANUARY 9, 009
13 Ordering Information Table 9. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 83056AGI-01 ICS83056AI01 0 Lead TSSOP Tube -40 C to 85 C 83056AGI-01T ICS83056AI01 0 Lead TSSOP 500 Tape & Reel -40 C to 85 C 83056AGI-01LF ICS3056AI01L Lead-Free 0 Lead TSSOP Tube -40 C to 85 C 83056AGI-01LFT ICS3056AI01L Lead-Free 0 Lead TSSOP 500 Tape & Reel -40 C to 85 C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT / ICS :1, SINGLE-ENDED LVCMOS MULTIPLEXER 13 ICS83056AGI-01 REV. A JANUARY 9, 009
14 Contact Information: Sales (inside USA) (outside USA) Fax: Technical Support Corporate Headquarters Integrated Device Technology, Inc. 604 Silver Creek Valley Road San Jose, CA United States (inside USA) (outside USA) Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA
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FEMTOCLOCK CRYSTAL-TO- 33V, 25V LVPECL CLOCK GENERATOR GENERAL DESCRIPTION The ICS843001CI is a Fibre Channel Clock ICS Generator and a member of the HiPerClocks TM HiPerClockS family of high performance
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GENERAL DESCRIPTION The is a 4 output LVPECL ICS Synthesizer optimized to generate clock HiPerClockS frequencies for a variety of high performance applications and is a member of the HiPerClocks TM family
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DATASHEET 2 TO 4 DIFFERENTIAL CLOCK MUX ICS557-06 Description The ICS557-06 is a two to four differential clock mux designed for use in PCI-Express applications. The device selects one of the two differential
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DATASHEET Description The generates four high-quality, high-frequency clock outputs. It is designed to replace multiple crystals and crystal oscillators in networking applications. Using ICS patented Phase-Locked
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DATASHEET ICS553 Description The ICS553 is a low skew, single input to four output, clock buffer. Part of IDT s ClockBlocks TM family, this is our lowest skew, small clock buffer. See the ICS552-02 for
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DATASHEET Description The is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates IDT s proprietary analog/digital Phase Locked Loop (PLL) techniques. IDT introduced
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DATASHEET Description The is a low-cost, low phase noise, high performance clock synthesizer for applications which require low phase noise and low jitter. It is IDT s lowest phase noise multiplier. Using
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DATASHEET ICS180-51 Description The ICS180-51 generates a low EMI output clock from a clock or crystal input. The device uses IDT s proprietary mix of analog and digital Phase-Locked Loop (PLL) technology
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DATASHEET ICS180-01 Description The ICS180-01 generates a low EMI output clock from a clock or crystal input. The device uses IDT s proprietary mix of analog and digital Phase Locked Loop (PLL) technology
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DATASHEET ICS10-52 Description The ICS10-52 generates a low EMI output clock from a clock or crystal input. The device uses ICS proprietary mix of analog and digital Phase-Locked Loop (PLL) technology
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PRELIMINARY DATASHEET ICS1493-17 Description The ICS1493-17 is a low-power, low-jitter clock synthesizer designed to replace multiple crystals and oscillators in portable audio/video systems. The device
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PRELIMINARY DATASHEET ICS348-22 Description The ICS348-22 synthesizer generates up to 9 high-quality, high-frequency clock outputs including multiple reference clocks from a low frequency crystal or clock
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DATASHEET ICS651 Description The ICS651 is a low skew, single input to four output, clock buffer. Part of IDT s ClockBlocks TM family, this is a low skew, small clock buffer. IDT makes many non-pll and
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DATASHEET ICS501 Description The ICS501 LOCO TM is the most cost effective way to generate a high-quality, high-frequency clock output from a lower frequency crystal or clock input. The name LOCO stands
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DATASHEET ICS557-0 Description The ICS557-0 is a clock chip designed for use in PCI-Express Cards as a clock source. It provides a pair of differential outputs at 00 MHz in a small 8-pin SOIC package.
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DATASHEET ICS501 Description The ICS501 LOCO TM is the most cost effective way to generate a high-quality, high-frequency clock output from a lower frequency crystal or clock input. The name LOCO stands
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DATASHEET ICS502 Description The ICS502 LOCO TM is the most cost effective way to generate a high-quality, high-frequency clock output and a reference from a lower frequency crystal or clock input. The
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DATASHEET ICS511 Description The ICS511 LOCO TM is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands
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DATASHEET Description The is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a.5 MHz or 5.00
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DTSHEET MK74CB218 Description The MK74CB218 Buffalo is a monolithic CMOS high speed clock driver. It consists of two identical single input to eight low-skew output, non-inverting clock drivers. This eliminates
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DATASHEET ICS512 Description The ICS512 is the most cost effective way to generate a high-quality, high frequency clock output and a reference clock from a lower frequency crystal or clock input. The name
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DATASHEET IDT9170B Description The IDT9170B generates an output clock which is synchronized to a given continuous input clock with zero delay (±1ns at 5 V VDD). Using IDT s proprietary phase-locked loop
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DATASHEET ICS7151A-50 Description The ICS7151A-50 is a clock generator for EMI (Electromagnetic Interference) reduction. Spectral peaks are attenuated by modulating the system clock frequency. Down or
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DATASHEET MK2705 Description The MK2705 provides synchronous clock generation for audio sampling clock rates derived from an MPEG stream, or can be used as a standalone clock source with a 27 MHz crystal.
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DATASHEET ICS309 Description The ICS309 is a versatile serially-programmable, triple PLL with spread spectrum clock source. The ICS309 can generate any frequency from 250kHz to 200 MHz, and up to 6 different
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FemtoClock Crystal-to-3.3 LPECL Frequency Synthesizer 8430252I-45 DATASHEET GENERAL DESCRIPTION The 8430252I-45 is a 2 output LPECL and LCMOS/LTTL Synthesizer optimized to generate Ethernet reference clock
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DATASHEET ICS3726-02 Description The ICS3726-02 is a low cost, low-jitter, high-performance designed to replace expensive discrete s modules. The ICS3726-02 offers a wid operating frequency range and high
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DATASHEET MK3722 Description The MK3722 is a low cost, low jitter, high performance VCXO and PLL clock synthesizer designed to replace expensive discrete VCXOs and multipliers. The patented on-chip Voltage
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DATASHEET ICS280 Description The ICS280 field programmable spread spectrum clock synthesizer generates up to four high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency
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DATASHEET MK2703 Description The MK2703 is a low-cost, low-jitter, high-performance PLL clock synthesizer designed to replace oscillators and PLL circuits in set-top box and multimedia systems. Using IDT
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DATASHEET MK1714-01 Description The MK1714-01 is a low cost, high performance clock synthesizer with selectable multipliers and percentages of spread spectrum designed to generate high frequency clocks
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DATASHEET MK1714-02 Description The MK1714-02 is a low cost, high performance clock synthesizer with selectable multipliers and percentages of spread designed to generate high frequency clocks with low
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DATASHEET LOW PHASE NOISE T1/E1 CLOCK ENERATOR MK1581-01 Description The MK1581-01 provides synchronization and timing control for T1 and E1 based network access or multitrunk telecommunication systems.
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DATASHEET ICS601-01 Description The ICS601-01 is a low-cost, low phase noise, high-performance clock synthesizer for applications which require low phase noise and low jitter. It is IDT s lowest phase
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DATASHEET MK5811C Description The MK5811C device generates a low EMI output clock from a clock or crystal input. The device is designed to dither a high emissions clock to lower EMI in consumer applications.
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DATASHEET ICS650-11 Description The ICS650-11 is a low cost, low jitter, high performance clock synthesizer customized for BroadCom. Using analog Phase-Locked Loop (PLL) techniques, the device accepts
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DATASHEET ICS7152A Description The ICS7152A-02 and -11 are clock generators for EMI (Electromagnetic Interference) reduction (see below for frequency ranges and multiplier ratios). Spectral peaks are attenuated
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ICS874003-02 GENERAL DESCRIPTION The ICS874003-02 is a high performance Differential-to-LDS Jitter Attenuator designed for ICS HiPerClockS use in PCI Express systems. In some PCI Express systems, such
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Low Skew, 1-to-4, Differential/LCMOS-to- 0.7 HCSL Fanout Buffer 85104I Data Sheet GENERAL DESCRIPTION The 85104I is a low skew, high performance 1-to-4 Differential/ LCMOS-to-0.7 HCSL Fanout Buffer. The
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DATASHEET ICS252 Description The ICS252 is a low cost, dual-output, field programmable clock synthesizer. The ICS252 can generate two output frequencies from 314 khz to 200 MHz using up to two independently
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