GENERAL DESCRIPTION FEATURES BLOCK DIAGRAM PIN ASSIGNMENT. 6:1, Single-Ended Multiplexer Data Sheet

Transcription

1 6:1, Single-Ended Multiplexer Data Sheet GENEAL DESCPTON The is a low skew, 6:1, Single-ended Multiplexer from DT. The has six selectable singleended clock inputs and one single-ended clock ouut. The ouut has a pin which may be set at 3.3, 2.5, or 1.8, making the device ideal for use in voltage translation applications. An ouut enable pin places the ouut in a high impedance state which may be useful for testing or debug purposes. The device operates up to 250MHz and is packaged in a 16 TSSOP package. FEATUES 6:1 single-ended multiplexer Q nominal ouut impedance: 7Ω ( = 3.3) Maximum ouut frequency: 250MHz Propagation delay: 3ns (maximum), = = 3.3 nput skew: 225ps (maximum), = = 3.3 Part-to-part skew: 475ps (maximum), = = 3.3 Additive phase jitter, MS: 0.19ps (typical), 3.3/3.3 Operating supply modes: / 3.3/ / / / / C to 85 C ambient operating temperature Available in lead-free (ohs 6) package BLOCK DAGAM PN ASSGNMENT CLK0 CLK1 CLK2 CLK3 Q CLK4 CLK5 SEL2 SEL1 SEL Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top iew OE 2016 ntegrated Device Technology, nc 1

2 = = = = = = Data Sheet TABLE 1. PN DESCPTONS Number Name Type Description 1 Q Ouut Single-ended clock ouut. LCMOS/LTTL interface levels. 2, 4 nc Unused No connect. 6, 8, 9, 11, 13, 15 CLK5, CLK4, CLK3, CLK2, CLK1, CLK0 nput Pulldown Single-ended clock inputs. LCMOS/LTTL interface levels. 3 OE nput Pullup Ouut enable. When LOW, ouuts are in HGH impedance state. When HGH, ouuts are active. LCMOS / LTTL interface levels. 5 GND Power Power supply ground. 7, 10, 14 SEL2, SEL1, SEL0 nput Pulldown Clock select input. See Control nput Function Table. LCMOS / LTTL interface levels. 12 Power Core and input supply pin. 16 Power Ouut supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PN CHAACTESTCS C N nput Capacitance 4 pf PULLUP nput Pullup esistor 51 kω PULLDOWN nput Pulldown esistor 51 kω C PD OUT Power Dissipation Capacitance (per ouut) Ouut mpedance pf pf pf Ω Ω Ω TABLE 3. CONTOL NPUT FUNCTON TABLE Control nputs SEL2 SEL1 SEL0 nput Selected to Q CLK CLK CLK CLK CLK CLK LOW LOW 2016 ntegrated Device Technology, nc 2

3 ABSOLUTE MAXMUM ATNGS Supply oltage, 4.6 nputs, -0.5 to Ouuts, O -0.5 to Package Thermal mpedance, θ JA 89 C/W (0 lfpm) Storage Temperature, T STG -65 C to 150 C NOTE: Stresses beyond those listed under Absolute Maximum atings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWE SUPPLY DC CHAACTESTCS, = = 3.3±5%, TA = -40 C TO 85 C Power Supply oltage Ouut Supply oltage Power Supply Current 40 ma Ouut Supply Current 5 ma TABLE 4B. POWE SUPPLY DC CHAACTESTCS, = 3.3±5%, = 2.5±5%, TA = -40 C TO 85 C Power Supply oltage Ouut Supply oltage Power Supply Current 40 ma Ouut Supply Current 5 ma TABLE 4C. POWE SUPPLY DC CHAACTESTCS, = 3.3±5%, = 1.8±0.2, TA = -40 C TO 85 C Power Supply oltage Ouut Supply oltage Power Supply Current 40 ma Ouut Supply Current 5 ma TABLE 4D. POWE SUPPLY DC CHAACTESTCS, = = 2.5±5%, TA = -40 C TO 85 C Power Supply oltage Ouut Supply oltage Power Supply Current 35 ma Ouut Supply Current 5 ma TABLE 4E. POWE SUPPLY DC CHAACTESTCS, = 2.5±5%, = 1.8±0.2, TA = -40 C TO 85 C Power Supply oltage Ouut Supply oltage Power Supply Current 35 ma Ouut Supply Current 5 ma 2016 ntegrated Device Technology, nc 3

4 TABLE 4F. LCMOS/LTTL DC CHAACTESTCS, TA = -40 C TO 85 C H L H L OH nput High oltage nput Low oltage nput High Current nput Low Current Ouut Higholtage = 3.3 ± 5% = 2.5 ± 5% = 3.3 ± 5% = 2.5 ± 5% CLK0:CLK5, SEL0:SEL2 = 3.3 or 2.5 ± 5% 150 µa OE = 3.3 or 2.5 ± 5% 5 µa CLK0:CLK5, SEL0:SEL2 = 3.3 or 2.5 ± 5% -5 µa OE = 3.3 or 2.5 ± 5% -150 µa = 3.3 ± 5%; NOTE = 2.5 ± 5%; NOTE = 1.8 ± 5%; NOTE = 3.3 ± 5%; NOTE OL Ouut Low oltage = 2.5 ± 5%; NOTE = 1.8 ± 5%; NOTE NOTE 1: Ouuts terminated with 50W to /2. See Parameter Measurement section, Load Test Circuit diagrams. TABLE 5A. AC CHAACTESTCS, = = 3.3 ± 5%, TA = -40 C TO 85 C f MAX Ouut Frequency 250 MHz LH Propagation Delay, Low to High; NOTE ns HL Propagation Delay, High to Low; NOTE ns tsk(i) nput Skew; NOTE ps tjit Buffer Additive Phase Jitter, MS; refer to Additive Phase Jitter Section; NOTE MHz, (12kHz to 20MHz) 0.19 ps tsk(pp) Part-to-Part Skew; NOTE 2, ps t / t F Ouut ise/fall Time 20% to 80% ps odc Ouut Duty Cycle % MUX SOL MUX 100MHz 45 db NOTE 1: Measured from /2 of the input to /2 of the ouut. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defi ned as skew between ouuts on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the ouut is measured at / ntegrated Device Technology, nc 4

5 TABLE 5B. AC CHAACTESTCS, = 3.3 ± 5%, = 2.5 ± 5%, TA = -40 C TO 85 C f MAX Ouut Frequency 250 MHz LH Propagation Delay, Low to High; NOTE ns HL Propagation Delay, High to Low; NOTE ns tsk(i) nput Skew; NOTE ps tjit Buffer Additive Phase Jitter, MS; refer to Additive Phase Jitter Section; NOTE MHz, (12kHz to 20MHz) 0.14 ps tsk(pp) Part-to-Part Skew; NOTE 2, ps t / t F Ouut ise/fall Time 20% to 80% ps odc Ouut Duty Cycle % MUX SOL MUX 100MHz 45 db NOTE 1: Measured from /2 of the input to /2 of the ouut. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defi ned as skew between ouuts on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the ouut is measured at /2. TABLE 5C. AC CHAACTESTCS, = 3.3 ± 5%, = 1.8 ± 5%, TA = -40 C TO 85 C f MAX Ouut Frequency 250 MHz LH Propagation Delay, Low to High; NOTE ns HL Propagation Delay, High to Low; NOTE ns tsk(i) nput Skew; NOTE ps tjit Buffer Additive Phase Jitter, MS; refer to Additive Phase Jitter Section; NOTE MHz, (12kHz to 20MHz) 0.16 ps tsk(pp) Part-to-Part Skew; NOTE 2, ps t / t F Ouut ise/fall Time 20% to 80% ps odc Ouut Duty Cycle % MUX SOL MUX 100MHz 45 db NOTE 1: Measured from /2 of the input to /2 of the ouut. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defi ned as skew between ouuts on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the ouut is measured at / ntegrated Device Technology, nc 5

6 TABLE 5D. AC CHAACTESTCS, = = 2.5 ± 5%, TA = -40 C TO 85 C f MAX Ouut Frequency 250 MHz LH Propagation Delay, Low to High; NOTE ns HL Propagation Delay, High to Low; NOTE ns tsk(i) nput Skew; NOTE ps tjit Buffer Additive Phase Jitter, MS; refer to Additive Phase Jitter Section; NOTE MHz, (12kHz to 20MHz) 0.21 ps tsk(pp) Part-to-Part Skew; NOTE 2, ps t / t F Ouut ise/fall Time 20% to 80% ps odc Ouut Duty Cycle % MUX SOL MUX 100MHz 45 db NOTE 1: Measured from /2 of the input to /2 of the ouut. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defi ned as skew between ouuts on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the ouut is measured at /2. TABLE 5E. AC CHAACTESTCS, = 2.5 ± 5%, = 1.8 ± -5%, TA = -40 C TO 85 C f MAX Ouut Frequency 250 MHz LH Propagation Delay, Low to High; NOTE ns HL Propagation Delay, High to Low; NOTE ns tsk(i) nput Skew; NOTE ps tjit Buffer Additive Phase Jitter, MS; refer to Additive Phase Jitter Section; NOTE MHz, (12kHz to 20MHz) 0.17 ps tsk(pp) Part-to-Part Skew; NOTE 2, ps t / t F Ouut ise/fall Time 20% to 80% ps odc Ouut Duty Cycle % MUX SOL MUX 100MHz 45 db NOTE 1: Measured from /2 of the input to /2 of the ouut. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defi ned as skew between ouuts on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the ouut is measured at / ntegrated Device Technology, nc 6

7 ATE PHASE JTTE The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specifi ed plot in many applications. Phase noise is defi ned as the ratio of the noise power present in a 1Hz band at a specifi ed offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dbm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. t is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase MHz (12kHz to 20MHz) = 0.19ps typical SSB PHASE NOSE dbc/hz OFFSET FOM CAE FEQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise fl oor of the equipment is higher than the noise fl oor of the device. This is illustrated above. The device meets the noise fl oor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment ntegrated Device Technology, nc 7

8 PAAMETE MEASUEMENT NFOMATON 3.3 COE/3.3 OUTPUT LOAD AC TEST CCUT 2.5 COE/2.5 OUTPUT LOAD AC TEST CCUT 3.3 COE/2.5 OUTPUT LOAD AC TEST CCUT 3.3 COE/1.8 OUTPUT LOAD AC TEST CCUT 2.5 COE/1.8 OUTPUT LOAD AC TEST CCUT PAT-TO-PAT SKEW 2016 ntegrated Device Technology, nc 8

9 POPAGATON DELAY OUTPUT SE/FALL TME NPUT SKEW OUTPUT DUTY CYCLE/PULSE WDTH/PEOD 2016 ntegrated Device Technology, nc 9

10 APPLCATON NFOMATON ECOMMENDATONS FO UNUSED NPUT PNS NPUTS: CLK NPUT: For applications not requiring the use of a clock input, it can be left fl oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. LCMOS CONTOL PNS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used ntegrated Device Technology, nc 10

11 ELABLTY NFOMATON TABLE 6. θ JA S. A FLOW TABLE FO 16 LEAD TSSOP θ JA by elocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards C/W C/W C/W Multi-Layer PCB, JEDEC Standard Test Boards 89.0 C/W 81.8 C/W 78.1 C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TANSSTO COUNT The transistor count for is: ntegrated Device Technology, nc 11

12 PACKAGE OUTLNE - G SUFFX FO 16 LEAD TSSOP TABLE 7. PACKAGE DMENSONS Millimeters SYMBOL Minimum Maximum N 16 A A A b c D E 6.40 BASC E e 0.65 BASC L α 0 8 aaa eference Document: JEDEC Publication 95, MO ntegrated Device Technology, nc 12

13 TABLE 8. ODENG NFOMATON Part/Order Number Marking Package Shipping Packaging Temperature 83056AGLF 83056AL 16 Lead Lead-Free TSSOP tube -40 C to 85 C 83056AGLFT 83056AL 16 Lead Lead-Free TSSOP tape & reel -40 C to 85 C 2016 ntegrated Device Technology, nc 13

14 ESON HSTOY SHEET ev Table Page Description of Change Date A T8 12 Ordering nformation Table - added Lead-Free marking. 1/18/06 B B B T5A - T5E Features Section - added Additive Phase Jitter bullet. AC Characteristics Tables - added tjit row and spec. Added Additive Phase Jitter section. T8 13 Ordering nformation - removed leaded devices. Updated data sheet format. T8 13 Ordering nformation - emoved CS from the Part/Order Number. Deleted LF note below table. Updated header and footer. 01/04/07 3/20/15 3/10/ ntegrated Device Technology, nc 14

15 Corporate Headquarters 6024 Silver Creek alley oad San Jose, CA USA Sales or Fax: Tech Support DSCLAME ntegrated Device Technology, nc. (DT) reserves the right to modify the products and/or specifi cations described herein at any time, without notice, at DT's sole discretion. Performance specifi cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of DT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of DT or any third parties. DT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an DT product can be reasonably expected to signifi cantly affect the health or safety of users. Anyone using an DT product in such a manner does so at their own risk, absent an express, written agreement by DT. ntegrated Device Technology, DT and the DT logo are trademarks or registered trademarks of DT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of DT or their respective third party owners. For datasheet type defi nitions and a glossary of common terms, visit Copyright 2016 ntegrated Device Technology, nc. All rights reserved.