FEATURES Four-bit, 2:1 single-ended multiplexer Nominal output impedance: 15Ω (V PIN ASSIGNMENT BLOCK DIAGRAM

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1 4-Bit, 2:1, Single-Ended Multiplexer 83054I-01 Datasheet GENEAL DESCIPTION The 83054I-01 is a 4-bit, 2:1, Single-ended Multiplexer and a member of the family of High Performance Clock Solutions from IDT. The 83054I-01 has two selectable single-ended clock inputs and four single-ended clock ouuts. The ouut has a pin which may be set at 3.3, 2.5, or 1.8, making the device ideal for use in voltage translation applications. An ouut enable pin places the ouut in a high impedance state which may be useful for testing or debug. Possible applications include systems with up to four transceivers which need to be independently set for different rates. For example, a board may have four transceivers, each of which need to be independently confi gured for 1 Gigabit Ethernet or 1 Gigabit Fibre Channel rates. Another possible application may require the ports to be independently set for FEC (Forward Error Correction) or non-fec rates. The device operates up to 250MHz and is packaged in a 16 TSSOP. FEATUES Four-bit, 2:1 single-ended multiplexer Nominal ouut impedance: 15Ω ( = 3.3) Maximum ouut frequency: 250MHz Propagation delay: 3.2ns (maximum), = = 3.3 Input skew: 170ps (maximum), = = 3.3 Ouut skew: 90ps (maximum), = = 3.3 Part-to-part skew: 800ps (maximum), = = 3.3 Additive phase jitter, MS at MHz, (12kHz 20MHz): 0.18ps (typical) Operating supply modes: / 3.3/ / / C to 85 C ambient operating temperature Available in lead-free (ohs 6) package BLOCK DIAGAM PIN ASSIGNMENT SEL0 CLK0 CLK1 Pulldown Pulldown Pulldown 0 1 Q0 SEL3 Q3 GND Q2 SEL2 CLK SEL0 Q0 GND Q1 SEL1 CLK0 OE 0 1 Q I Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top iew SEL3 OE Pulldown Pullup 2015 Integrated Device Technology, Inc 1

2 TABLE 1. PIN DESCIPTIONS Number Name Type Description 1, 6 11, 16 SEL3, SEL2, SEL1, SEL0 Input Pulldown Clock select inputs. See Control Input Function Table. LCMOS / LTTL interface levels. 2, 5, 12, 15 Q3, Q2, Q1, Q0 Ouut Single-ended clock ouut. LCMOS/LTTL interface levels. 3, 14 Power Ouut supply pins. 4, 13 GND Power Power supply ground. 7, 10 CLK1, CLK0 Input Pulldown Single-ended clock inputs. LCMOS/LTTL interface levels. 8 Power Positive supply pin. Ouut enable. When LOW, ouuts are in HIGH impedance state. 9 OE Input Pullup When HIGH, ouuts are active. LCMOS / LTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHAACTEISTICS C IN Input Capacitance 4 pf PULLUP Input Pullup esistor 51 kω PULLDOWN Input Pulldown esistor 51 kω C PD OUT Power Dissipation Capacitance (per ouut) Ouut Impedance = pf = pf = pf = Ω = Ω = Ω TABLE 3. CONTOL INPUT FUNCTION TABLE Control Inputs Ouuts SELx Qx 0 CLK0 1 CLK Integrated Device Technology, Inc 2

3 ABSOLUTE MAXIMUM ATINGS Supply oltage, 4.6 Inputs, I -0.5 to Ouuts, O -0.5 to Package Thermal Impedance, θ JA C/W (0 mps) Storage Temperature, T STG -65 C to 150 C NOTE: Stresses beyond those listed under Absolute Maximum atings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWE SUPPLY DC CHAACTEISTICS, = 3.3±5%, = 3.3±5%, O 2.5±5%, O 1.8±0.2, TA = -40 C TO 85 C Power Supply oltage Ouut Supply oltage I Power Supply Current 45 ma I Ouut Supply Current No Load 5 ma TABLE 4B. POWE SUPPLY DC CHAACTEISTICS, = 2.5±5%, = 2.5±5%, O 1.8±0.2, TA = -40 C TO 85 C Power Supply oltage Ouut Supply oltage I Power Supply Current 40 ma I Ouut Supply Current No Load 5 ma 2015 Integrated Device Technology, Inc 3

4 TABLE 4C. LCMOS/LTTL DC CHAACTEISTICS, TA = -40 C TO 85 C IH IL I IH I IL Input High oltage Input Low oltage Input High Current Input Low Current OH Ouut Higholtage; = 3.3 ± 5% = 2.5 ± 5% = 3.3 ± 5% = 2.5 ± 5% CLK0, CLK1, SEL0:SEL3 = 3.3 or 2.5 ± 5% 150 µa OE = 3.3 or 2.5 ± 5% 5 µa CLK0, CLK1, SEL0:SEL3 = 3.3 or 2.5 ± 5% -5 µa OE = 3.3 or 2.5 ± 5% -150 µa = 3.3 ± 5% 2.6 = 2.5 ± 5% 1.8 = 1.8 ± = 3.3 ± 5% 0.5 OL Ouut Low oltage; = 2.5 ± 5% 0.45 = 1.8 ± : Ouuts terminated with 50Ω to See Parameter Measurement section, Load Test Circuit diagrams. TABLE 5A. AC CHAACTEISTICS, = = 3.3 ± 5%, TA = -40 C TO 85 C f MAX Ouut Frequency 250 MHz LH Propagation Delay, Low to High; ns HL Propagation Delay, High to Low; ns tsk(o) Ouut Skew; NOTE 2, ps tsk(i) Input Skew; NOTE ps tsk(pp) Part-to-Part Skew; NOTE 2, ps tjit Buffer Additive Phase Jitter, MS; refer to Additive Phase Jitter section, NOTE , Integration ange: 12kHz 20MHz 0.18 ps t / t F Ouut ise/fall Time 20% to 80% ps odc Ouut Duty Cycle ƒout 175MHz % MUX ISOL MUX 45 db : Measured from /2 of the input to /2 of the ouut. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between ouuts at the same voltage and with equal load conditions. Measured at NOTE 4: Defi ned as skew between ouuts on different devices operating a the same supply voltags and with equal load conditions. Using the same type of input on each device, the ouut is measured at NOTE 5: Driving only one input clock Integrated Device Technology, Inc 4

5 TABLE 5B. AC CHAACTEISTICS, = 3.3 ± 5%, = 2.5 ± 5%, TA = -40 C TO 85 C f MAX Ouut Frequency 250 MHz LH Propagation Delay, Low to High; ns HL Propagation Delay, High to Low; ns tsk(o) Ouut Skew; NOTE 2, ps tsk(i) Input Skew; NOTE ps tsk(pp) Part-to-Part Skew; NOTE 2, ps tjit Buffer Additive Phase Jitter, MS; refer to Additive Phase Jitter section, NOTE , Integration ange: 12kHz 20MHz 0.14 ps t / t F Ouut ise/fall Time 20% to 80% ps odc Ouut Duty Cycle % MUX ISOL MUX 45 db : Measured from /2 of the input to /2 of the ouut. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between ouuts at the same voltage and with equal load conditions. Measured at NOTE 4: Defi ned as skew between ouuts on different devices operating a the same supply voltags and with equal load conditions. Using the same type of input on each device, the ouut is measured at NOTE 5: Driving only one input clock. TABLE 5C. AC CHAACTEISTICS, = 3.3 ± 5%, = 1.8 ± 0.2, TA = -40 C TO 85 C f MAX Ouut Frequency 250 MHz LH Propagation Delay, Low to High; ns HL Propagation Delay, High to Low; ns tsk(o) Ouut Skew; NOTE 2, ps tsk(i) Input Skew; NOTE ps tsk(pp) Part-to-Part Skew; NOTE 2, ps tjit Buffer Additive Phase Jitter, MS; refer to Additive Phase Jitter section, NOTE , Integration ange: 12kHz 20MHz 0.16 ps t / t F Ouut ise/fall Time 20% to 80% ps odc Ouut Duty Cycle % MUX ISOL MUX 45 db : Measured from /2 of the input to /2 of the ouut. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between ouuts at the same voltage and with equal load conditions. Measured at NOTE 4: Defi ned as skew between ouuts on different devices operating a the same supply voltags and with equal load conditions. Using the same type of input on each device, the ouut is measured at NOTE 5: Driving only one input clock Integrated Device Technology, Inc 5

6 TABLE 5D. AC CHAACTEISTICS, = = 2.5 ± 5%, TA = -40 C TO 85 C f MAX Ouut Frequency 250 MHz LH Propagation Delay, Low to High; ns HL Propagation Delay, High to Low; ns tsk(o) Ouut Skew; NOTE 2, ps tsk(i) Input Skew; NOTE ps tsk(pp) Part-to-Part Skew; NOTE 2, ps tjit Buffer Additive Phase Jitter, MS; refer to Additive Phase Jitter section, NOTE , Integration ange: 12kHz 20MHz 0.22 ps t / t F Ouut ise/fall Time 20% to 80% ps odc Ouut Duty Cycle ƒout 175MHz % MUX ISOL MUX 45 db : Measured from /2 of the input to /2 of the ouut. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between ouuts at the same voltage and with equal load conditions. Measured at NOTE 4: Defi ned as skew between ouuts on different devices operating a the same supply voltags and with equal load conditions. Using the same type of input on each device, the ouut is measured at NOTE 5: Driving only one input clock. TABLE 5E. AC CHAACTEISTICS, = 2.5 ± 5%, = 1.8 ± 0.2, TA = -40 C TO 85 C f MAX Ouut Frequency 250 MHz LH Propagation Delay, Low to High; ns HL Propagation Delay, High to Low; ns tsk(o) Ouut Skew; NOTE 2, ps tsk(i) Input Skew; NOTE ps tsk(pp) Part-to-Part Skew; NOTE 2, ps tjit Buffer Additive Phase Jitter, MS; refer to Additive Phase Jitter section, NOTE , Integration ange: 12kHz 20MHz 0.19 ps t / t F Ouut ise/fall Time 20% to 80% ps odc Ouut Duty Cycle ƒout 200MHz % MUX ISOL MUX 45 db : Measured from /2 of the input to /2 of the ouut. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Defi ned as skew between ouuts at the same voltage and with equal load conditions. Measured at NOTE 4: Defi ned as skew between ouuts on different devices operating a the same supply voltags and with equal load conditions. Using the same type of input on each device, the ouut is measured at NOTE 5: Driving only one input clock Integrated Device Technology, Inc 6

7 AITIE PHASE JITTE The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specifi ed plot in many applications. Phase noise is defi ned as the ratio of the noise power present in a 1Hz band at a specifi ed offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dbm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. SSB PHASE NOISE dbc/hz Additive Phase Jitter (andom) at MHz (12kHz - 20MHz) = 0.18ps (typical) 1k 10k 100k 1M 10M 100M OFFSET FOM CAIE FEQUENCY (HZ) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise fl oor of the equipment is higher than the noise fl oor of the device. This is illustrated above. The device meets the noise fl oor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment Integrated Device Technology, Inc 7

8 PAAMETE MEASUEMENT INFOMATION 3.3 COE/3.3 OUTPUT LOAD AC TEST CICUIT 2.5 COE5 OUTPUT LOAD AC TEST CICUIT 3.3 COE5 OUTPUT LOAD AC TEST CICUIT 3.3 COE/1.8 OUTPUT LOAD AC TEST CICUIT 2.5 COE/1.8 OUTPUT LOAD AC TEST CICUIT PAT-TO-PAT SKEW 2015 Integrated Device Technology, Inc 8

9 POPAGATION DELAY OUTPUT ISE/FALL TIME OUTPUT SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PEIOD INPUT SKEW 2015 Integrated Device Technology, Inc 9

10 APPLICATION INFOMATION ECOMMENDATIONS FO UNUSED INPUT AND OUTPUT PINS INPUTS: CLK INPUTS For applications not requiring the use of a clock input, it can be left fl oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. OUTPUTS: LCMOS OUTPUTS All unused LCMOS ouut can be left fl oating. There should be no trace attached. LCMOS CONTOL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ELIABILITY INFOMATION TABLE 5. θ JA S. AI FLOW TABLE FO 16 LEAD TSSOP θ JA by elocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards C/W 96.0 C/W 93.9 C/W TANSISTO COUNT The transistor count for 83054I-01 is: Integrated Device Technology, Inc 10

11 PACKAGE OUTLINE - G SUFFIX FO 16 LEAD TSSOP TABLE 6. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum Maximum N 16 A A A b c D E 6.40 BASIC E e 0.65 BASIC L α 0 8 aaa eference Document: JEDEC Publication 95, MO Integrated Device Technology, Inc 11

12 TABLE 7. ODEING INFOMATION Part/Order Number Marking Package Shipping Packaging Temperature 83054AGI-01LF 054AI01L 16 lead Lead Free TSSOP Tray -40 C to +85 C 83054AGI-01LFT 054AI01L 16 lead Lead Free TSSOP Tape and eel -40 C to +85 C 2015 Integrated Device Technology, Inc 12

13 EISION HISTOY SHEET ev Table Page Description of Change Date A T General Description - removed ICS chip and HiPerClocks. Features Section - removed reference to leaded package. Ordering Information - removed leaded parts and the LF note below the table. Updated header and footer Integrated Device Technology, Inc 13

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