ICS LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ICS853011

Transcription

1 DIFFERENTIAL-TO-2.5/ LPECL/ECL Systems, FANOUT Inc. BUFFER DATA SHEET GENERAL DESCRIPTION The is a low skew, high performance 1-to-2 Differential-to-2.5/ LPECL/ ICS HiPerClockS ECL Fanout Buffer and a member of the HiPerClockS family of High Performance Clock Solutions from ICS. The is characterized to operate from either a 2.5 or a power supply. Guaranteed output and part-to-part skew characteristics make the ideal for those clock distribution applications demanding well defined performance and repeatability. FEATURES 2 differential 2.5/ LPECL / ECL outputs 1 differential, n input pair, n pair can accept the following differential input levels: LPECL, LDS, CML, SSTL imum output frequency: >3GHz Translates any single ended input signal to LPECL levels with resistor bias on n input Output skew: 5ps (typical) Part-to-part skew: 130ps (maximum) Propagation delay: 390ps (maximum) Additive phase jitter, RMS: 0.06ps (typical) LPECL mode operating voltage supply range: CC = to 3.8, EE = 0 ECL mode operating voltage supply range: CC = 0, EE = -3.8 to C to 85 C ambient operating temperature Available in both Standard and lead-free RoHS compliant packages BLOCK DIAGRAM PIN ASSIGNMENT n Q0 nq0 Q1 nq1 Q0 nq0 Q1 nq cc n EE 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top iew 8-Lead TSSOP, 118 mil 3mm x 3mm x 0.95mm package body G Package Top iew

2 TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 Q0, nq0 3, 4 Q1, nq1 5 EE 6 n 7 8 CC NOTE: Pullup and Pulldow n e Description O utput Differential output pair. LPECL interface levels. O utput Differential output pair. LPECL interface levels. P ower Negative supply pin. Pullup/ Pulldown ulldown Clock input. /2 default when left floating. LPECL interface levels. C C P Clock input. Default LOW when left floating. LPECL interface levels. P ower Positive supply pin. refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol R PULLDOWN R CC/ 2 Parameter Test Conditions imum ical imum Pulldown Resistor 75 kω Pullup/Pulldown Resistors kω Units 2 2

3 ABSOLUTE MAXIMUM RATINGS Supply oltage, CC 4.6 (LPECL mode, EE = 0) Negative Supply oltage, EE -4.6 (ECL mode, CC = 0) s, I (LPECL mode) -0.5 to CC s, I (ECL mode) 0.5 to EE Outputs, I O Continuous Current ma Surge Current 100mA Operating Temperature Range, TA -40 C to +85 C Storage Temperature, T STG -65 C to C Package Thermal Impedance, θ JA C/W (0 lfpm) (Junction-to-Ambient) for 8 Lead SOIC Package Thermal Impedance, θ JA C/W (0 m/s) (Junction-to-Ambient) for 8 Lead TSSOP NOTE: Stresses beyond those listed under Absolute imum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, CC = TO 3.8; EE = 0 Symbol CC I EE Parameter Test Conditions imum ical imum Positive Supply oltage Power Supply Current 25 ma Units TABLE 3B. LPECL DC CHARACTERISTICS, CC = ; EE = 0 Symbol Parameter C 25 C 85 C Units OH Output High oltage; NOTE OL Output Low oltage; NOTE PP Peak-to-Peak oltage High oltage CMR Common Mode Range; NOTE 2, I IH High Current, n I IL Low Current n and output parameters vary 1:1 with. can vary to CC E E NOTE 1: Outputs terminated with Ω to - 2. C CO NOTE 2: Common mode voltage is defined as. I H NOTE 3: For single-ended applications, the maximum input voltage for, n is C C 3 3

4 TABLE 3C. LPECL DC CHARACTERISTICS, CC = 2.5; EE = 0 Symbol TABLE 3D. ECL DC CHARACTERISTICS, CC = 0; EE = -3.8 TO Symbol TABLE 4. AC CHARACTERISTICS, CC = 0; EE = -3.8 TO OR CC = TO 3.8; EE = 0 Symbol f Parameter -40 C 25 C 85 C Output Frequency > 3 > 3 > 3 GHz MAX t PD ropagation Delay; NOTE 1 P ps t sk(o) Output Skew; NOTE 2, ps t sk(pp) Part-to-Part Skew; NOTE 3, ps tjit t R /t F Parameter OH utput High oltage; NOTE 1 OL utput Low oltage; NOTE 1 PP eak-to-peak oltage I IH I IL CMR Parameter OH utput High oltage; NOTE 1 OL utput Low oltage; NOTE 1 PP eak-to-peak oltage I IH I IL CMR Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section, Integration Range: 12KHz to 20MHz -40 C 25 C 85 C 4 Units ps O utput Rise/Fall Time 20% to 80% ps odc Output Duty Cycle f 1GHz % All parameters are measured at f 1.7GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. O O P High oltage Common Mode Range; NOTE 2, 3 EE EE EE , n High Current Low Current and output parameters vary 1:1 with NOTE 1: Outputs terminated with Ω to NOTE 2: Common mode voltage is defined NOTE 3: For single-ended applications, -40 C 25 C 85 C O O P High oltage Common Mode Range; NOTE 2, High Current, n Low Current n For notes see above Table 3B, LPECL DC Characteristics. n can vary to CC E E - 2. C CO as. I H the maximum input voltage for, n is C C Units Units 4

5 ADDITIE PHASE JITTER The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dbm) or a ratio of the power in As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The dethe 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase Jitter MHz@12kHz to 20MHz = 0.06ps (typical) SSB PHASE NOISE dbc/hz k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 5 5

6 PARAMETER MEASUREMENT INFORMATION 2 CC, CCO Qx SCOPE CC n LPECL nqx PP Cross Points CMR EE EE -1.8 to OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEEL nqx PART 1 Qx nqx Qx nqy PART 2 Qy tsk(pp) nqy Qy tsk(o) PART-TO-PART SKEW OUTPUT SKEW n 80% 80% SWING Clock Outputs 20% t R t F 20% nq0, nq1 Q0, Q1 t PD OUTPUT RISE/FALL TIME PROPAGATION DELAY nq0, nq1 Q0, Q1 t PW t PERIOD odc = t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 6 6

7 APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage _REF = CC /2 is generated by the bias resistors, and C1. This bias circuit should be located as close as possible to the input pin. The ratio of and might need to be adjusted to position the _REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5 and CC =, _REF should be 1.25 and / = CC Single Ended Clock 1K _REF n C1 0.1u 1K FIGURE 1. SINGLE ENDED SIGNAL DRIING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: LPECL OUTPUT All unused LPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. 7 7

8 LPECL CLOCK INPUT INTERFACE The /n accepts LPECL, CML, SSTL and other differential signals. Both SWING and OH must meet the PP and CMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS /n input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5 CML 2.5 SSTL Zo = 60 Ohm Zo = 60 Ohm R3 120 R4 120 n HiPerClockS /n n HiPerClockS /n FIGURE 2A. HIPERCLOCKS /N INPUT DRIEN FIGURE 2B. HIPERCLOCKS /N INPUT DRIEN BY A CML DRIER BY AN SSTL DRIER R3 125 R4 125 LDS C1 R3 1K R4 1K LPECL n HiPerClockS R5 100 C2 1K 1K n HiPerClockS /n FIGURE 2C. HIPERCLOCKS /N INPUT DRIEN FIGURE 2D. HIPERCLOCKS /N INPUT DRIEN BY A LPECL DRIER BY A LDS DRIER LPECL C1 R3 84 R4 84 C2 n HiPerClockS /n R R FIGURE 2E. HIPERCLOCKS /N INPUT DRIEN BY A LPECL DRIER WITH AC COUPLE 8 8

9 TERMINATION FOR LPECL OUTPUTS The clock layout topology shown below is a typical termination for LPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nfout are low impedance follower outputs that generate ECL/LPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Z o = Ω 125Ω 125Ω FOUT FIN Z o = Ω Z o = Ω FOUT FIN RTT = 1 (( OH + OL ) / ( CC 2)) 2 Z o Ω Ω RTT CC - 2 Z o = Ω 84Ω 84Ω FIGURE 3A. LPECL OUTPUT TERMINATION FIGURE 3B. LPECL OUTPUT TERMINATION 9 9

10 TERMINATION FOR 2.5 LPECL OUTPUT Figure 4A and Figure 4B show examples of termination for 2.5 LPECL driver. These terminations are equivalent to terminating Ω to CC - 2. For CC = 2.5, the CC - 2 is very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. CCO= R CCO= ,5 LPECL Driver 62.5 R ,5 LPECL Driver - R3 18 FIGURE 4A. 2.5 LPECL DRIER TERMINATION EXAMPLE FIGURE 4B. 2.5 LPECL DRIER TERMINATION EXAMPLE CCO= ,5 LPECL Driver - FIGURE 4C. 2.5 LPECL TERMINATION EXAMPLE 10 10

11 POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for CC = 3.8, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Power (core) MAX = CC_MAX * I EE_MAX = 3.8 * 25mA = 95mW Power (outputs) MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.94mW = 61.88mW Total Power _MAX (3.8, with all outputs switching) = 95mW mW = mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125 C. The equation for Tj is as follows: Tj = θ JA * Pd_total + T A Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is C/W per Table 5A below. Therefore, Tj for an ambient temperature of 85 C with all outputs switching is: 85 C W * C/W = C. This is well below the limit of 125 C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 5A. THERMAL RESISTANCE θ JA FOR 8-PIN SOIC, FORCED CONECTION θ JA by elocity (Linear Feet per ute) Single-Layer PCB, JEDEC Standard Test Boards C/W C/W C/W Multi-Layer PCB, JEDEC Standard Test Boards C/W C/W 97.1 C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 5B. THERMAL RESISTANCE θ JA FOR 8-PIN TSSOP, FORCED CONECTION θ JA by elocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards C/W 90.5 C/W 89.8 C/W 11 11

12 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LPECL output driver circuit and termination are shown in Figure 5. CC Q1 OUT RL CC - 2 FIGURE 5. LPECL DRIER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a Ω load, and a termination voltage of - 2. CC For logic high, OUT = OH_MAX = CC_MAX ( CC_MAX - OH_MAX ) = For logic low, OUT = OL_MAX = CC_MAX 1.67 ( CC_MAX - OL_MAX ) = 1.67 Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [( ( - 2))/R OH_MAX CC_MAX [( )/Ω] * = 19.92mW L] * ( CC_MAX - ) = [(2 - ( - ))/R * ( - ) = OH_MAX CC_MAX OH_MAX L] CC_MAX OH_MAX Pd_L = [( ( - 2))/R OL_MAX CC_MAX [(2-1.67)/Ω] * 1.67 = 11.02mW L] * ( CC_MAX Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW - ) = [(2 - ( - ))/R * ( - ) = OL_MAX CC_MAX OL_MAX L] CC_MAX OL_MAX 12 12

13 RELIABILITY INFORMATION TABLE 6A. θ JA S. AIR FLOW TABLE FOR 8 LEAD SOIC θ JA by elocity (Linear Feet per ute) Single-Layer PCB, JEDEC Standard Test Boards C/W C/W C/W Multi-Layer PCB, JEDEC Standard Test Boards C/W C/W 97.1 C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 6B. θ JA S. AIR FLOW TABLE FOR 8 LEAD TSSOP θ JA by elocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards C/W 90.5 C/W 89.8 C/W TRANSISTOR COUNT The transistor count for is: 96 Pin compatible with MC100LEP11 and SY100EP11U 13 13

14 PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 7A. PACKAGE DIMENSIONS SYMBOL MINIMUN Millimeters N 8 MAXIMUM A A B C D E e 1.27 BASIC H h L α 0 8 Reference Document: JEDEC Publication 95, MS-012 TABLE 7B. PACKAGE DIMENSIONS SYMBOL imum Millimeters N 8 imum A A A b c D E E1 e e BASIC 4.90 BASIC 3.00 BASIC 0.65 BASIC 1.95 BASIC L α 0 8 aaa Reference Document: JEDEC Publication 95, MO

15 TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature BM BM 8 lead SOIC tube -40 C to 85 C BMT BM 8 lead SOIC C to 85 C BMLF BL 8 lead "Lead Free" SOIC tube -40 C to 85 C BMLFT BL 8 lead "Lead Free" SOIC C to 85 C BG 011B 8 lead TSSOP tube -40 C to 85 C BGT 011B 8 lead TSSOP C to 85 C BGLF 11BL 8 lead "Lead Free" TSSOP tube -40 C to 85 C BGLFT 11BL 8 lead "Lead Free" TSSOP C to 85 C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments

16 REISION HISTORY SHEET Rev B B C C C Table T3B T3C T3D Page T T8 15 T5B T6B T Description of Change LPECL Table - 85, from min. to 2.22 min. O H and 2.33 typical to typical. 2.5 LPECL Table - 85, from min. to 1.42 min. and OH 1.53 typical to typical. ECL Table - changed 85, from min. to min. and typical to typical. Updated LPECL Output Termination Diagrams. Updated LPECL Clock Inteface Figure 4D. Corrected Figure 4C. Added "Lead Free" Part/Order Number rows. AC Characteristics Table - added Additive Phase Jitter. Added Additive Phase Jitter Section. Features Section - added Lead-Free bullet. Added "Recommendations for Unused and Output Pins". Ordering Information Table - corrected Lead-Free marking and added Lead- Free note. Pin Assignment - added 8 Lead TSSOP package. Absolute imum Ratings - added TSSOP to Package Thermal Impedance. Power Considerations - added 8 Lead TSSOP Thermal Resistance. Added 8 Lead TSSOP Reliability Information. Added TSSOP Package Outline and Dimensions. Ordering Information - Added 8 Lead TSSOP part number and marking. Date 9/2/03 11/12/03 9/7/04 7/13/05 11/2/

17 SD0060CN02270T ICS ICS270 ICS852911I Frequency Triple LOW SKEW, MHZ PLL Field DIFFERENTIAL Generator 1-TO-9 1-TO-2 Programmable DIFFERENTIAL-TO-HSTL DIFFERENTIAL-TO-2.5/ & DELAY CXO LINE Buffers Clock FOR for Synthesizer COMMERCIAL FANOUT Mother LPECL/ECL Boards BUFFER APPLICATIONS FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: For Sales Fax: For Tech Support Corporate Headquarters Device Technology, Inc Silver Creek alley Road San Jose, CA United States (outside U.S.) Asia Pacific and Japan Device Technology Singapore (1997) Pte. Ltd. Reg. No G 435 Orchard Road #20-03 Wisma Atria Singapore Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Device Technology, Inc. Accelerated Thinking is a service mark of Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA XX-XXXX-XXXXX