PIN ASSIGNMENT. 0 0 PLL Bypass

Transcription

1 CRYSTAL-TO-LDS PCI EXPRESS CLOCK SYNTHESIZER W/SPREAD SPECTRUM ICS GENERAL DESCRIPTION The ICS is a 2 output PCI Express clock ICS synthesizer optimized to generate low jitter PCIe HiPerClockS referee clocks with or without spread spectrum modulation and is a member of the HiPerClockS family of high performae clock solutions from IDT. Spread type and amount can be configured via the SSC control pins. Using a 25MHz, 18pF parallel resonant crystal, the device will generate LDS clocks at either 25MHz, 100MHz, 125MHz or 250MHz. The ICS uses a low jitter CO that easily meets PCI Express jitter requirements and is packaged in a 32-pin FQFN package. FEATURES Two LDS outputs at 25MHz, 100MHz, 125MHz or 250MHz Crystal oscillator interface, 25MHz, 18pF parallel resonant crystal Supports the following output frequeies: 25MHz, 100MHz, 125MHz or 250MHz CO range: 240MHz - 700MHz Supports SSC downspread at 0.50% and -0.75%, centerspread at ±0.25% and no spread options Cycle-to-cycle jitter: 70 (typical) Period jitter: 40 (typical) Full 3.3 power supply mode 0 C to 70 C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages PIN ASSIGNMENT Q0 nq0 GND GND DDA DDO Q1 nq BLOCK DIAGRAM OE Pullup DD DD DDO FSEL ICS Lead FQFN 5mm x 5mm x 0.75mm package body K Package Top iew GND SSC1 GND Q XTAL_IN XTAL_OUT 25MHz OSC Phase Detector CO MHz 0 0 PLL Bypass nq0 Q1 nq1 FSEL1 SSC0 DD OEB XTAL_IN XTAL_OUT OE GND Feedback Divider 20 SSC[1:0] Pullup:Pullup Default = 100MHz Pulldown:Pullup FSEL[1:0] 2 2 Spread Spectrum Control The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Iorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT / ICS LDS PCI EXPRESS CLOCK SYNTHESIZER 1 ICS844202BK-245 RE. A JULY 9, 2007

2 TABLE 1. PIN DESCRIPTIONS Number Νυμ βερ Name Ναμ ε 1, 2, 11 DD 3, 4, 6, 8, 12, 18, 20, 21, 23, 24 5, 27 DDO 7 FSEL0 9 FSEL1 10, SSC0 19 SSC1 XTAL_IN, 13, 14 XTAL_OUT 15 OE 16, 17, GND 30 25, 26 nq1, Q1 28 DDA 31, 32 nq0, Q0 NOTE: Pullup and Pulldown ΤType ψπ ε Description Δε σχριπτιο ν P ower Core supply pins. U nused No connect. P ower Output supply pins. P ullup Output frequey select pin. See Table 3A. LCMOS/LTTL interface levels. P ulldown Output frequey select pin. See Table 3A. LCMOS/LTTL interface levels. Pullup Pullup Spread spectrum control pins. See Table 3B. LCMOS/LTTL interface levels. Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. (PLL referee.) Output enable pin. Logic HIgh, outputs are enabled. Logic LOW, outputs are in Hi-Z. LCMOS/LTTL interface levels. P ower Power supply ground. O utput Differential output pair. LDS interface levels. P ower Analog supply pin. O utput Differential output pair. LDS interface levels. refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol C IN R R PULLUP PULLDOWN Parameter nput Capacitae nput Pulllup Resistor nput Pulldown Resistor Test Conditions Minimum Typical Maximum Units p I 4 F I 51 kω I 51 kω TABLE 3A. FSEL[1:0] FUNCTION TABLE FSEL1 SEL0 Outputs Q0:1/nQ0: Bypass (25MHz F PLL ) MHz (default) MHz MHz TABLE 3B. SSC[1:0] FUNCTION TABLE SSC1 SSC0 Spread % 0 0 Center ± Down Down No Spread (default) IDT / ICS LDS PCI EXPRESS CLOCK SYNTHESIZER 2 ICS844202BK-245 RE. A JULY 9, 2007

3 ABSOLUTE MAXIMUM RATINGS Supply oltage, DD 4.6 s, I -0.5 to DD Outputs, I O Continuous Current 10mA Surge Current 15mA Package Thermal Impedae, θ JA 42.4 C/W (0 m) Storage Temperature, T STG -65 C to 150 C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Futional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, DD = DDA = DDO = 3.3±5%, TA = 0 C TO 70 C Symbol DD D D I DD I I D DA DO DA D DO Parameter Test Conditions Minimum Typical Maximum Units Core Supply oltage Analog Supply oltage DD DD Output Supply oltage Power Supply Current 83 ma Analog Supply Current 12 ma Output Supply Current 26 ma TABLE 4B. LCMOS / LTTL DC CHARACTERISTICS, DD = DDA = DDO = 3.3±5%, TA = 0 C TO 70 C Symbol IH IL I IH I IL Parameter nput High oltage nput Low oltage Test Conditions Minimum Typical Maximum D I 2 D + I FSEL1 DD = IN = µ A High Current SSC0, SSC1, FSEL0, OE DD = IN = µ A Low Current FSEL1 DD = 3.465, = 0 IN -5 µ A SSC0, SSC1, FSEL0, OE DD = 3.465, = 0 IN -150 µ A Units TABLE 4C. LDS DC CHARACTERISTICS, DD = DDA = DDO = 3.3±5%, TA = 0 C TO 70 C Symbol OD Δ OD OS Δ OS Parameter ifferential Output Test Conditions Minimum Typical 5 Maximum Units m m D oltage 3 0 OD Magnitude Change 50 Offset oltage 1.33 Magnitude Change 50 m OS IDT / ICS LDS PCI EXPRESS CLOCK SYNTHESIZER 3 ICS844202BK-245 RE. A JULY 9, 2007

4 TABLE 5. CRYSTAL CHARACTERISTICS Parameter Mode of Oscillation Test Conditions Minimum Typical Fundamental Maximum Frequey 25 MHz Equivalent Series Resistae (ESR) TBD Ω Shunt Capacitae 7 pf Drive Level 100 µ W NOTE: Characterized using an 18pF parallel resonant crystal. Units TABLE 6. AC CHARACTERISTICS, DD = DDA = DDO = 3.3±5%, TA = 0 C TO 70 C Symbol f OUT t jit(per) Parameter Output Frequey Period Jitter, RMS tj it(cc) Cycle-to-Cycle Jitter; NOTE 1, 2 Test Conditions Minimum Typical Maximum Units 25 MHz 125 MHz 100 MHz 250 MHz 25MHz MHz MHz MHz 40 25MHz MHz MHz MHz MHz t sk(o) Output Skew; NOTE 2, 3 0 F xtal Crystal Range; NOTE 1 2 F M SSC Modulation Frequey; NOTE 4 TBD khz F MF SSC Modulation Factor; NOTE 4 T BD % SSCred Spectral Reduction; NOTE 5 11 db tstable Power-up to Stable Clock Output 10 ms t R / tf O utput Rise/Fall Time 20% - 80% 525 odc Output Duty Cycle 50 % NOTE 1: This parameter is defined in accordae with JEDEC Standard 65. NOTE 2: Only valid within the CO operating range. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Spread Spectrum clocking enabled. IDT / ICS LDS PCI EXPRESS CLOCK SYNTHESIZER 4 ICS844202BK-245 RE. A JULY 9, 2007

5 PARAMETER MEASUREMENT INFORMATION OH 3.3±10% POWER SUPPLY + Float GND DD, DDO DDA LDS Qx nqx SCOPE 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains % of all measurements 6σ contains ( x10-7 )% of all measurements Referee Point (Trigger Edge) Histogram Mean Period (First edge after trigger) REF OL 3.3 LDS OUTPUT LOAD AC TEST CIRCUIT PERIOD JITTER nqx Qx nq0, nq1 Q0, Q1 nqy tcycle n tcycle n+1 Qy tsk(o) tjit(cc) = tcycle n tcycle n Cycles OUTPUT SKEW CYCLE-TO-CYCLE JITTER Clock Outputs 20% 80% 80% t R t F 20% OD nq0, nq1 Q0, Q1 t PW t PERIOD t PW odc = x 100% t PERIOD OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT / ICS LDS PCI EXPRESS CLOCK SYNTHESIZER 5 ICS844202BK-245 RE. A JULY 9, 2007

6 APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. DD, DDA and DDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performae, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a.01μf bypass capacitor should be connected to each DDA. DD DDA μF 10Ω.01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. C1 27p XTAL_OUT X1 18pF Parallel Crystal C2 27p XTAL_IN FIGURE 2. CRYSTAL INPUt INTERFACE RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: LCMOS CONTROL PINS All control pins have internal pull-u or pull-downs; additional resistae is not required but can be added for additional protection. A 1kΩ resistor can be used. OUTPUTS: LDS OUTPUTS All unused LDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. IDT / ICS LDS PCI EXPRESS CLOCK SYNTHESIZER 6 ICS844202BK-245 RE. A JULY 9, 2007

7 LCMOS TO XTAL INTERFACE The XTAL_IN input can accept a single-ended LCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interferee with the power rail and to reduce noise. This configuration requires that the output impedae of the driver (Ro) plus the series resistae (Rs) equals the transmission line impedae. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedae. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. DD CC DD CC R1 Ro Rs Zo = 50.1uf XTAL_IN Zo = Ro + Rs R2 XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LCMOS DRIER TO XTAL INPUT INTERFACE THERMAL RELEASE PATH The expose metal pad provides heat transfer from the device to the P.C. board. The expose metal pad is ground pad connected to ground plane through thermal via. The exposed pad on the device to the exposed metal pad on the PCB is contacted through solder as shown in Figure 4. For further information, please refer to the Application Note on Surface Mount Assembly of Amkor s Thermally /Electrically Enhae Leadframe Base Package, Amkor Technology. PIN SOLDER EPAD SOLDER PIN PIN PAD GROUND PLANE EXPOSED METAL PAD PIN PAD THERMAL IA (GROUND PAD) FIGURE 4. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE IDT / ICS LDS PCI EXPRESS CLOCK SYNTHESIZER 7 ICS844202BK-245 RE. A JULY 9, 2007

8 3.3 LDS DRIER TERMINATION A general LDS interface is shown in Figure 5. In a 100Ω differential transmission line environment, LDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs LDS + R Ohm Differential Transmission Line FIGURE 5. TYPICAL LDS DRIER TERMINATION IDT / ICS LDS PCI EXPRESS CLOCK SYNTHESIZER 8 ICS844202BK-245 RE. A JULY 9, 2007

9 POWER CONSIDERATIONS This section provides information on power dissipation and jution temperature for the ICS Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for DD = % = 3.645, which gives worst case results. Power (core) MAX = DD_MAX * (I DD_MAX + I DDA_MAX + I DDO_MAX ) = * (83mA + 12mA + 26mA) = 121mW 2. Jution Temperature. Jution temperature, Tj, is the temperature at the jution of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended jution temperature for HiPerClockS TM devices is 125 C. The equation for Tj is as follows: Tj = θ JA * Pd_total + T A Tj = Jution Temperature θ JA = Jution-to-Ambient Thermal Resistae Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate jution temperature, the appropriate jution-to-ambient thermal resistae θ JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 42.4 C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70 C with all outputs switching is: 70 C W * 42.4 C/W = 75.1 C. This is well below the limit of 125 C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θ JA FOR 32-LEAD FQFN, FORCED CONECTION θ JA by elocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 42.4 C/W 37.0 C/W 33.2 C/W IDT / ICS LDS PCI EXPRESS CLOCK SYNTHESIZER 9 ICS844202BK-245 RE. A JULY 9, 2007

10 RELIABILITY INFORMATION TABLE 7. θ JA S. AIR FLOW TABLE FOR 32 LEAD FQFN θ JA by elocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 42.4 C/W 37.0 C/W 33.2 C/W TRANSISTOR COUNT The transistor count for ICS is: 4715 IDT / ICS LDS PCI EXPRESS CLOCK SYNTHESIZER 10 ICS844202BK-245 RE. A JULY 9, 2007

11 PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD FQFN TABLE 8. PACKAGE DIMENSIONS SYMBOL JEDEC ARIATION ALL DIMENSIONS IN MILLIMETERS HHD-2 MINIMUM NOMINAL MAXIMUM N 32 A A A Ref. b N D 8 N E 8 D 5.00 BASIC D E 5.00 BASIC E e 0.50 BASIC L Referee Document: JEDEC Publication 95, MO-220 IDT / ICS LDS PCI EXPRESS CLOCK SYNTHESIZER 11 ICS844202BK-245 RE. A JULY 9, 2007

12 TABLE 9. ORDERING INFORMATION Part/Order Number ICS844202BK-245 ICS844202BK-245T ICS844202BK-245LF ICS844202BK-245LFT NOTE: Parts that are ordered Marking TBD TBD ICS402B245L ICS402B245L an "LF" suffix with Package Shipping Packaging Temperature 32 Lead FQFN tray 0 C to 70 C 32 Lead FQFN 2500 tape & reel 0 C to 70 C 32 Lead "Lead-Free" FQFN tray 0 C to 70 C 32 Lead "Lead-Free" FQFN 2500 tape & reel 0 C to 70 C to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Iorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extneded temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT / ICS LDS PCI EXPRESS CLOCK SYNTHESIZER 12 ICS844202BK-245 RE. A JULY 9, 2007

13 Innovate with IDT and accelerate your future networks. Contact: For Sales Fax: For Tech Support Corporate Headquarters Integrated Device Technology, I Silver Creek alley Road San Jose, CA United States (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No G 435 Orchard Road #20-03 Wisma Atria Singapore Europe IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) Fax: +44 (0) Integrated Device Technology, I. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, I. Accelerated Thinking is a service mark of Integrated Device Technology, I. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA