Clock Generator for PowerQUICC III
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1 MOTOROLA SEMICONDUCTOR TECHNICAL DATA The is a PLL based clock generator specifically designed for Motorola Microprocessor And Microcontroller applications including the PowerQUICC III. This device generates a microprocessor input clock plus the 500 Rapid I/O clock. The microprocessor clock is selectable in output frequency to any of the commonly used microprocessor input and bus frequencies. The Rapid I/O outputs are LVDS compatible. The device offers eight low skew clock outputs organized into two output banks, each configurable to support different clock frequencies. The extended temperature range of the supports telecommunication and networking requirements. Features 8 LVCMOS outputs for processor and other circuitry 2 differential LVDS outputs for Rapid I/O interface Crystal oscillator or external reference input 25 or 33 Input reference frequency Selectable output frequencies include = 200, 66, 33,25,, 00, 83, 66, 50, 33 or 6 Buffered reference clock output Rapid I/O (LVDS) Output = 500, 250 or 25 Low cycle-to-cycle and period jitter 00-lead PBGA package 00-lead Pb-free Package Available 3.3V supply with 3.3V or 2.5V output LVCMOS drive Supports computing, networking, telecommunications applications Ambient temperature range 40 C to +85 C MICROPROCESSOR CLOCK GENERATOR Order number: Rev 0, 07/2004 Functional Description The uses either a 25 or 33 reference frequency to generate 8 LVCMOS output clocks, of which, the frequency is selectable from 6 to 200. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers, divide this frequency by 0, 2, 5, 6, 8, 20, 24, 30, 40, 60 or 20 to produce output frequencies of 200, 66, 33, 25,, 00, or 6. The single-ended LVCMOS outputs are divided into two banks of 4 low skew outputs each, for use in driving a microprocessor or microcontroller clock input as well as other system components. The 2 GHz PLL output frequency is also divided to produce a 25, 250 or 500 clock output for Rapid I/O applications such as found on the PowerQUICC III communications processor. The input reference, either crystal or external input is also buffered to a separate output that my be used as the clock source for a Gigabit Ethernet PHY if desired. The reference clock may be provided by either an external clock input of 25 or 33. An internal oscillator requiring a 25 crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal oscillator or external clock input is selected via the input pin of REF_SEL. Other than the crystal, no external components are required for crystal oscillator operation. The REF_33 configuration pins is used to select between a 33 and 25 input frequency. The is packaged in a 00 lead MAPBGA package to optimize both performance and board density. SCALE 2: VF SUFFIX VM SUFFIX (Pb-FREE) 00 MAPBGA PACKAGE CASE DATA SHEET IDT Freescale Motorola, Timing Inc. Solutions 2004 Organization has been For acquired More Information by Integrated Device On This Technology, Product, Inc
2 CLK PCLK PCLK REF_CLK_SEL XTAL_IN XTAL_OUT REF_SEL 0 OSC 0 Ref PLL N QA0 QA QA2 QA3 PLL_BYPASS REF_33 N QB0 QB CLK_A[0:5] CLK_B[0:5] RIO_C[0:] MR Figure. Logic Diagram 4, 8, 6, 40 Table. Pin Configurations Pin I/O Type Function Supply Active/State CLK Input LVCMOS PLL Reference Clock Input (pull-down) V DD PCLK, PCLK Input LVPECL PLL Reference Clock Input (PCLK - pull-down, PCLK - pull-up and V DD pull-down) QA0, QA, QA2, QA3 Output LVCMOS Bank A Outputs V DDOA QB0, QB, QB2, QB3 Output LVCMOS Bank B Outputs V DDOB QC0, QC, QC0, QC Output LVDS Bank C Outputs V DDOC REF_OUT Output LVCMOS Reference Output (25 or 33 ) V DD XTAL_IN Input LVCMOS Crystal Oscillator Input Pin V DD XTAL_OUT Output LVCMOS Crystal Oscillator Output Pin V DD REF_CLK_SEL Input LVCMOS Select between CLK and PCLK Input (pull-down) V DD High REF_SEL Input LVCMOS Select between External Input and Crystal Oscillator Input (pull-down) V DD High REF_33 Input LVCMOS Selects 33 Input (pull-down) V DD High MR Input LVCMOS Master Reset (pull-up) V DD Low PLL_BYPASS Input LVCMOS Select PLL or static test mode (pull-down) V DD High CLK_A[0:5] Input LVCMOS Configures Bank A clock output frequency (pull-up) V DD High CLK_B[0:5] 2 Input LVCMOS Configures Bank B clock output frequency (pull-up) V DD High RIO_C [0:] Input LVCMOS Configures Bank C clock output frequency (pull-down) V DD V DD 3.3 V Supply V DDA Analog Supply V DDOA Supply for Output Bank A V DDOB Supply for Output Bank B GND Ground. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb) 2. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb) PowerPC bit ordering (bit 0 = msb, bit = lsb) QB2 QB3 QC0 QC0 QC QC REF_OUT IDT TIMING SOLUTIONS 2 MOTOROLA 2
3 Table 2. Function Table Control Default 0 REF_CLK_SEL 0 CLK PCLK REF_SEL 0 CLK or PCLK XTAL PLL_BYPASS 0 Normal Bypass REF_33 0 Selects 25 Reference Selects 33 Reference MR Reset Normal CLK_A, CLK_B, and RIO_C control output frequencies. See Table 3 and Table 4 for specific device configuration Table 3. Output Configurations (Banks A & B) CLK_x[0:5] CLK_x[0] (msb). PowerPC bit ordering (bit 0 = msb, bit 5 = lsb) 2. Minimum value for N CLK_x[] CLK_x[2] CLK_x[3] CLK_x[4] CLK_x[5] (lsb) N Frequency () Table 4. Output Configurations (Bank C) RIO_C[0:] Frequency () (test output) IDT MOTOROLA 3 TIMING SOLUTIONS 3
4 OPERATION INFORMATION Output Frequency Configuration The was designed to provide the commonly used frequencies in PowerQUICC, PowerPC and other microprocessor systems. Table 3 lists the configuration values that will generate those common frequencies. The can generate numerous other frequencies that may be useful in specific applications. The output frequency (f out ) of either Bank A or Bank B may be calculated by the following equation. f out = 2000 / N where f out is in and N = 2 * CLK_x[0:5] This calculation is valid for all values of N from 8 to 26. Note that N = 5 is a modified case of the configuration inputs CLK_x[0:5]. To achieve N = 5 CLK_x[0:5] is configured to 00 or 7. Crystal Input Operation TBD Power-Up and MR Operation Figure 2 defines the release time and the minimum pulse length for MR pin. The MR release time is based upon the power supply being stable and within V DD specifications. See Table for actual parameter values. The may be configured after release of reset and the outputs will be stable for use after lock indication is obtained. Power Supply Bypassing The is a mixed analog/digital product. The architecture of the supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all V DD pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. V DD MR t reset_rel Figure 2. MR Operation V DD t reset_pulse V DD 22 µf 0. µf 5 Ω V DDA 0. µf Figure 3. V CC Power Supply Bypass IDT TIMING SOLUTIONS 4 MOTOROLA 4
5 Table 5. Absolute Maximum Ratings Symbol Characteristics Min Max Unit Condition V DD Supply Voltage (core) V V DDA Supply Voltage (Analog Supply Voltage) 0.3 V DD V V DDOx Supply Voltage (LVCMOS output for Bank A or B) 0.3 V DD V V IN DC Input Voltage 0.3 V DD +0.3 V V OUT DC Output Voltage V DDx +0.3 V I IN DC Input Current ±20 ma I OUT DC Output Current ±50 ma T S Storage Temperature C. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. 2. V DDx references power supply pin associated with specific output pin. Table 6. General Specifications V TT Output Termination Voltage V DD 2 V MM ESD Protection (Machine Model) 25 V HBM ESD Protection (Human Body Model) 2000 V CDM ESD Protection (Charged Device Model) 500 V LU Latch-Up Immunity 00 ma C IN Input Capacitance 4 pf Inputs C PD Power Dissipation Capacitance 0 pf Per Output θ JA Thermal Resistance (junction-to-ambient) 54.5 C/W Air flow = 0 T A Ambient Temperature C Table 7. DC Characteristics (T A = 40 C to 85 C) Supply Current for V DD = 3.3 V ± 5%, V DDOA = 3.3 V ± 5 and V DDOB = 3.3 V ± 5% I DD + I DDA Maximum Quiescent Supply Current (Core) 200 ma V DD + V DDA pins I DDA Maximum Quiescent Supply Current (Analog Supply) 5 ma V DDIN pins I DDOA, I DDOB Maximum Bank A and B Supply Current 75 ma V DDOA and V DDOB pins Supply Current for V DD = 3.3 V ± 5%, V DDOA = 2.5 V ± 5% and V DDOB = 2.5 V ± 5% I DD + I DDA Maximum Quiescent Supply Current (Core) 200 ma V DD + V DDA pins I DDA Maximum Quiescent Supply Current (Analog Supply) 5 ma V DDIN pins I DDOA, I DDOB Maximum Bank A and B Supply Current 00 ma V DDOA and V DDOB pins IDT MOTOROLA 5 TIMING SOLUTIONS 5
6 Table 8. LVDS DC Characteristics (T A = 40 C to 85 C) Differential LVDS Clock Outputs (QC0, QC0 and QC, QC) for V DD = 3.3 V ± 5% V PP Output Differential Voltage (peak-to-peak) (LVDS) mv V OS Output Offset Voltage (LVDS) mv. V PP is the minimum differential input voltage swing required to maintain AC characteristics including t PD and device-to-device skew. Table 9. LVPECL DC Characteristics (T A = 40 C to 85 C) Differential LVPECL Clock Inputs (CLK, CLK) for V DD = 3.3 V ± 0.5% V PP Differential Voltage 2 (peak-to-peak) (LVPECL) 250 mv V CMR Differential Input Crosspoint Voltage 3 (LVPECL).0 V DD 0.6 V. AC characteristics are design targets and pending characterization. 2. V PP is the minimum differential input voltage swing required to maintain AC characteristics including t PD and device-to-device skew. 3. V CMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V CMR (AC) range and the input swing lies within the V PP (AC) specification. Violation of V CMR (AC) or V PP (AC) impacts the device propagation delay, device and part-to-part skew. Table 0. LVCMOS I/O DC Characteristics (T A = 40 C to 85 C) LVCMOS for V DD = 3.3 V ± 5% V IH Input High Voltage 2.0 V DD V LVCMOS V IL Input Low Voltage 0.8 V LVCMOS I IN Input Current ± 200 µa V IN = V DDL or GND LVCMOS for V DD = 3.3 V ±5%, V DDOA = 3.3 V ± 5 and V DDOB = 3.3 V ± 5% V OH Output High Voltage 2.4 V I OH = 24 ma V OL Output Low Voltage 0.5 V I OL = 24 ma Z OUT Output Impedance 4 7 Ω LVCMOS for V DD = 3.3 V ±5%, V DDOA = 2.5 V ± 5% and V DDOB = 2.5 V ± 5% V OH Output High Voltage.9 V I OH = 5 ma V OL Output Low Voltage 0.4 V I OL = 5 ma Z OUT Output Impedance 8 22 Ω. Inputs have pull-down resistors affecting the input current. IDT TIMING SOLUTIONS 6 MOTOROLA 6
7 Table. AC Characteristics (V DD = 3.3 V ± 5%, V DDOA = 3.3 V ± 5%,V DDOB = 3.3 V ± 5%, T A = 40 C to +85 C) 2 Input and Output Timing Specification f ref Input Reference Frequency (25 input) Input Reference Frequency (33 input) XTAL Input Input Reference Frequency in PLL Bypass Mode PLL bypass f VCO VCO Frequency Range f MCX Output Frequency Bank A output Bank B output Bank C output AC characteristics are design targets and pending characterization. 2. AC characteristics apply for parallel output termination of 50Ω to V TT. 3. In bypass mode, the divides the input reference clock. 4. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: f ref = (f VCO M) N PLL locked f refpw Reference Input Pulse Width 2 ns f refccc Input Frequency Accuracy 00 ppm t r, t f Output Rise/Fall Time ns 20% to 80% DC Output Duty Cycle PLL Specifications % Bank A and B Bank C t LOCK Maximum PLL Lock Time 0 ms t reset_ref MR Hold Time on Power Up 0 ns t reset_pulse MR Hold Time 0 ns Skew and Jitter Specifications t sk(o) Output-to-Output Skew (within a bank) 50 ps t sk(o) Output-to-Output Skew (across banks A and B) 400 ps V DDOA = 3.3 V V DDOB = 3.3 V t JIT(CC) Cycle-to-Cycle Jitter ps ps Bank A and B Bank C t JIT(PER) Period Jitter 200 ps Bank A and C t JIT( ) I/O Phase Jitter RMS ( σ) 50 ps Bank A and C Pulse Generator Z = 50Ω Z O = 50Ω R T = 50Ω DUT Z O = 50Ω R T = 00Ω V TT Figure 4. AC Test Reference (LVDS Outputs) Pulse Generator Z = 50Ω Z O = 50Ω Z O = 50Ω R T = 50Ω DUT R T = 50Ω V TT Figure 5. AC Test Reference (LVCMOS Outputs) V TT IDT MOTOROLA 7 TIMING SOLUTIONS 7
8 Table 2. Pin Diagram (Top View) A V DDOB V DDOB CLKA[] CLKA[3] CLKA[5] V DD QA QA2 V DDOB V DDOB B V DDOB V DDOB CLKA[0] CLKA[2] CLKA[4] QA0 V DD QA3 V DDOB V DDOB C RSVD RSVD V DD V DD V DD V DD V DD V DD V DD REF_OUT D V DDA V DDA V DD GND GND GND GND V DD QC0 QC0 E REF_SEL CLK V DD GND GND GND GND V DD V DD GND F PCLK PCLK V DD GND GND GND GND V DD QC QC G REF_CLK_SEL REF_33 V DD GND GND GND GND V DD PLL_BYPASS MR H XTAL_IN XTAL_OUT V DD V DD V DD V DD V DD V DD RIO_C[] RIO_C[0] J V DDOB V DDOB CLKB[0] CLKB[2] CLKB[4] QB0 V DDOB QB3 V DDOB V DDOB K V DDOB V DDOB CLKB[] CLKB[3] CLKB[5] V DDOB QB QB2 V DDOB V DDOB Table 3. Pin List Signal 00 Pin MAPBGA Signal 00 Pin MAPBGA Signal 00 Pin MAPBGA Signal 00 Pin MAPBGA Signal 00 Pin MAPBGA V DDOB A RSVD C REF_SEL E REF_CLK_SEL G V DDOB J V DDOB A2 RSVD C2 CLK E2 REF_33 G2 V DDOB J2 CLKA[] A3 V DD C3 V DD E3 V DD G3 CLKB[0] J3 CLKA[3] A4 V DD C4 GND E4 GND G4 CLKB[2] J4 CLKA[5] A5 V DD C5 GND E5 GND G5 CLKB[4] J5 V DD A6 V DD C6 GND E6 GND G6 QB0 J6 QA A7 V DD C7 GND E7 GND G7 V DDOB J7 QA2 A8 V DD C8 V DD E8 V DD G8 QB3 J8 V DDOB A9 V DD C9 V DD E9 PLL_BYPASS G9 V DDOB J9 V DDOB A0 REF_OUT C0 GND E0 MR G0 V DDOB J0 V DDOB B V DDA D PCLK F XTAL_IN H V DDOB K V DDOB B2 V DDA D2 PCLK F2 XTAL_OUT H2 V DDOB K2 CLKA[0] B3 V DD D3 V DD F3 V DD H3 CLKB[] K3 CLKA[2] B4 GND D4 GND F4 V DD H4 CLKB[3] K4 CLKA[4] B5 GND D5 GND F5 V DD H5 CLKB[5] K5 QA0 B6 GND D6 GND F6 V DD H6 V DD K6 V DDOA B7 GND D7 GND F7 V DD H7 QB K7 QA3 B8 V DD D8 V DD F8 V DD H8 QB2 K8 V DDOB B9 QC0 D9 QC F9 RIO_C[] H9 V DDOB K9 V DDOB B0 QC0 D0 QC F0 RIO_C[0] H0 V DDOB K0 IDT TIMING SOLUTIONS 8 MOTOROLA 8
9 OUTLINE DIMENSIONS VF SUFFIX 00 MAP PBGA PACKAGE CASE ISSUE O A INDEX AREA B C K K J H G F E D C B A TOP VIEW 2 A INDEX AREA 9X BOTTOM VIEW 4X X 9X M A B C 0.0 M A CASE ISSUE O SIDE VIEW (.8).7 MAX NOTES:. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y4.5M, MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGING. 4 A SEATING PLANE DETAIL K ROTATED 90 CLOCKWISE 5 00X 0.2 A 0.35 A DATE /26/02 IDT TIMING SOLUTIONS 9 MOTOROLA 9
10 PART MPC92459 NUMBERS INSERT 900 Clock Generator PRODUCT Low Voltage for NAME PowerQUICC LVDS AND Clock DOCUMENT III Synthesizer TITLE Innovate with IDT and accelerate your future networks. Contact: For Sales Fax: For Tech Support Corporate Headquarters Integrated Device Technology, Inc Silver Creek Valley Road San Jose, CA 9538 United States (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (997) Pte. Ltd. Reg. No G 435 Orchard Road #20-03 Wisma Atria Singapore Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA XX-XXXX-XXXXX
Distributed by: www.jameco.com -800-83-4242 The content and copyrights of the attached material are the property of its owner. Freescale Semiconductor Technical Data The is a PLL based clock generator
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