3.3 VOLT FRAME RATE COMMUNICATIONS PLL MK1574. Features. Description. Block Diagram DATASHEET
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1 DATASHEET 3.3 VOLT FRAME RATE COMMUNICATIONS PLL MK1574 Description The MK1574 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 khz clock input as a reference, and generates many popular communications frequencies. All outputs are frequency locked together and to the input. This allows for the generation of locked clocks to the 8 khz backplane clock, simplifying clock generation and distribution in communications systems. ICS manufactures the largest variety of clock generators and buffers, and can customize this device for a variety of frequencies. Features 3.3 volt operation Packaged in 16-pin SOIC Accepts 8 khz input clock Output clock rates include T1, E1, T2, E2 Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges Available in Pb (lead) free package For jitter attenuation, use the MK2049 For 5.0 V operation, use the MK A Block Diagram VDD 2 GND 2 CLK1 FS khz input clock Input Buffer PLL Clock Synthesis and Control Circuitry CLK2 CLK3 8 khz (recovered) CAP1 CAP2 IDT / ICS 3.3 VOLT FRAME RATE COMMUNICATIONS PLL 1 MK1574 REV F
2 Pin Assignment ICLK 1 16 FS3 VDD 2 15 NC VDD 3 14 FS2 CAP FS1 GND 5 12 CLK3 CAP CLK2 GND 7 10 CLK1 FS KOUT Output Clocks Decoding Table Decode Address ICLK Multiplier CLK1 CLK2 CLK3 FS3:0 (Hex) pin1 On-chip pin 10 pin 11 pin Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved khz khz khz khz khz khz A 8.00 khz B 8.00 khz C 8.00 khz D 8.00 khz E 8.00 khz F 8.00 khz = connect directly to ground, 1 = connect directly to VDD. IDT / ICS 3.3 VOLT FRAME RATE COMMUNICATIONS PLL 2 MK1574 REV F
3 Pin Descriptions Pin Number Pin Name Pin Type External Components Pin Description 1 ICLK Input Clock input. Connect to an 8 khz clock input. 2 VDD Power Connect to 3.3 V. 3 VDD Power Connect to 3.3 V. 4 CAP1 Input Connect to a ceramic capacitor and a resistor in series between this pin and CAP2. Refer to the section Loop Bandwidth and Loop Filter Component Selection. 5 GND Power Connect to ground. 6 CAP2 Power Connect to a ceramic capacitor and a resistor in series between this pin and CAP1. Refer to the section Loop Bandwidth and Loop Filter Component Selection. 7 GND Power Connect to ground. 8 FS0 Input Frequency select 0. Determines CLK outputs per table above. 9 8KOUT Output Recovered 8 khz output clock. Can be low jitter, better duty cycle than clock input. 10 CLK1 Output Clock 1 determined by status of FS3:0 per table above. 11 CLK2 Output Clock 2 determined by status of FS3:0 per table above. 12 CLK3 Output Clock 3 determined by status of FS3:0 per table above. 13 FS1 Input Frequency select 1. Determines CLK outputs per table above. 14 FS2 Input Frequency select 2. Determines CLK outputs per table above. 15 NC No connect. Do not connect anything to this pin. 16 FS3 Input Frequency select 3. Determines CLK outputs per table above. The MK1574 requires a minimum number of external components for proper operation. An RC network (see the section Loop Bandwidth and Loop Filter Component Selection ) should be connected between CAP1 and CAP2 as close tot he device as possible. Decoupling capacitors of 0.01µF should be connected between VDD and GND on pins 2, 3, 5 and 7, as close to the device as possible. A series termination resistor of 33Ω may be used close to each clock output pin to reduce reflections. IDT / ICS 3.3 VOLT FRAME RATE COMMUNICATIONS PLL 3 MK1574 REV F
4 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK1574. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Supply Voltage, VDD (referenced to GND) -0.5 V to 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial) 0 to +70 C Ambient Operating Temperature (industrial) -40 to +85 C Storage Temperature -65 to +150 C Junction Temperature 150 C Soldering Temperature 260 C Recommended Operation Conditions DC Electrical Characteristics Rating Parameter Min. Typ. Max. Units Ambient Operating Temperature (commercial) C Ambient Operating Temperature (industrial) C Power Supply Voltage (measured in respect to GND) V VDD = 3.3 V, Ambient temperature 0 to +70 C, unless stated otherwise Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD V Input High Voltage V IH 2 V Input Low Voltage V IL 0.8 V Output High Voltage V OH I OH = -4 ma VDD-0.4 V Output High Voltage V OH I OH = -25 ma 2.4 V Output Low Voltage V OL I OL = 25 ma 0.4 V Operating Supply IDD No Load 13 ma Current Short Circuit Current I OS Each output ±100 ma Input Capacitance C IN 7 pf IDT / ICS 3.3 VOLT FRAME RATE COMMUNICATIONS PLL 4 MK1574 REV F
5 AC Electrical Characteristics VDD = 3.3 V, Ambient Temperature 0 to +70 C, unless stated otherwise Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency f IN khz Output Clock Rise Time t OR 0.8 to 2.0 V 1.5 ns Output Clock Fall Time t OF 2.0 to 0.8 V 1.5 ns Output Clock Duty Cycle, t DC At VDD/ to % High time Absolute Clock Period 1 ns Jitter Actual Mean Frequency Any clock selection 0 0 ppm Error Versus Target (note 1) Note 1: All multipliers as shown in the table on page two are exact, and are stored in ROM on the chip. Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to θ JA Still air 120 C/W Ambient θ JA 1 m/s air flow 115 C/W θ JA 3 m/s air flow 105 C/W Thermal Resistance Junction to Case θ JC 58 C/W Loop Bandwidth and Loop Filter Component Selection The series-connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a high quality ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. The series connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a high quality ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. Ceramic capacitors should have C0G or NP0 dielectric. Avoid high-k dielectrics like Z5U and X7R; these and other ceramics which have piezoelectric properties allow mechanical vibration in the system to increase the output jitter because the mechanical energy is converted directly to voltage noise on the VCO input. The values of the RC network determine the bandwidth of the PLL. The values of the loop filter components are calculated using the constants K1 and K2 from the Loop Filter Constants table (page 7). The loop bandwidth is set by the capacitor C and the constant K1 using the formula: BW (Hz) = K1 C Equation 1 IDT / ICS 3.3 VOLT FRAME RATE COMMUNICATIONS PLL 5 MK1574 REV F
6 The loop damping is set by the resistor R, the capacitor C, and the constant K2 using the formula:: R = ζ * K2 C For example, to design the loop filter whewn generating MHz from 8 khz: 1. From the Output Clock Decoding table (page 2), the address is E. The Loop Filter Constants table (page 7) shows the constants K1 = and K2 = A good value for the loop bandwidth is 1/20 the input frequency; where 8 khz/20 = 400 Hz. Using equation 1, 400 = K1 C Therefore, Equation 2; ζ (zeta) is the damping factor ( ) 2 C = = 16.6 nf (16 nf nearest standard value A good value for the damping factor ζ is From equation 2, R = * E-9 = 34.7 kω (36 kω nearest standard value) IDT / ICS 3.3 VOLT FRAME RATE COMMUNICATIONS PLL 6 MK1574 REV F
7 Loop Filter Constants This table shows the constants K1 and K2 that are used with the equations on page 6 to calculate the external loop filter components. Loop Filter Contstants for MK Decode Address Loop Filter Constants FS3:0 (Hex) K1 K Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved A B C D E F PC Board Layout A proper board layout is critical to the successful use of the MK1574. In particular, the CAP1 and CAP2 pins are very sensitive to noise and leakage (CAP1 at pin 4 is the most sensitive). Traces must be as short as possible and the capacitor and resistor must be mounted next to the device as shown to the right. The capacitor connected between pins 3 and 5 is the power supply decoupling capacitor. The high frequency output clocks on may benefit from a series 33Ω resistor connected close to the pin (not shown). IDT / ICS 3.3 VOLT FRAME RATE COMMUNICATIONS PLL 7 MK1574 REV F
8 Clock Multipliers/Accuracies In the table on page 2 are the actual multipliers stored in the MK1574 ROM, which yield the exact values shown for the output clocks. Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No Millimeters Inches INDEX AREA 1 2 D E H Symbol Min Max Min Max A A B C D E e 1.27 BASIC BASIC H h L α A h x 45 A1 - C - C e B SEATING PLANE.10 (.004) C L IDT / ICS 3.3 VOLT FRAME RATE COMMUNICATIONS PLL 8 MK1574 REV F
9 Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature MK S MK S Tubes 16-pin SOIC 0 to +70 C MK STR MK S Tape and Reel 16-pin SOIC 0 to +70 C MK SLF MK SLF Tubes 16-pin SOIC 0 to +70 C MK SLFTR MK SLF Tape and Reel 16-pin SOIC 0 to +70 C MK SI MK SI Tubes 16-pin SOIC -40 to +85 C MK SITR MK SI Tape and Reel 16-pin SOIC -40 to +85 C MK SILF MK SILF Tubes 16-pin SOIC -40 to +85 C MK SILFTR MK SILF Tape and Reel 16-pin SOIC -40 to +85 C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. IDT / ICS 3.3 VOLT FRAME RATE COMMUNICATIONS PLL 9 MK1574 REV F
10 Innovate with IDT and accelerate your future networks. Contact: For Sales Fax: For Tech Support <product line > <product line phone> Corporate Headquarters Integrated Device Technology, Inc Silver Creek Valley Road San Jose, CA United States (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No G 435 Orchard Road #20-03 Wisma Atria Singapore Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA
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DATASHEET ICS2059-02 Description The ICS2059-02 is a VCXO (Voltage Controlled Crystal Oscillator) based clock multiplier and jitter attenuator designed for system clock distribution applications. This
ICS83032I 75MHZ, 3 RD OVERTONE OSCILLATOR W/DUAL LVCMOS/LVTTL OUTPUTS. 75MHZ, 3RD OVERTONE Integrated OSCILLATOR W/DUAL ICS83032I
75MHZ, 3RD OVERTONE OSCILLATOR W/DUAL LVCMOS/LVTTL Systems, OUTPUTS Inc. DATA SHEET GENERAL DESCRIPTION The is a SAS/SATA dual output ICS LVCMOS/LVTTL oscillator and a member of the HiPerClockS HiperClocks
MK AMD GEODE GX2 CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET MK1491-09 Description The MK1491-09 is a low-cost, low-jitter, high-performance clock synthesizer for AMD s Geode-based computer and portable appliance applications. Using patented analog Phased-Locked
2 TO 4 DIFFERENTIAL CLOCK MUX ICS Features
DATASHEET 2 TO 4 DIFFERENTIAL CLOCK MUX ICS557-06 Description The ICS557-06 is a two to four differential clock mux designed for use in PCI-Express applications. The device selects one of the two differential
ICS2304NZ-1 LOW SKEW PCI/PCI-X BUFFER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS2304NZ-1 Description The ICS2304NZ-1 is a high-performance, low skew, low jitter PCI/PCI-X clock driver. It is designed to distribute high-speed signals in PCI/PCI-X applications operating
ICS LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER. Features. Description. Block Diagram INA INB SELA
BUFFER Description The ICS552-02 is a low skew, single-input to eightoutput clock buffer. The device offers a dual input with pin select for glitch-free switching between two clock sources. It is part
CLOCK DISTRIBUTION CIRCUIT. Features
DATASHEET CLCK DISTRIBUTIN CIRCUIT IDT6P30006A Description The IDT6P30006A is a low-power, eight output clock distribution circuit. The device takes a TCX or LVCMS input and generates eight high-quality
1:2 LVCMOS/LVTTL-to-LVCMOS/LVTTL Zero Delay Buffer for Audio
1: LVCMOS/LVTTL-to-LVCMOS/LVTTL Zero Delay Buffer for Audio ICS8700-05 DATA SHEET General Description The ICS8700-05 is a 1: LVCMOS/LVTTL low phase ICS noise Zero Delay Buffer and is optimized for audio
Addr FS2:0. Addr FS2:0
DATASHEET Description The MK1575-01 is a clock recovery Phase-Locked Loop (PLL) designed for clock synthesis and synchronization in cost sensitive applications. The device is optimized to accept a low-frequency
PT7C4511. PLL Clock Multiplier. Features. Description. Pin Configuration. Pin Description
Features Zero ppm multiplication error Input crystal frequency of 5-30 MHz Input clock frequency of - 50 MHz Output clock frequencies up to 200 MHz Peak to Peak Jitter less than 200ps over 200ns interval
ICS83021I. Features. General Description. Pin Assignment. Block Diagram 1-TO-1 DIFFERENTIAL- TO-LVCMOS/LVTTL TRANSLATOR
1-TO-1 DIFFERENTIAL- TO-LVCMOS/LVTTL TRANSLATOR General Description The is a 1-to-1 Differential-to-LVCMOS/ ICS LVTTL Translator and a member of the HiPerClockS HiPerClockS family of High Performance Clock
Advance Information Clock Generator for PowerQUICC III
Freescale Semiconductor Technical Data Advance Information The is a PLL based clock generator specifically designed for Freescale Microprocessor and Microcontroller applications including the PowerPC and
Description. This Clock Multiplier is the most cost-effective way to Input crystal frequency of 5-40 MHz
PT7C4512 Features Description Zero ppm multiplication error This Clock Multiplier is the most cost-effective way to Input crystal frequency of 5-40 MHz generate a high quality, high frequency clock outputs
ICS9P936. Low Skew Dual Bank DDR I/II Fan-out Buffer DATASHEET. Description. Pin Configuration
DATASHEET Description Dual DDR I/II fanout buffer for VIA Chipset Output Features Low skew, fanout buffer SMBus for functional and output control Single bank 1-6 differential clock distribution 1 pair
ICS83056I-01. General Description. Features. Block Diagram. Pin Assignment 6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER ICS83056I-01
ICS83056I-01 General Description The ICS83056I-01 is a 6-bit, :1, Single-ended ICS LVCMOS Multiplexer and a member of the HiPerClockS HiPerClockS family of High Performance Clock Solutions from IDT. The
ICS507-01/02 PECL Clock Synthesizer
Description The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz (or other high speed) differential PECL clock output from a low frequency crystal input. Using Phase-Locked-
FEATURES 2:1 single-ended multiplexer Q nominal output impedance: 15Ω (V DDO BLOCK DIAGRAM PIN ASSIGNMENT 2:1, SINGLE-ENDED MULTIPLEXER ICS83052I
ICS8305I GENERAL DESCRIPTION The ICS8305I is a low skew, :1, Single-ended ICS Multiplexer and a member of the HiPerClockS family of High Performance Clock Solutions from IDT HiPerClockS The ICS8305I has
FemtoClock Crystal-to-LVDS Clock Generator
FemtoClock Crystal-to-LDS Clock Generator 844021-01 DATA SHEET GENERAL DESCRIPTION The 844021-01 is an Ethernet Clock Generator. The 844021-01 uses an 18pF parallel resonant crystal over the range of 24.5MHz
Low-Cost Notebook EMI Reduction IC. Applications. Modulation. Phase Detector
Low-Cost Notebook EMI Reduction IC Features Provides up to 15dB of EMI suppression FCC approved method of EMI attenuation Generates a 1X low EMI spread spectrum clock of the input frequency Operates between
Clock Generator for PowerQUICC III
MOTOROLA SEMICONDUCTOR TECHNICAL DATA The is a PLL based clock generator specifically designed for Motorola Microprocessor And Microcontroller applications including the PowerQUICC III. This device generates
PT7C4502 PLL Clock Multiplier
Features Low cost frequency multiplier Zero ppm multiplication error Input crystal frequency of 5-30 MHz Input clock frequency of 4-50 MHz Output clock frequencies up to 180 MHz Period jitter 50ps (100~180MHz)
Features. Applications
PRELIMINARY DATASHEET IDTHS421V16 Description The IDTHS421V16 is a bi-directional, low power, Quad single-pole, double-throw (SPDT) hybrid switch targeted at dual SIM card multiplexing. It is optimized
IDT5V80001 MOST CLOCK INTERFACE. Description. Features. Block Diagram DATASHEET
DATASHEET IDT5V80001 Description The IDT5V80001 is a high performance clock interface for use in MOST (Media Oriented Systems Traport) enabled systems. It can be used in two modes: generating a master
3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE IDT23S05 FEATURES: Phase-Lock Loop Clock Distribution 10MHz to 133MHz operating frequency Distributes one clock input to one bank of five outputs
BLOCK DIAGRAM PIN ASSIGNMENTS. 8302I-01 Datasheet. Low Skew, 1-to-2 LVCMOS / LVTTL Fanout Buffer W/ Complementary Output
Low Skew, 1-to-2 LVCMOS / LVTTL Fanout Buffer W/ Complementary Output 8302I-01 Datasheet DESCRIPTION The 8302I-01 is a low skew, 1-to-2 LVCMOS/LVTTL Fanout Buffer w/complementary Output. The 8302I-01 has
Low Skew CMOS PLL Clock Drivers
Low Skew CMOS PLL Clock Drivers The MC88915 Clock Driver utilizes phase-locked loop technology to lock its low skew outputs' frequency and phase onto an input reference clock. It is designed to provide
Distributed by: www.jameco.com -800-83-4242 The content and copyrights of the attached material are the property of its owner. Freescale Semiconductor Technical Data The is a PLL based clock generator
PI6C49X0204A. Low Skew 1 TO 4 Clock Buffer. Features. Description. Block Diagram. Pin Assignment
Features ÎÎLow skew outputs (250 ps) ÎÎPackaged in 8-pin SOIC ÎÎLow power CMOS technology ÎÎOperating Voltages of 1.5 V to 3.3 V ÎÎOutput Enable pin tri-states outputs ÎÎ3.6 V tolerant input clock ÎÎIndustrial
Low-Jitter, 8kHz Reference Clock Synthesizer Outputs MHz
19-3530; Rev 0; 1/05 Low-Jitter, 8kHz Reference General Description The low-cost, high-performance clock synthesizer with an 8kHz input reference clock provides six buffered LVTTL clock outputs at 35.328MHz.
ICS Glitch-Free Clock Multiplexer
Description The ICS580-01 is a clock multiplexer (mux) designed to switch between 2 clock sources with no glitches or short pulses. The operation of the mux is controlled by an input pin but the part can
Features. 1 CE Input Pullup
CMOS Oscillator MM8202 PRELIMINARY DATA SHEET General Desription Features Using the IDT CMOS Oscillator technology, originally developed by Mobius Microsystems, the MM8202 replaces quartz crystal based
3.3V ZERO DELAY CLOCK MULTIPLIER
3.3V ZERO DELAY CLOCK MULTIPLIER IDT2308 FEATURES: Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 1 operating frequency Distributes one clock input to two banks of four outputs
Features. Applications
DATASHEET IDTHS221P10 Description The IDTHS221P10 is a high-performance hybrid switch device, combined with hybrid low distortion audio and USB 2.0 high speed data (480 Mbps) signal switches, and analog
ICS Pin Configuration. Features/Benefits. Specifications. Block Diagram DATASHEET LOW EMI, SPREAD MODULATING, CLOCK GENERATOR.
DATASHEET LW EMI, SPREAD MDULATING, CLCK GENERATR ICS9730 Features/Benefits ICS9730 is a Spread Spectrum Clock targeted for Mobile PC and LCD panel applications that generates an EMI-optimized clock signal
ICS MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER 260MHZ, CRYSTAL-TO-LVCMOS ICS84021
DATA SHEET 260MHZ, CRYSTAL-TO-LCMOS LTTL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION The is a general purpose, Crystal-to- ICS LCMOS/LTTL High Frequency Synthesizer HiPerClockS and a member of the HiPerClockS
FemtoClock Crystal-to-3.3V LVPECL Clock Generator ICS843011C
FemtoClock Crystal-to-3.3V LVPECL Clock Generator ICS843011C DATA SHEET GENERAL DESCRIPTION The ICS843011C is a Fibre Channel Clock Generator. The ICS843011C uses a 26.5625MHz crystal to synthesize 106.25MHz