PI6C V Low Skew 1-to-4 LVTTL/LVCMOS to LVPECL Fanout Buffer. Description. Features. Block Diagram. Pin Configuration

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1 Features Maximum operation frequency: 500 MHz 4 pair of differential LVPECL outputs Selectable CLK 0 and inputs CLK 0, accept LVCMOS, LVTTL input level Output Skew: 80ps (maximum) Part-to-part skew: 50ps (maximum) Propagation delay:.9ns (maximum) 3.3V power supply Additive jitter of 36.7fs (typical) Operating Temperature: -40 o C to 85 o C Packaging (Pb-free & Green available): 20-pin TSSOP (L) Description The PI6C is a high-performance low-skew LVPECL fanout buffer. PI6C features two selectable single-ended clock inputs and translates to four LVPECL outputs. The CLK 0 and inputs accept LVCMOS or LVTTL signals. The outputs are synchronized with input clock during asynchronous assertion/ deassertion of pin. PI6C is ideal for singleended LVTTL/LVCMOS to LVPECL translations. Typical clock translation and distribution applications are data-communications and telecommunications. Block Diagram Pin Configuration D LE Q V EE Q 0 NQ 0 CLK 0 Q 0 nq 0 Q nq CLK Q NQ Q 2 NQ 2 Q 2 nq Q 3 NQ 3 Q 3 nq 3 PS8735A 03/25/

2 Pin Description Name Pin # Type Description V EE P Connect to Negative power supply 2 I_PU 3 I_PD CLK 0 4 I_PD LVCMOS / LVTTL clock input 6 I_PD LVCMOS / LVTTL clock input 5, 7, 8, 9 No internal connection. 0, 3, 8 P Synchronizing clock enable. When high, clock outputs follow clock input. When low, Qx outputs are forced low, nqx outputs are forced high. LVCMOS/LVTTL level with 50KΩ pull up. Clock select input. When high, selects input. When low, selects CLK 0 input. LVCMOS/LVTTL level with 50KΩ pull down. Connect to 3.3V. Q 3, n Q 3, 2 O Differential output pair, LVPECL interface level. Q 2, n Q 2 4, 5 O Differential output pair, LVPECL interface level. Q, n Q 6, 7 O Differential output pair, LVPECL interface level. Q 0, n Q 0 9, 20 O Differential output pair, LVPECL interface level.. I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up. Pin Characteristics C IN Input Capacitance 4 pf R_pullup Input Pullup Resistance 50 R_pulldown Input Pulldown Resistance 50 KΩ Control Input Function Table Inputs Outputs Selected Source Q 0 :Q 3 n Q 0 : n Q CLK 0 Diasbled: Low Diasbled: High 0 Disabled: Low Disabled: High 0 CLK 0 Enabled Enabled Enabled Enabled. After switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below. 2 PS8735A 03/25/

3 Figure. Timing Diagram Disabled Enabled CLK 0 nq0:nq3 Q0:Q3 Clock Input Function Table Inputs Outputs CLK 0 or Q 0 :Q 3 n Q 0 : n Q 3 0 LOW HIGH HIGH LOW Absolute Maximum Ratings Supply voltage Referenced to GND 4.6 V IN Input voltage Referenced to GND V V OUT Output voltage Referenced to GND V T STG Storage temperature o C. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress speci fications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. V Operating Conditions Power Supply Voltage V T A Ambient Temperature o C I EE Power Supply Current 500 MHz 60 ma 3 PS8735A 03/25/

4 LVCMOS/LVTTL DC Characteristics (T A = -40 o C to 85 o C, = 3.0V to 3.6V unless otherwise stated below.) V IH V IL I IH I IL Input High Voltage Input Low Voltage Input High Current Input Low Current CLK 0,,, V CLK 0, V, V CLK0, CLK, V IN = = 3.6V 50 ua V IN = = 3.6V 5 ua CLK 0,, V IN = 0V, = 3.6V -5 ua V IN = 0V, = 3.6V -50 ua LVPECL DC Characteristics (T A = -40 o C to 85 o C, = 3.0V to 3.6V unless otherwise stated below.) V OH Output High Voltage () V OL Output Low Voltage () V V SWING Peak-to-peak Output Voltage Swing Outputs terminated with 50Ω to -2.0V AC Characteristics (T A = -40 o C to 85 o C, = 3.0V to 3.6V) f max Output Frequency 500 MHz t Pd Propagation Delay ().0.9 ns T sk(o) Output-to-output Skew (2) 80 T sk(pp) Part-to-part Skew (3) 50 t r /t f Output Rise/Fall time 20% - 80% odc Output Duty Cycle % J add Additive Jitter At 55.25MHz over 2kHz to 20MHz ps 36.7 fs. Measured from the /2 of the input to the differential output crossing point 2. Defined as skew between outputs at the same supply voltage and with equal load condition. Measured at the outputs differential crossing point. 3. Defined as skew between outputs on different parts operating at the same supply voltage and with equal load condition. Measured at the outputs differential crossing point. 4. All parameters are measured at 500 MHz unless noted otherwise 4 PS8735A 03/25/

5 Packaging Mechanical: 20-Pin TSSOP (L) BSC Max SEATING PLANE Ordering Information Ordering Code Package Code Package Description PI6C LE L Pb-free & Green 20-pin 73-mil wide TSSOP Thermal characteristics can be found on the company web site at E = Pb-free & Green X suffix = Tape/Reel Pericom Semiconductor Corporation PS8735A 03/25/