Description Q0+ Q0- Q1+ Q1- Q2+ Q2- VDD Q3+ Q3- Q4+ Q4- CLK_SEL CLK0. nclk0 Q5+ Q5- SYNC_OE Q6+ Q6- CLK1. nclk1 Q7+ Q7- VEE Q8+ Q8- Q9+ Q9-
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- Leslie Chambers
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1 LVPECL Fanout Buffer with Sync OE Features ÎÎF MAX < 1.5GHz ÎÎ10 pairs of differential LVPECL/ ECL outputs ÎÎLow additive jitter, < 0.03ps (typ) ÎÎSelectable differential input pairs with single ended input option ÎÎInput CLK accepts: LVPECL, LVDS, CML, SSTL input level ÎÎOutput skew: 55ps (max) ÎÎOperating Temperature: -40 o C to 85 o C ÎÎECL mode operating voltage range V DD / V DDO = 0V, V EE = -3.6V to V ÎÎPower supply: 3.3V ±10% or 2.5V ±5% ÎÎPackaging (Pb-free & Green), 32-pin TQFP available Description The PI6C is a high-performance low-skew 1-to-10 LVPE- CL/ ECL fanout buffer. The PI6C features two selectable differential clock inputs and translates to ten LVPECL/ ECL outputs. The CLK inputs accept LVPECL, LVDS, CML and SSTL signals. PI6C is ideal for clock distribution applications such as providing fanout for low noise Pericom oscillators. Block Diagram Pin Configuration Q0+ Q0- Q1+ Q1- Q0+ Q1+ Q2+ Q0- Q1- Q2- CLK0 nclk0 CLK1 nclk1 0 1 Q2+ Q2- Q3+ Q3- Q4+ Q4- Q5+ Q5- VDD CLK_SEL CLK0 nclk Q3+ Q3- Q4+ Q4- Q5+ CLK_SEL D Q Q6+ Q6- Q7+ Q7- CLK1 nclk1 VEE Q6+ Q5- Q6- LE Q8+ Q8- Q9+ Q8+ Q9+ Q9- Q9- Q8- Q7- Q7+ 1 PI6C Rev C 10/09/2013
2 Pin Description Pin # Name Type Description 1 V DD Power Core Power Supply 2 CLK_SEL Input Clock select input. When high, selects CLK1 input. When low, selects CLK0 input. LVCMOS/LVTTL level with 50kΩ pull down. 3 CLK0 Input Differential clock input with pull-down 4 nclk0 Input Inverting differential clock input. Defaults to VDD/2 if left floating. 5 Input Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nq outputs are forced high. LVCMOS / LVTTL interface levels. 6 CLK1 Input Differential clock input with pull-down 7 nclk1 Input Inverting differential clock input. Defaults to V DD /2 if left floating. 8 V EE Power Connect to negative power supply 9, 16, 25, 32 V DDO Power Output Power pin 11, 10 Q9+, Q9- Output Differential output pair, LVPECL interface level. 13,12 Q8+, Q8- Output Differential output pair, LVPECL interface level. 15,14 Q7+, Q7- Output Differential output pair, LVPECL interface level. 18,17 Q6+, Q6- Output Differential output pair, LVPECL interface level. 20,19 Q5+, Q5- Output Differential output pair, LVPECL interface level. 22,21 Q4+, Q4- Output Differential output pair, LVPECL interface level. 24, 23 Q3+, Q3- Output Differential output pair, LVPECL interface level. 27,26 Q2+, Q2- Output Differential output pair, LVPECL interface level. 29,28 Q1+, Q1- Output Differential output pair, LVPECL interface level. 31,30 Q0+, Q0- Output Differential output pair, LVPECL interface level. CLK_SEL Input Function Table Inputs Outputs 0 CLK0 1 CLK1 2 PI6C Rev C 10/09/2013
3 nclk[0:1] CLK[0:1] Disabled Enabled Q[0:9]- Q[0:9]- Q[0:9]+ 1. Exact enable/ disable time shown above only valid for frequencies <200MHz. Clock Input Function Table CLK0 or CLK1 Inputs nclk0 or nclk1 Q[0:9]+ Outputs Input Function Table Input Outputs Q[0:9]+ Q[0:9]- 0 Disabled; LOW Disabled; HIGH 1 Enabled Enabled Input to Output Mode Polarity 0 1 LOW HIGH Differential to Differential Non Inverting 1 0 HIGH LOW Differential to Differential Non Inverting 0 Biased LOW HIGH Single Ended to Differential Non Inverting 1 Biased HIGH LOW Single Endded to Differential Non Inverting Biased 0 HIGH LOW Single Endded to Differential Inverting Biased 1 LOW HIGH Single Endded to Differential Inverting 3 PI6C Rev C 10/09/2013
4 Absolute Maximum Ratings (1) V DD Supply voltage Referenced to GND 4.6 V V IN Input voltage Referenced to GND -0.5 V DD +0.5V V IOUT Surge Current 100 ma T STG Storage temperature o C Note: 1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These ratings are stress specifications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Operating Conditions V DD V DDO Core Power Supply Voltage Output Power Supply Voltage V T A Ambient Temperature o C I DD Core Power Supply Current 90 I DDO Output Power Supply Current All LVPECL outputs unloaded 110 V ma LVCMOS/LVTTL DC Characteristics (TA = -40 o C to +85 o C, VDD = 3.3V ±10%, = 2.5V ±5% to 3.3V ±10%) V IH V IL I IH I IL Input High Voltage Input Low Voltage Input High Current Input Low Current 1.7 V DD V IN = V DD = 3.6V 150 μa V IN = 0V, V DD = 3.6V -150 μa V 4 PI6C Rev C 10/09/2013
5 LVPECL DC Characteristics (T A = -40 o C to +85 o C, V DD = 3.3V ±10%, V DDO = 2.5V ±5% to 3.3V ±10%) I IH Input High Current CLK0, CLK1 V IN = V DD = 3.6V 150 µa nclk0, nclk1 V IN = V DD = 3.6V 150 µa Input Low Current nclk0, nclk1 V DD = 3.6V, V IN = 0V -150 µa CLK0, CLK1 V DD = 3.6V, V IN = 0V -150 µa I IL V PP Peak-to-peak Voltage V V CMR Common Mode Input Voltage (1) V EE +0.5 V DD V V OH Output High Voltage (2) V DDO = 2.5V or 3.3V V DDO -1.4 V DDO -0.9 V V OL Output Low Voltage (2) V DDO = 2.5V or 3.3V V DDO -2.0 V DDO -1.7 V V SWING Peak-to-peak Output Voltage Swing V R Input Pullup/Pulldown Resistance 50 kω 1. For single-ended applications, the maximum input voltage for CLK and /CLK is V DD +0.3V 2. Outputs terminated with 50Ω to V DD -2.0V AC Characteristics (T A = -40 o C to +85 o C, V DD = 3.3V ±10%, V DDO = 2.5V ±5% to 3.3V ±10%) f max Output Frequency 1500 MHz t pd Propagation Delay (1) ps Tsk Output-to-output Skew (2) ps Tsk(p-p) Part-to-Part Skew (3) 250 ps t r /t f Output Rise/Fall time 20% - 80% 150 ps t odc Output duty cycle f 650 MHz % V PP t j Output Swing Buffer additive jitter RMS LVPECL outputs, f 650 MHz 1. Measured from the differential input to the differential output crossing point MHz with 12KHz to 20MHz integration range 400 mv 0.03 ps 2. Defined as skew between outputs at the same supply voltage and with equal loads. Measured at the output differential crossing point 3. This parameter is guaranteed by design 5 PI6C Rev C 10/09/2013
6 Configuration Test Load Board Termination for LVPECL outputs LVPECL Buffer V DDQx Z = 50Ω o L = 0 ~ 10 in. 100Ω Z = 50Ω o 150Ω 150Ω 6 PI6C Rev C 10/09/2013
7 Packaging Mechanical: 32-pin TQFP (FA) 9.00 BSC.354 Square DOCUMENT CONTROL NO. PD REVISION: C DATE: 03/09/05 1 Square BSC.276 Max REF mm GAUGE PLANE Seating Plane BSC X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS 1. Controlling dimensions in millimeters 2. Ref.: JEDEC MS-026D/ABA 3. Package Outline Exclusive of Mold Flash and Metal Burr Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA DESCRIPTION: 32-Pin, Thin Quad Flat Package, TQFP PACKAGE CODE: FA Ordering Information (1,2,3) Ordering Code Package Code Package Description PI6C FAIE FA Pb-free & Green, 32-pin TQFP 1. Thermal characteristics can be found on the company web site at 2. E = Pb-free & Green 3. X suffix = Tape/Reel Pericom Semiconductor Corporation PI6C Rev C 10/09/2013
2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux
2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux Features F MAX = 500MHz 10 pairs of differential LVPECL outputs Low additive jitter,
PI6C V/3.3V 1.5GHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux /Q4 /Q5 /Q6 /Q3
LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux Features ÎÎF MAX < 1.5GHz ÎÎ10 pairs of differential LVPECL outputs ÎÎLow additive jitter, < 0.03ps (typ) ÎÎSelectable differential input pairs
PI6C V Low Skew 1-to-4 LVTTL/LVCMOS to LVPECL Fanout Buffer. Description. Features. Block Diagram. Pin Configuration
Features Maximum operation frequency: 500 MHz 4 pair of differential LVPECL outputs Selectable CLK 0 and inputs CLK 0, accept LVCMOS, LVTTL input level Output Skew: 80ps (maximum) Part-to-part skew: 50ps
PI6C V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer. Description. Features. Block Diagram. Pin Diagram
Features Pin-to-pin compatible to ICS8533-01 Maximum operation frequency: 800MHz 4 pair of differential LVPECL outputs Selectable differential CLK and PCLK inputs CLK, n CLK pair accepts LVDS, LVPECL,
PI6C V/3.3V, 500 MHz Twelve 2-to-1 Differential LVPECL Clock Multiplexer. Description. Features. Block Diagram.
LVPECL Clock Multiplexer Features Pin-to-pin compatible to ICS85352I F MAX 500 MHz Propagation Delay < 4ns Output-to-output skew < 100ps 12 pairs of differential LVPECL outputs Selectable differential
PI6C B. 3.3V Low Jitter 1-to-4 Crystal/LVCMOS to LVPECL Fanout Buffer. Description. Features. Block Diagram. Pin Diagram
Features Maximum output frequency: 500MHz 4 pair of differential LPECL outputs Selectable and crystal inputs accepts LCMOS, LTTL input level Ultra low additive phase jitter: < 0.05 ps (typ) (differential
PI6C High Performance LVPECL Fanout Buffer. Features. Description. Applications. Pin Configuration (20-Pin TSSOP) Block Diagram
Features ÎÎ4 LVPECL outputs ÎÎUp to 1.5GHz output frequency ÎÎUltra low additive phase jitter: < 0.03 ps (typ) (differential 156.25MHz, 12KHz to 20MHz integration range) ÎÎTwo selectable inputs ÎÎLow delay
PI6C4511. PLL Clock Multiplier. Features. Description. Block Diagram. PLL Clock Synthesis and Control Circuit. Output Buffer. Crystal Oscillator
Features ÎÎZero ppm multiplication error ÎÎInput crystal frequency range: 5-30MHz ÎÎInput clock frequency range: 2-50MHz ÎÎOutput clock frequencies up to 200MHz ÎÎPeriod jitter 150ps ÎÎ9 selectable frequencies
PI6CL V/1.5V, 200MHz, 1:4 Networking Clock Buffer. Features. Description. Pin Description
Features High-speed, low-noise, non-inverting 1:4 buffer Maximum Frequency up to 200 MHz Low output skew < 100ps Low propagation delay < 3.5ns Optimized duty cycle 3.3 tolerent input 1.2 or 1.5 supply
Description. Applications
High Performance HCSL Fanout Buffer Features ÎÎ2 HCSL outputs ÎÎUp to 250MHz output frequency ÎÎUltra low additive phase jitter: < 0.1 ps (typ) ÎÎTwo selectable inputs ÎÎLow delay from input to output
PI6C49X0208. High Performance 1:8 Multi-Voltage CMOS Buffer
Features 8 single-ended outputs Fanout Buffer Up to 200MHz output frequency Ultra low output additive jitter = 0.01ps (typ.) Selectable reference inputs support Xtal (10~50MHz), singleended and differential
PI6LC48P Output LVPECL Networking Clock Generator
Features ÎÎFour differential LVPECL output pairs ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input ÎÎSupports the following output frequencies: 156.25MHz, 125MHz, 62.5MHz
PI6C :4 24MHz Clock Buffer. Description. Features. Applications. Block Diagram. Pin Configuration (16-Pin TSSOP) 16-pin (173 mil) TSSOP
Features ÎÎSupport XTAL or Clock input at 24MHz ÎÎFour buffered outputs support V DDO operation ÎÎVery low phase jitter(rms) : < 1.5ps (max) ÎÎVery low additive jitter:
2.5/3.3V 1:22 HIGH-PERFORMANCE, LOW-VOLTAGE PECL BUS CLOCK DRIVER & TRANSLATOR w/ INTERNAL TERMINATION
2.5/3.3V 1:22 HIGH-PERFORMANCE, LOW-VOLTAGE PECL BUS CLOCK DRIVER & TRANSLATOR w/ INTERNAL TERMINATION FEATURES LVPECL or LVDS input to 22 LVPECL outputs 100K ECL compatible outputs LVDS input includes
PI90LV031A PI90LV027A PI90LV017A. 3V LVDS High-Speed Differential Line Drivers. Description. Features PI90LV027A PI90LV031A PI90LV017A
PI90LV03A PI90LV027A PI90LV07A 3V LVDS High-Speed Differential Line Drivers Features Signaling Rates >400Mbps (200 MHz) Single 3.3V Power Supply Design ±30mV Differential Swing Maximum Differential Skew
PI6C :8 Clock Driver for Intel PCI Express Chipsets. Description. Features. Pin Configuration. Block Diagram
Features Eight Pairs of Differential Clocks Low skew < 50ps Low Cycle-to-cycle jitter < 50ps Output Enable for all outputs Outputs Tristate control via SMBus Power Management Control Programmable PLL Bandwidth
PI6C557-03B. PCIe 3.0 Clock Generator with 2 HCSL Outputs. Features. Description. Pin Configuration (16-Pin TSSOP) Block Diagram
Features ÎÎPCIe 3.0 compliant à à PCIe 3.0 Phase jitter - 0.45ps RMS (High Freq. Typ.) ÎÎLVDS compatible outputs ÎÎSupply voltage of 3.3V ±10% ÎÎ5MHz crystal or clock input frequency ÎÎHCSL outputs, 0.8V
PI6LC48P03 3-Output LVPECL Networking Clock Generator
Features ÎÎThree differential LVPECL output pairs ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input ÎÎSupports the following output frequencies: 125MHz, 156.25MHz, 312.5MHz,
PI6LC48P Output LVPECL Networking Clock Generator
Features ÎÎThree differential LVPECL output pairs ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input ÎÎSupports the following output frequencies: 125MHz, 156.25MHz, 312.5MHz,
ICS83021I. Features. General Description. Pin Assignment. Block Diagram 1-TO-1 DIFFERENTIAL- TO-LVCMOS/LVTTL TRANSLATOR
1-TO-1 DIFFERENTIAL- TO-LVCMOS/LVTTL TRANSLATOR General Description The is a 1-to-1 Differential-to-LVCMOS/ ICS LVTTL Translator and a member of the HiPerClockS HiPerClockS family of High Performance Clock
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2-Bit Bus Switch with Individual Enables Features Near-Zero propagation delay 5Ω switches connect inputs to outputs Direct bus connection when switches are ON Ultra Low Quiescent Power (0.2μA typical)
3.3V LVPECL 1:4. Features. Description. Block Diagram AK8181D
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PI5V330S. Low On-Resistance Wideband/Video Quad 2-Channel Mux/DeMux. Features. Description. Block Diagram. Pin Configuration.
Features High-performance solution to switch between video sources Wide bandwidth: 570 MHz (typical) Low On-Resistance: 5Ω (typical) Low crosstalk at 10 MHz: 80dB Ultra-low quiescent power (0.1µA typical)
Low Skew, 1-to-6, Crystal-to-LVDS Fanout Buffer ICS DATA SHEET. General Description. Features. Block Diagram. Pin Assignment ICS
Low Skew, 1-to-6, Crystal-to-LVDS Fanout Buffer ICS8546-01 DATA SHEET General Description The ICS8546-01 is a low skew, high performance 1-to-6 Crystal Oscillator-to-LVDS Fanout Buffer. The ICS8546-01
PL V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer
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PI6LC48P03A 3-Output LVPECL Networking Clock Generator
Features ÎÎThree differential LVPECL output pairs ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input ÎÎSupports the following output frequencies: 125MHz, 156.25MHz, 312.5MHz,
PI6LC48P0201A 2-Output LVPECL Networking Clock Generator
Features ÎÎTwo differential LVPECL output pairs ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input ÎÎSupports the following output frequencies: 62.5MHz, 125MHz, 156.25MHz
PI5C Bit, 2-Port Bus Switch. Features. Description. Pin Configuration. Block Diagram. Pin Description. Truth Table (1) Pin Name Description
Features ÎÎNear-Zero propagation delay ÎÎ5-ohm switches connect inputs to outputs ÎÎDirect bus connection when switches are on ÎÎUltra Low Quiescent Power (0.2μA typical) Ideally suited for notebook applications
Low Skew, 1-to-4 Differential-to-3.3V LVPECL Fanout Buffer
Low Skew, 1-to-4 Differential-to- LVPECL Fanout Buffer 8533I-01 DATA SHEET GENERAL DESCRIPTION The 8533I-01 is a low skew, high performance 1-to-4 Differential-to- LVPECL Fanout Buffer. The 8533I-01 has
Description. Applications. ÎÎNetworking systems ÎÎEmbedded systems ÎÎOther systems
Features ÎÎ3.3V ±10% supply voltage ÎÎ25MHz XTAL or reference clock input ÎÎFive PCIe 2.0 Compliant 100MHz selectable HCSL outputs with -0.5% spread default is spread off ÎÎTwo 25MHz LVCMOS output ÎÎIndustrial
Low Skew, 1-to-6, Differential-to- 2.5V, 3.3V LVPECL/ECL Fanout Buffer
Low Skew, 1-to-6, Differential-to- 2.5V, LVPECL/ECL Fanout Buffer ICS853S006I DATA SHEET General Description The ICS853S006I is a low skew, high performance 1-to-6 Differential-to-2.5V/ LVPECL/ECL Fanout
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3.3V DIFFERENTIAL LVPECL/CML/LVDS-to-LVTTL TRANSLATOR FEATURES 3.3V power supply 1.9ns typical propagation delay 275MHz f MAX Differential LVPECL/CML/LVDS inputs 24mA LVTTL outputs Flow-through pinouts
PI6C49X0204A. Low Skew 1 TO 4 Clock Buffer. Features. Description. Block Diagram. Pin Assignment
Features ÎÎLow skew outputs (250 ps) ÎÎPackaged in 8-pin SOIC ÎÎLow power CMOS technology ÎÎOperating Voltages of 1.5 V to 3.3 V ÎÎOutput Enable pin tri-states outputs ÎÎ3.6 V tolerant input clock ÎÎIndustrial
3.3V/5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX
3.3V/5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX FEATURES High-speed 1:4 PECL/ECL fanout buffer 2:1 multiplexer input Guaranteed AC parameters over temp/voltage: > 2.5GHz f MAX (toggle) < 225ps
PI6C49X0204B Low Skew, 1-TO-4 LVCMOS/LVTTL Fanout Buffer Features Description Block Diagram Pin Assignment
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PI6LC4830. HiFlex TM Network Clock Generator. Features. Description. Pin Configuration. Block Diagram
IN_SEL PI6LC4830 Features ÎÎ3.3V supply voltage ÎÎ3 HCSL and 1 LVCMOS 100MHz outputs with OE/ function ÎÎ1 LVCMOS 100/50MHz selectable ÎÎ25MHz crystal or differential input ÎÎLow 1ps RMS max integrated
CLK_EN CLK_SEL. Q3 THIN QFN-EP** (4mm x 4mm) Maxim Integrated Products 1
19-2575; Rev 0; 10/02 One-to-Four LVCMOS-to-LVPECL General Description The low-skew, low-jitter, clock and data driver distributes one of two single-ended LVCMOS inputs to four differential LVPECL outputs.
Low Skew, 1-to16, Differential-to-2.5V LVPECL Fanout Buffer
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ICS83056I-01. General Description. Features. Block Diagram. Pin Assignment 6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER ICS83056I-01
ICS83056I-01 General Description The ICS83056I-01 is a 6-bit, :1, Single-ended ICS LVCMOS Multiplexer and a member of the HiPerClockS HiPerClockS family of High Performance Clock Solutions from IDT. The
PI5C3253. Dual 4:1 Mux/DeMux Bus Switch
Features Near-Zero propagation delay 5Ω switches connect inputs to outputs Direct bus connection when switches are ON ESD Protection up to 2kV HBM Ultra Low Quiescent Power (0.2μA typical) Ideally suited
PI3C V/3.3V, High Bandwidth, Hot Insertion 10-Bit, 2-Port, Bus Switch
2.5V/3., High Bandwidth, Hot Insertion Features Near-Zero propagation delay 5-ohm switches connect inputs to outputs High Bandwidth (>400 MHz) Permits Hot Insertion. Rail-to-Rail, 3. or 2.5V ing 5V I/O
PI3HDMI412FT. 4-Differential Channel, 2:1 Mux/DeMux, DVI/HDMI Compliant Signal Switch with Flow-through Pin Out
Features 4-Differential Channel 2:1 Mux/DeMux DVI, HDMI rev 1.1, and HDMI rev 1.2 signal compatible -3dB BW = 1.5 GHz (3.0Gbps) Crosstalk: -35dB@1.65Gbps Switching speed: 4ns Isolation: -37dB@1.65Gbps
BLOCK DIAGRAM PIN ASSIGNMENTS. 8302I-01 Datasheet. Low Skew, 1-to-2 LVCMOS / LVTTL Fanout Buffer W/ Complementary Output
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Low Skew, 1-to-4 Differential-to- LVPECL Fanout Buffer 8533-01 Data Sheet GENERAL DESCRIPTION The 8533-01 is a low skew, high performance 1-to-4 Differential-to- LVPECL Fanout Buffer. The 8533-01 has two
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4/ 5 Differential-to-3.3V LVPECL Clock Generator
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Features. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)
2.5V Low Jitter, Low Skew 1:12 LVDS Fanout Buffer with 2:1 Input MUX and Internal Termination General Description The is a 2.5V low jitter, low skew, 1:12 LVDS fanout buffer optimized for precision telecom
PRELIMINARY LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER VCC PIN ASSIGNMENT. Q0 nq0. Q1 nq1. Q3 nq3
GENERAL DESCRIPTION The is a high speed 2-to-4 LVCMOS/ ICS LVTTL-to-LVPECL/ECL Clock Multiplexer and is HiPerClockS a member of the HiPerClockS family of high performance clock solutions from ICS. The
Features. Applications. Markets
2GHz, Low-Power, 1:6 LVPECL Fanout Buffer with 2:1 Input MUX and Internal Termination General Description The is a 2.5V/3.3V precision, high-speed, 1:6 fanout capable of handling clocks up to 2.0GHz. A
PI6LC48P0301A 3-Output LVPECL Networking Clock Generator
Features ÎÎThree differential LVPECL output pairs ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input ÎÎSupports the following output frequencies: 125MHz, 156.25MHz, 312.5MHz,
Features. Applications. Markets
1.5GHz Precision, LVPECL 1:5 Fanout with 2:1 MUX and Fail Safe Input with Internal Termination Precision Edge General Description The is a 2.5/3.3V, 1:5 LVPECL fanout buffer with a 2:1 differential input
SY89871U. General Description. Features. Typical Performance. Applications
2.5GHz Any Diff. In-To-LVPECL Programmable Clock Divider/Fanout Buffer w/ Internal Termination General Description The is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed
3.3V/5V PECL/ECL 3GHz DUAL DIFFERENTIAL 2:1 MULTIPLEXER
3.3V/5V PECL/ECL 3GHz DUAL DIFFERENTIAL 2:1 MULTIPLEXER FEATURES Dual, fully differential 2:1 PECL/ECL multiplexer Guaranteed AC parameters over temperature/ voltage: > 3GHz f MAX (toggle) < 100ps within
Features. Applications. Markets
3.2Gbps Precision, 1:2 LVPECL Fanout Buffer with Internal Termination and Fail Safe Input General Description The is a 2.5/3.3V, high-speed, fully differential 1:2 LVPECL fanout buffer optimized to provide
NB3N853531E. 3.3 V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer
3.3 V Xtal or LVTTL/LVCMOS Input 2:1 MUX to 1:4 LVPECL Fanout Buffer Description The NB3N853531E is a low skew 3.3 V supply 1:4 clock distribution fanout buffer. An input MUX selects either a Fundamental
NOT RECOMMENDED FOR NEW DESIGNS. 3.3V/5V 3GHz PECL/ECL 2:1 MULTIPLEXER
NOT RECOMMENDED FOR NEW DESIGNS Micrel, Inc. 3.3V/5V 3GHz PECL/ECL 2:1 MULTIPLEXER FEATURES 2:1 PECL/ECL multiplexer Guaranteed AC-performance over temperature/ voltage >3GHz f MAX (toggle)
SY89847U. General Description. Functional Block Diagram. Applications. Markets
1.5GHz Precision, LVDS 1:5 Fanout with 2:1 MUX and Fail Safe Input with Internal Termination General Description The is a 2.5V, 1:5 LVDS fanout buffer with a 2:1 differential input multiplexer (MUX). A
PI3C V/3.3V, High Bandwidth, Hot Insertion 8-Bit, 2-Port, Bus Switch. Description. Features. Pin Configuration. Block Diagram.
Features Near-Zero propagation delay 5-ohm switches connect inputs to outputs High Bandwidth Operation (>400 MHz) Permits Hot Insertion 5V I/O Tolerant Rail-to-Rail 3.3V or 2.5V Switching 2.5V Supply Voltage
PI74LPT V, 16-Bit Buffer/Line Driver. Features. Description. Block Diagram
Features Compatible with LCX and LVT families of products Supports 5V Tolerant Mixed Signal Mode Operation Input can be 3V or 5V Output can be 3V or connected to 5V bus Advanced Low Power CMOS Operation
PI6C
PIC0 2345789023457890234578902234578902345789023457890223457890234578902345789022345789023457890234578902234578902 Product Features Four synchronous outputs Selectable divider/multiplier Output Enable
PI6LC48P25104 Single Output LVPECL Clock Generator
Features ÎÎSingle differential LPECL output ÎÎOutput frequency range: 145MHz to 187.5MHz ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal (12kHz - 20MHz): 0.3ps (typical) ÎÎFull 3.3 or 2.5 supply
PRECISION 1:8 LVPECL FANOUT BUFFER WITH 2:1 RUNT PULSE ELIMINATOR INPUT MUX
PRECISION 1:8 LVPECL FANOUT BUFFER WITH 2:1 RUNT PULSE ELIMINATOR INPUT MUX FEATURES Selects between two clocks, and provides 8 precision, low skew LVPECL output copies Guaranteed AC performance over temperature
5.5GHz 1:4 FANOUT BUFFER/ TRANSLATOR w/400mv LVPECL OUTPUTS AND INTERNAL INPUT TERMINATION. Precision Edge SY58022U FEATURES DESCRIPTION APPLICATIONS
5.5GHz 1:4 FANOUT BUFFER/ TRANSLATOR w/400mv LVPECL OUTPUTS AND TERNAL PUT TERMATION FEATURES Precision 1:4, 400mV LVPECL fanout buffer Guaranteed AC performance over temperature and voltage: > 5.5GHz
Programmable Low Voltage 1:10 LVDS Clock Driver ADN4670
Data Sheet Programmable Low Voltage 1:10 LVDS Clock Driver FEATURES FUNCTIONAL BLOCK DIAGRAM Low output skew
Features. Applications
Ultra-Precision, 8:1 MUX with Internal Termination and 1:2 LVPECL Fanout Buffer Precision Edge General Description The is a low-jitter, low-skew, high-speed 8:1 multiplexer with a 1:2 differential fanout
Low Skew, 1-To-4, Crystal Oscillator/LVCMOS-To-3.3V LVPECL Fanout Buffer
Low Skew, 1-To-4, Crystal Oscillator/LVCMOS-To-3.3V LVPECL Fanout Buffer ICS8535I-31 General Description The ICS8535I-31 is a low skew, high performance ICS 1-to-4 3.3V Crystal Oscillator/LVCMOS-to-3.3V
PI6LC48S25A Next Generation HiFlex TM Ethernet Network Clock Generator
Features ÎÎ3.3V & 2.5V supply voltage ÎÎCrystal/CMOS input: 25 MHz ÎÎDifferential input: 25MHz, 125MHz, and 156.25 MHz ÎÎOutput frequencies: 312.5, 156.25, 125, 100, 50, 25MHz ÎÎ4 Output banks with selectable
AND INTERNAL TERMINATION
4.5GHz, 1:6 LVPECL Fanout Buffer WITH 2:1 MUX Input AND TERNAL TERMATION FEATURES Provides six ultra-low skew copies of the selected input 2:1 MUX input included for clock switchover applications Guaranteed
Features. Applications. Markets
Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with /EN 3.2Gbps, 3.2GHz General Description The is a fully differential, low voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with active-low Enable (/EN).
Features. Applications
PCIe Fanout Buffer 267MHz, 8 HCSL Outputs with 2 Input MUX PrecisionEdge General Description The is a high-speed, fully differential 1:8 clock fanout buffer optimized to provide eight identical output
4GHz, 1:4 LVPECL FANOUT BUFFER/ TRANSLATOR WITH INTERNAL TERMINATION
4GHz, 1:4 LVPECL FANOUT BUFFER/ TRANSLATOR WITH TERNAL TERMATION FEATURES Precision 1:4, LVPECL fanout buffer Guaranteed AC performance over temperature/ voltage: >4GHz f MAX (clock)
Features. Applications. Markets
Precision LVPECL Runt Pulse Eliminator 2:1 MUX with 1:2 Fanout and Internal Termination General Description The is a low jitter PECL, 2:1 differential input multiplexer (MUX) optimized for redundant source
PI6C PCI Express Clock. Product Features. Description. Block Diagram. Pin Configuration
Product Features ÎÎLVDS compatible outputs ÎÎSupply voltage of 3.3V ±10% ÎÎ5MHz input frequency ÎÎHCSL outputs, 0.7V Current mode differential pair ÎÎJitter 60ps cycle-to-cycle (typ) ÎÎSpread of ±0.5%,
PT7C4511. PLL Clock Multiplier. Features. Description. Pin Configuration. Pin Description
Features Zero ppm multiplication error Input crystal frequency of 5-30 MHz Input clock frequency of - 50 MHz Output clock frequencies up to 200 MHz Peak to Peak Jitter less than 200ps over 200ns interval
Features. Truth Table (1)
3.3V/5V, 4GHz PECL/ECL 2 Clock Generator Precision Edge General Description The is an integrated 2 divider with differential clock inputs. It is functionally equivalent to the SY100EP32V but in an ultra-small
PI5C3384 PI5C3384C. 10-Bit, 2-Port Bus Switch
PI5C3384 PI5C3384C 0-Bit, 2-Port Bus Switch Features: Near-Zero propagation delay 5Ω switches connect inputs to outputs Direct bus connection when switches are ON Ultra-low quiescent power (0.2μA typical)
Features. Applications
267MHz 1:2 3.3V HCSL/LVDS Fanout Buffer PrecisionEdge General Description The is a high-speed, fully differential 1:2 clock fanout buffer with a 2:1 input MUX optimized to provide two identical output
Features. Applications. Markets
Precision LVPECL Runt Pulse Eliminator 2:1 Multiplexer General Description The is a low jitter PECL, 2:1 differential input multiplexer (MUX) optimized for redundant source switchover applications. Unlike
PI6C557-03AQ. PCIe 2.0 Clock Generator with 2 HCSL Outputs for Automotive Applications. Description. Features. Pin Configuration (16-Pin TSSOP)
PCIe.0 Clock Generator with HCSL Outputs for Automotive Applications Features ÎÎPCIe.0 compliant à à Phase jitter -.1ps RMS (typ) ÎÎLVDS compatible outputs ÎÎSupply voltage of 3.3V ±10% ÎÎ5MHz crystal
ICS558A-02 LVHSTL TO CMOS CLOCK DIVIDER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS558A-02 Description The ICS558A-02 accepts a high-speed LVHSTL input and provides four CMOS low skew outputs from a selectable internal divider (divide by 3, divide by 4). The four outputs
Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator
Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator 87016 DATASHEET GENERAL DESCRIPTION The 87016 is a low skew, 1:16 LVCMOS/LVTTL Clock Generator. The device has 4 banks of 4 outputs and each bank can be independently
SY58608U. General Description. Features. Functional Block Diagram
3.2Gbps Precision, 1:2 LVDS Fanout Buffer with Internal Termination and Fail Safe Input General Description The is a 2.5V, high-speed, fully differential 1:2 LVDS fanout buffer optimized to provide two
SY89854U. General Description. Features. Typical Applications. Applications
Precision Low Power 1:4 LVPECL Fanout Buffer/Translator with Internal Termination General Description The is a 2.5V/3.3V precision, highspeed, fully differential 1:4 LVPECL fanout buffer. Optimized to
Features. Applications
2.5GHz, Any Differential, In-to-LVPECL, Programmable Clock Divider/Fanout Buffer with Internal Termination General Description This low-skew, low-jitter device is capable of accepting a high-speed (e.g.,
100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator
3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator General Description The is a LVTTL/LVCMOS to differential LVPECL translator operating from a single +3.3V supply. Both outputs of a differential
PI5C32X384/32X384C. 20-Bit, 2-Port Bus Switch. Features. Description. Pin Configuration. Block Diagram. Pin Description
PI5C32X384/32X384C Features Near-Zero propagation delay 5Ω switches connect inputs to outputs Direct bus connection when switches are ON Ultra-low quiescent power 32X384 (0.2µA typical) Ideally suited
3.3V/5V DUAL LVTTL/LVCMOS-to-DIFFERENTIAL LVPECL TRANSLATOR
3.3V/5V DUAL LVTTL/LVCMOS-to-DIFFERENTIAL LVPECL TRANSLATOR Precision Edge FEATURES 3.3V and 5V power supply option 300ps typical propagation delay Differential LVPECL outputs PNP LVTTL inputs for minimal
Features. Applications. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)
Flexible Ultra-Low Jitter Clock Synthesizer Clockworks FLEX General Description The SM802xxx series is a member of the ClockWorks family of devices from Micrel and provide an extremely low-noise timing
SM General Description. ClockWorks. Features. Applications. Block Diagram
ClockWorks PCI-e Octal 100MHz/200MHz Ultra-Low Jitter, HCSL Frequency Synthesizer General Description The is a member of the ClockWorks family of devices from Micrel and provides an extremely low-noise
Features. Applications
Ultra-Precision 1:8 LVDS Fanout Buffer with Three 1/ 2/ 4 Clock Divider Output Banks Revision 6.0 General Description The is a 2.5V precision, high-speed, integrated clock divider and LVDS fanout buffer
6GHz, 1:6 CML FANOUT BUFFER WITH 2:1 MUX INPUT AND INTERNAL I/O TERMINATION
6GHz, 1:6 CML FANOUT BUFFER WITH 2:1 MUX PUT AND TERNAL I/O TERMATION Precision Edge FEATURES Provides six ultra-low skew copies of the selected input 2:1 MUX input included for clock switchover applications
Crystal or Differential to LVCMOS/ LVTTL Clock Buffer
Crystal or Differential to LVCMOS/ LVTTL Clock Buffer IDT8L3010I DATA SHEET General Description The IDT8L3010I is a low skew, 1-to-10 LVCMOS / LVTTL Fanout Buffer. The low impedance LVCMOS/LVTTL outputs
XR81112 Universal Clock - High Frequency LVCMOS/LVDS/LVPECL Clock Synthesizer
Universal Clock - High Frequency LVCMOS/LVDS/LVPECL Clock Synthesizer General Description The XR81112 is a family of Universal Clock synthesizer devices in a compact FN-12 package. The devices generate
SY89540U. General Description. Features. Typical Performance. Applications. Precision Low Jitter 4x4 LVDS Crosspoint Switch with Internal Termination
Precision Low Jitter 4x4 LVDS Crosspoint Switch with Internal Termination General Description The is a low-jitter, low skew, high-speed 4x4 crosspoint switch optimized for precision telecom and enterprise
PCI-EXPRESS CLOCK SOURCE. Features
DATASHEET ICS557-01 Description The ICS557-01 is a clock chip designed for use in PCI-Express Cards as a clock source. It provides a pair of differential outputs at 100 MHz in a small 8-pin SOIC package.
ULTRA PRECISION 8:1 MUX WITH INTERNAL TERMINATION AND 1:2 400mV LVPECL FANOUT BUFFER
ULTRA PRECISION 8:1 MUX WITH INTERNAL TERMINATION AND 1:2 400mV LVPECL FANOUT BUFFER FEATURES Selects between 1 of 8 inputs, and provides 2 precision, low skew LVPECL output copies Guaranteed AC performance
XCO FAST TURNAROUND CLOCK OSCILLATOR HIGH FREQUENCY, LOW JITTER CLOCK OSCILLATOR FEATURES + DESCRIPTION SELECTOR GUIDE LVCMOS LVDS LVPECL
XCO FAST TURNAROUND DESCRIPTION FEATURES + The XCO clock series is a cutting edge family of low to high frequency, low jitter output, single or multi - frequency clock oscillators. The XCO clocks are available
PI2EQX Gbps, 1:2 Port Switch, SATA2/SAS ReDriver. Description. Features. Pin Description (Top Side View)
Features ÎÎTwo 3.2Gbps differential signal ÎÎAdjustable Receiver Equalization ÎÎ100-Ohm Differential CML I/O s ÎÎIndependent output level control ÎÎInput signal level detect and squelch for each channel
NOT RECOMMENDED FOR NEW DESIGNS
NOT RECOMMENDED FOR NEW DESIGNS 3.3V, DUAL DIFFERENTIAL LVPECL-TO-LVTTL TRANSLATOR FEATURES 3.3V power supply 2.0ns typical propagation delay