A Bit Serial Input, Constant-Current Latched LED Driver

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1 Features and Benefits Up to 9 ma constant-current outputs Undervoltage lockout Low-power MOS logic and latches High data input rate Functional replacement for TB6276BN/BF Packages Not to scale 24-pin DIP (A package) 24-pin TSSOP with exposed thermal pad (LP package) 24-pin SOIW (LW package) Description The A6276 is specifically designed for LED-display applications. Each BiMOS device includes a 16-bit MOS shift register, accompanying data latches, and 16 NPN constantcurrent sink drivers. Except for package style and allowable package power dissipation, the device options are identical. The MOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 5 V logic supply, typical serial data-input rates are up to 2 MHz. The LED drive current is de ter mined by the user selection of a single resistor. A MOS serial data output permits cascaded connections in applications requiring additional drive lines. For inter-digit blanking, all output drivers can be disabled with an ENABLE input high. Similar 8-bit devices are available as the A6275. Three package styles are provided: through-hole DIP (suffix A), surface-mount SOI (suffix LW), and TSSOP with exposed thermal pad (suffix LP). In normal applications, the copper leadframe and low logic-power dissipation of the DIP allow it to sink maximum rated current through all outputs con tin u ous ly over the operating temperature range (9 ma,.75 V drop, 85 ). All packages are lead (Pb) free, with % matte tin leadframe plating. Functional Block Diagram H

2 Selection Guide Part Number Package Packing Ambient Temperature ( ) A6276EA-T 24-pin DIP 15 per tube to 85 A6276ELPTR-T * 24-pin TSSOP per reel to 85 A6276ELWTR-T 24-pin SOIW per reel to 85 A6276SLWTR-T * 24-pin SOIW per reel 2 to 85 *Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the variant is obsolete and notice has been given. Sale of the variant is currently restricted to existing customer applications. The variant should not be purchased for new design applications because of obsolescence in the near future. Samples are no longer available. Status date change November 1, 28. Deadline for receipt of LAST TIME BUY orders is April 25, 29. Absolute Maximum Ratings* haracteristic Symbol Notes Rating Units Supply Voltage V DD 7. V Output Voltage V O.5 to 17 V Input Voltage V ROUT.4 to V DD +.4 V Output urrent I O 9 ma Ground urrent I GND 1475 ma Range S 2 to 85 º Operating Ambient Temperature T A Range E to 85 º Maximum Junction Temperature T J (max) 15 º Storage Temperature T stg 55 to 15 º *aution: These MOS devices have input static protection (lass 2) but are still sus cep ti ble to damage if exposed to extremely high static electrical charges. Thermal haracteristics may require derating at maximum conditions, see application information haracteristic Symbol Test onditions* Value Units Package A, 1-layer PB based on JEDE standard 5 º/W Package Thermal Resistance R θja Package LP, 2-layer PB with 3.8 in. 2 copper area each side 32 º/W Package LW, 1-layer PB based on JEDE standard 85 º/W *Additional thermal information available on the Allegro website 4. ALLOWABLE PAKAGE POWER DISSIPATION IN WATTS PIN TSSOP*, R θja = 32 /W 24-PIN DIP, RθJA = 5 /W 24-LEAD SOI, RθJA = 85 /W AMBIENT TEMPERATURE IN *Mounted on single-layer, two-sided PB, with 3.8 in 2 copper each side; additional information on Allegro Web site ; 2

3 Pin-out Diagram (A, LP, and LW packages) GROUND 1 V DD 24 LOGI SUPPLY SERIAL DATA IN 2 I O REGULATOR 23 R EXT LOK 3 K 22 SERIAL DATA OUT LATH ENABLE OUT 4 5 L REGISTER LATHES OE 21 2 OUTPUT ENABLE OUT 15 OUT OUT 14 OUT OUT 13 OUT OUT 12 OUT OUT 11 OUT OUT 1 OUT OUT 9 OUT OUT 8 Terminal Description Terminal No. Terminal Name Function 1 GND Reference terminal for control logic. 2 SERIAL DATA IN Serial-data input to the shift-register. 3 LOK lock input terminal for data shift on rising edge. 4 LATH ENABLE Data strobe input terminal; serial data is latched with high-level input. 5-2 OUT -15 The 16 current-sinking output ter mi nals. 21 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output drivers are turned OFF (blanked). 22 SERIAL DATA OUT MOS serial-data output to the following shift-register. 23 R EXT An external resistor at this terminal establishes the output current for all sink drivers. 24 SUPPLY (V DD ) The logic supply voltage (typically 5 V) ; opyright 2, 23 3

4 V DD V DD IN IN Dwg. EP-1-11 OUTPUT ENABLE (active low) LATH ENABLE Dwg. EP-1-12 V DD V DD IN OUT Dwg. EP-63-6 Dwg. EP-1-13 LOK and SERIAL DATA IN SERIAL DATA OUT TRUTH TABLE Serial Shift Register ontents Serial Latch Latch ontents Output Output on tents Data lock Data Enable Enable Input Input I 1 I 2 I 3... I N-1 I N Output Input I 1 I 2 I 3... I N-1 I N Input I 1 I 2 I 3... I N-1 I N H H R 1 R 2... R N-2 R N-1 R N-1 L L R 1 R 2... R N-2 R N-1 R N-1 X R 1 R 2 R 3... R N-1 R N R N X X X... X X X L R 1 R 2 R 3... R N-1 R N P 1 P 2 P 3... P N-1 P N P N H P 1 P 2 P 3... P N-1 P N L P 1 P 2 P 3... P N-1 P N X X X... X X H H H H... H H L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State ; 4

5 ELETRIAL HARATERISTIS at T A = +25, V DD = 5 V (unless otherwise noted). Limits haracteristic Symbol Test onditions Min. Typ. Max. Unit Supply Voltage Range V DD Operating V Under-Voltage Lockout V DD(UV) V DD = 5 V V Output urrent I O V E =.7 V, R EXT = ma (any single output) V E =.7 V, R EXT = ma Output urrent Matching I O.4 V V E(A) = V E(B).7 V: (difference between any R EXT = 25 ±1.5 ±6. % two outputs at same V E ) R EXT = 47 ±1.5 ±6. % Output Leakage urrent I EX V OH = 15 V μa Logic Input Voltage V IH.7V DD V DD V V IL GND.3V DD V SERIAL DATA OUT V OL I OL = 5 μa.4 V Voltage V OH I OH = -5 μa 4.6 V Input Resistance R I ENABLE Input, Pull Up 15 3 k LATH Input, Pull Down 2 k Supply urrent I DD(OFF) R EXT = open, V OE = 5 V ma R EXT = 47 Ω, V OE = 5 V ma R EXT = 25 Ω, V OE = 5 V ma I DD(ON) R EXT = 47, V OE = V ma R EXT = 25, V OE = V ma Typical Data is at V DD = 5 V and is for design information only ; 5

6 SWITHING HARATERISTIS at T A = 25, V DD = V IH = 5 V, V E =.4 V, V IL = V, R EXT = 47 Ω, I O = ma, V L = 3 V, R L = 65 Ω, L = 1.5 pf. Limits haracteristic Symbol Test onditions Min. Typ. Max. Unit Propagation Delay Time t phl LOK-OUT n 35 ns LATH-OUT n 35 ns ENABLE-OUT n 35 ns LOK-SERIAL DATA OUT ns Propagation Delay Time t plh LOK-OUT n 3 ns LATH-OUT n 3 ns ENABLE-OUT n 3 ns LOK-SERIAL DATA OUT ns Output Fall Time t f 9% to 1% voltage ns Output Rise Time t r 1% to 9% voltage 15 3 ns REOMMENDED OPERATING ONDITIONS haracteristic Symbol onditions Min. Typ. Max. Unit Supply Voltage V DD V Output Voltage V O V Output urrent I O ontinuous, any one output 9 ma I OH SERIAL DATA OUT -1. ma I OL SERIAL DATA OUT 1. ma Logic Input Voltage V IH.7V DD V DD +.3 V V IL -.3.3V DD V lock Frequency f K ascade operation 1 MHz ; 6

7 TIMING REQUIREMENTS and SPEIFIATIONS (Logic Levels are V DD and Ground) LOK 5% A B SERIAL DATA IN DATA 5% t p SERIAL DATA OUT 5% DATA D E LATH ENABLE 5% OUTPUT ENABLE LOW = ALL OUTPUTS ENABLED t p HIGH = OUTPUT OFF OUT N OUTPUT ENABLE OUT N 5% F t phl 5% DATA LOW = OUTPUT ON Dwg. WP-29-1 HIGH = ALL OUTPUTS DISABLED (BLANKED) 9% t plh t f DATA t r 5% 1% Dwg. WP-3-1A A. Data Active Time Before lock Pulse (Data Set-Up Time), t su(d)... 5 ns B. Data Active Time After lock Pulse (Data Hold Time), t h(d)... 2 ns. lock Pulse Width, t w(k)... 5 ns D. Time Between lock Activation and Latch Enable, t su(l)... ns E. Latch Enable Pulse Width, t w(l)... ns F. Output Enable Pulse Width, t w(oe) μs NOTE: Timing is representative of a 1 MHz clock. Significantly higher speeds are attainable. Max. lock Transition Time, t r or t f... 1 μs Serial data present at the input is transferred to the shift register on the logic -to-logic 1 transition of the LOK input pulse. On succeeding LOK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The serial data must appear at the input prior to the rising edge of the LOK input waveform. Information present at any register is transferred to the respective latch when the LATH ENABLE is high (serial-topar al lel con ver sion). The latches continue to accept new data as long as the LATH ENABLE is held high. Ap pli ca tions where the latches are bypassed (LATH ENABLE tied high) will require that the OUTPUT EN ABLE input be high during serial data entry. When the OUTPUT ENABLE input is high, the output sink driv ers are disabled (OFF). The in for ma tion stored in the latches is not affected by the OUTPUT ENABLE input. With the OUT- PUT ENABLE input low, the outputs are con trolled by the state of their re spec tive latches ; 7

8 ALLOWABLE OUTPUT URRENT AS A FUNTION OF DUTY YLE A6276EA A6276ELW VE = 1 V VE =.7 V 2 TA = +25 VDD = 5 V R JA = 5 /W VE = 4 V VE = 3 V VE = 2 V 2 TA = +25 VDD = 5 V R JA = 75 /W VE = 4 V VE = 3 V VE = 2 V VE = 1 V 2 2 Dwg. GP Dwg. GP-62-6 VE = 1 V VE =.7 V 2 TA = +5 VDD = 5 V R JA = 5 /W VE = 4 V VE = 3 V VE = 2 V 2 TA = +5 VDD = 5 V R JA = 75 /W VE = 4 V VE = 3 V VE = 2 V VE = 1 V 2 Dwg. GP Dwg. GP ; 8

9 ALLOWABLE OUTPUT URRENT AS A FUNTION OF DUTY YLE (cont.) A6276EA A6276ELW VE =.7 V VE =.4 V 2 TA = +85 VDD = 5 V R JA = 5 /W VE = 4 V VE = 3 V VE = 2 V VE = 1 V 2 VE = 4 V TA = +85 VDD = 5 V R JA = 75 /W VE = 3 V VE = 2 V VE = 1 V VE =.7 V 2 Dwg. GP Dwg. GP-62-8 TYPIAL HARATERISTIS OUTPUT URRENT IN ma/bit 2 TA = +25 REXT = VE IN VOLTS Dwg. GP ; 9

10 ALLOWABLE OUTPUT URRENT AS A FUN TION OF DUTY YLE (cont.) A6276ELP VE =1V 2 TA =+25ı VDD =5V Rˇ JA =ı /W VE =4V VE =2V VE =3V 2 VE =1V 2 TA =+5ı VDD =5V Rˇ JA =ı /W VE =4V VE =3V VE =2V ; 1

11 Applications Information The load current per bit (I O ) is set by the external re sis tor (R EXT ) as shown in the figure below k 2 k 3 k URRENT-ONTROL RESISTANE, R V E =.7 V EXT IN OHMS 5 k Dwg. GP-61 Package Power Dissipation (P D ). The maximum allow able package power dissipation is determined as P D (max) = (15 - T A )/R JA. The actual package power dissipation is P D (act) = D (V E I O 16) + (V DD I DD ), where D is the duty cycle. When the load supply voltage is greater than 3 V to 5 V, considering the package power dissipating limits of these devices, or if P D (act) > P D (max), an external voltage reducer (V DROP ) should be used. diode (V Z ), or a series string of diodes (approximately.7 V per diode) for a group of drivers. If the available voltage source will cause unacceptable dissipation and series resistors or diode(s) are undesirable, a regulator such as the Sanken Series SAI or Series SI can be used to pro vide supply voltages as low as 3.3 V. For reference, typical LED forward voltages are: White V Blue V Green V Yellow V Amber V Red V Infrared V Pattern Layout. This device has a common logic-ground and power-ground terminal. If ground pattern layout con tains large common-mode resistance, and the voltage between the system ground and the LATH ENABLE or LOK terminals ex ceeds 2.5 V (because of switching noise), these devices may not operate correctly. V LED V DROP Load Supply Voltage (V LED ). These devices are designed to operate with driver voltage drops (V E ) of.4 V to.7 V with LED forward voltages (V F ) of 1.2 V to 4. V. If higher voltages are dropped across the driver, package power dissipation will be increased significantly. To minimize package power dissipation, it is rec om - mend ed to use the lowest possible load supply voltage or to set any series dropping voltage (V DROP ) as V DROP = V LED - V F - V E with V DROP = I o R DROP for a single driver, or a Zener V F V E Dwg. EP ; 11

12 Package A, 24-pin DIP A MIN MAX For Reference Only (reference JEDE MS-1 BE) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area ±.12 Package A, 24-pin TSSOP with exposed thermal pad ±.1 4 ± B ±.1 6. ±.2. ± A (1.) 24X SEATING PLANE.25 SEATING PLANE GAUGE PLANE PB Layout Reference View MAX.15 MAX A For Reference Only (reference JEDE MO-153 ADT) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown Terminal #1 mark area B Exposed thermal pad (bottom surface) Reference land pattern layout (reference IP7351 TSOP65P6X12-25M); all pads a minimum of.2 mm from all adjacent pads; adjust as necessary to meet application process requirements and PB layout tolerances; when mounting on a multilayer PB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDE Standard JESD51-5) ; 12

13 Package LW, 24-pin SOIW 15.± ± ±.1 1.3± A X.1 SEATING PLANE SEATING PLANE GAUGE PLANE B PB Layout Reference View.41 ± MAX.2 ±.1 For Reference Only (Reference JEDE MS-13 AD) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Reference pad layout (reference IP SOI127P13X265-24M) All pads a minimum of.2 mm from all adjacent pads; adjust as necessary to meet application process requirements and PB layout tolerances opyright 2-28, The products described here are manufactured under one or more U.S. patents or U.S. patents pending. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, assumes no responsibility for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: ; 13

A Bit Serial Input, Constant-Current Latched LED Driver

A Bit Serial Input, Constant-Current Latched LED Driver Features and Benefits Up to 9 ma constant-current outputs Undervoltage lockout Low-power CMOS logic and latches High data input rate Functional replacement for TB6276BN/BF Packages Not to scale 24-pin