FEATURES. Controlled Output Slew Rate High-Speed Data Storage 60 V Minimum Output Breakdown

Size: px

Start display at page:

Download "FEATURES. Controlled Output Slew Rate High-Speed Data Storage 60 V Minimum Output Breakdown"

Alberta Bennett
5 years ago
Views:

1 Data Sheet 262.2C* DABiC-IV, 0-BIT -INPUT, OUT OUT 7 OUT 6 GROUND LOGIC OUT 5 OUT CLK VDD ST A60xA V BB BLNK 0 ABSOLUTE MAXIMUM RATINGS at T A = 25 C Logic Supply Voltage, V DD V Driver Supply Voltage, V BB V Continuous Output Current Range, I OUT ma to +5 ma Input Voltage Range, V IN V to V DD V Package Power Dissipation, P D... See Graph Operating Temperature Range, T A (Suffix E ) C to +5 C (Suffix S ) C to +5 C Storage Temperature Range, T S C to +25 C THE A60XEP IS A DISCONTINUED PRODUCT Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges OUT OUT 0 LOAD OUT OUT 2 OUT 3 Dwg. PP-02 The A60 devices combine 0-bit CMOS shift registers, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. Designed primarily to drive vacuumfluorescent displays, the 60 V and -0 ma output ratings also allow these devices to be used in many other peripheral power driver applications. The A60 feature an increased data input rate (compared with the older UCN/UCQ50-F) and a controlled output slew rate. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 3.3 V or 5 V logic supply, serial-data input rates of at least 0 MHz. A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are avail-able as the A6 (2 bits), A62 (20 bits), and A6 (32 bits). The A60 output source drivers are npn Darlingtons, capable of sourcing up to 0 ma. The controlled output slew rate reduces electromagnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. For inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a BLANK- ING input high. The pnp active pull-downs will sink at least 2.5 ma. The A60 are available in two temperature ranges for optimum performance in commercial (suffix S-) or industrial (suffix E-) applications. They are provided in three package styles for through-hole DIP (suffix -A), surface-mount SOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix -EP). Copper lead frames, low logicpower dissipation, and low output-saturation voltages allow all devices to source 25 ma from all outputs continuously over the maximum operating temperature range. FEATURES Controlled Output Slew Rate High-Speed Data Storage 60 V Minimum Output Breakdown Improved Replacements High Data Input Rate for TL0, UCN50, PNP Active Pull-Downs and UCQ50 Low Output-Saturation Voltages Low-Power CMOS Logic and Latches FOR REFERENCE ONLY Complete part number includes a suffix to identify operating temperature range (E- or S-) and package type (-A, -EP, or -LW). Always order by complete part number, e.g., A60SLW.

2 0-BIT -INPUT, TYPICAL OUTPUT DRIVER V BB TYPICAL INPUT CIRCUIT V DD OUT N IN Dwg. EP-02- Dwg. EP-00-5 A60xLW A60xEP OUT OUT 7 OUT 6 GROUND LOGIC OUT CLK VDD ST V BB BLNK OUT OUT 0 LOAD OUT OUT 2 The A60xEP is a DISCONTINUED PRODUCT NC GROUND LOGIC CLK V DD ST OUT 5 3 OUT OUT 3 OUT 0 V BB BLNK LOAD NC Dwg. PP-05 OUT NO CONNECTION 0 NC NC 2 OUT 3 NO CONNECTION Dwg. PP-02-2 The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS SUFFIX 'A', RθJA = 65 C/W SUFFIX 'EP', RθJA = 7 C/W SUFFIX 'LW', RθJA = 0 C/W AMBIENT TEMPERATURE IN C Dwg. GP-02-A 5 Northeast Cutoff, Box 5036 Worcester, Massachusetts (50) Copyright, 2003 Allegro MicroSystems, Inc.

3 0-BIT -INPUT, FUNCTIONAL BLOCK DIAGRAM V DD LOGIC -PARALLEL SHIFT MOS BIPOLAR V BB LOAD GROUND OUT OUT 2 OUT 3 OUT N Dwg. FP-03- TRUTH TABLE Serial Shift Register Contents Serial Latch Contents Output Contents Data Clock Data Strobe Input Input I I 2 I 3... I N- I N Output Input I I 2 I 3... I N- I N Blanklng I I 2 I 3... I N- I N H H R R 2... R N-2 R N- R N- L L R R 2... R N-2 R N- R N- X R R 2 R 3... R N- R N R N X X X... X X X L R R 2 R 3... R N- R N P P 2 P 3... P N- P N P N H P P 2 P 3... P N- P N L P P 2 P 3... P N- P N X X X... X X H L L L... L L L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State

4 0-BIT -INPUT, ELECTRICAL CHARACTERISTICS at T A = +25 C (A60S-) or over operating temperature range (A60E-), V BB = 60 V unless otherwise noted. V DD = 3.3 V V DD = 5 V Characteristic Symbol Test Conditions Mln. Typ. Max. Min. Typ. Max. Units Output Leakage Current I CEX V OUT = 0 V < < µa Output Voltage V OUT() I OUT = -25 ma V V OUT(0) I OUT = ma V Output Pull-Down Current I OUT(0) V OUT = 5 V to V BB ma Input Voltage V IN() V V IN(0)..7 V Input Current I IN() V IN = V DD <0.0.0 <0.0.0 µa I IN(0) V IN = 0 V < < µa Input Clamp Voltage V IK I IN = -200 µa V Serial Data Output Voltage V OUT() I OUT = -200 µa V V OUT(0) I OUT = 200 µa V Maximum Clock Frequency f c 0* 0* MHz Logic Supply Current I DD() All Outputs High ma I DD(0) All Outputs Low ma Load Supply Current I BB() All Outputs High, No Load ma I BB(0) All Outputs Low µa Blanking-to-Output Delay t dis(bq) C L = 30 pf, to µs t en(bq) C L = 30 pf, to µs Strobe-to-Output Delay t p(sth-ql) R L = 2.3 kω, C L 30 pf µs t p(sth-qh) R L = 2.3 kω, C L 30 pf µs Output Fall Time t f R L = 2.3 kω, C L 30 pf µs Output Rise Time t r R L = 2.3 kω, C L 30 pf µs Output Slew Rate dv/dt R L = 2.3 kω, C L 30 pf V/µs Clock-to-Serial Data Out Delay t p(ch-sqx) I OUT = ±200 µa ns Negative current is defined as coming out of (sourcing) the specified device terminal. Typical data is is for design information only and is at T A = +25 C. *Operation at a clock frequency greater than the specified minimum value is possible but not warranteed. 5 Northeast Cutoff, Box 5036 Worcester, Massachusetts (50)

5 0-BIT -INPUT, TIG REQUIREMENTS and SPECIFICATIONS (Logic Levels are V DD and Ground) C A B DATA t p(ch-sqx) DATA D E LOW = ALL OUTPUTS ENABLED t p(sth-qh) t p(sth-ql) OUT N 0% 0% DATA Dwg. WP-02 HIGH = ALL OUTPUTS BLANKED (DISABLED) t dis(bq) OUT N t en(bq) 0% t r DATA 0% t f A. Data Active Time Before Clock Pulse (Data Set-Up Time), t su(d) ns B. Data Active Time After Clock Pulse (Data Hold Time), t h(d) ns C. Clock Pulse Width, t w(ch) ns D. Time Between Clock Activation and Strobe, t su(c) ns E. Strobe Pulse Width, t w(sth) ns NOTE Timing is representative of a 0 MHz clock. Higher speeds may be attainable; operation at high temperatures will reduce the specified maximum clock frequency. Serial Data present at the input is transferred to the shift register on the logic 0 to logic transition of the input pulse. On succeeding pulses, the registers shift data information towards the PUT. The Dwg. WP-030A DATA must appear at the input prior to the rising edge of the input waveform. Information present at any register is transferred to the respective latch when the is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the is held high. Applications where the latches are bypassed ( tied high) will require that the input be high during serial data entry. When the input is high, the output source drivers are disabled (OFF); the pnp active pull-down sink drivers are ON. The information stored in the latches is not affected by the input. With the input low, the outputs are controlled by the state of their respective latches.

6 0-BIT -INPUT, A60EA & A60SA Dimensions in Inches (controlling dimensions) MAX MAX Dwg. MA-00-A in Dimensions in Millimeters (for reference only) MAX MAX Dwg. MA-00-A mm NOTES:. Exact body and lead configuration at vendor s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below.. Supplied in standard sticks/tubes of 2 devices. 5 Northeast Cutoff, Box 5036 Worcester, Massachusetts (50)

7 0-BIT -INPUT, A60EEP & A60SEP Dimensions in Inches (controlling dimensions) 3 The A60xEP is a DISCONTINUED PRODUCT INDEX AREA Dwg. MA A in Dimensions in Millimeters (for reference only) INDEX AREA Dwg. MA A mm NOTES:. Exact body and lead configuration at vendor s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of devices or add TR to part number for tape and reel.

8 0-BIT -INPUT, A60ELW and A60SLW Dimensions in Inches (for reference only) TO Dimensions in Millimeters (controlling dimensions) Dwg. MA in TO Dwg. MA mm NOTES:. Exact body and lead configuration at vendor s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 37 devices or add TR to part number for tape and reel. 5 Northeast Cutoff, Box 5036 Worcester, Massachusetts (50)

DISCONTINUED PRODUCT 5810-F FOR REFERENCE ONLY. Recommended replacement A6810

DISCONTINUED PRODUCT 5810-F FOR REFERENCE ONLY. Recommended replacement A6810 BiMOS II 0-BIT -INPUT, LATCHED SOURCE DRIVERS Data Sheet 2682.24E OUT 8 OUT 7 OUT 6 GROUND LOGIC OUT 5 OUT 4 2 3 4 5 6 7 8 CLK VDD ST UCN580AF V BB BLNK 8 7 6 5 4 3 2 9 0 OUT 9 OUT 0 DATA OUT LOAD OUT