DABiC-IV 20-Bit Serial-Input Latched Source Driver

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Collin Hines
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1 Features and Benefits ontrolled output slew rate High-speed data storage 60 V minimum output break down High data-input rate PNP active pull-downs Low output-saturation voltages Low-power MOS logic and latches Improved replacements for TL581x, UN581x, and UQ581x Package: 8-pin SOIW (Package LW) Not to scale 8-pin PL (EP package) Description The A681 device combines a 0-bit MOS shift register, accompanying data latches and control circuitry with bipolar sourcing out puts,and PNP active pull-downs. De signed pri mar ily to drive vacuum-flu o res cent displays, the 60 V and -40 ma output ratings also allow these devices to be used in many other peripheral power driver applications. The A681 features an increased data-input rate (com pared with the older UN/UQ581-F) and a controlled output slew rate. The MOS shift register and latches allow direct interfacing with mi cro pro ces sor-based systems. With a 3.3 or 5 V logic supply, they operate to at least 10 MHz. A MOS serial data output permits cascaded con nec tions in ap pli ca tions re quir ing additional drive lines. Similar devices are avail able as the A6810 (10-bit) and A6818 (3-bit). The A681 output source drivers are NPN Dar ling tons, capable of sourcing up to 40 ma. The controlled output slew rate reduces elec tro mag net ic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emis sions ontinued on the next page Functional Block Diagram F

2 Description (continued) regulations. For inter-digit blanking, all output drivers can be dis abled and all sink drivers turned on with a BLANK ING input high. The PNP active pull-downs sink at least.5 ma. Three temperature ranges are available for optimum performance in commercial (suffix S-), industrial (suffix E-), or automotive (suffix K-) ap pli ca tions. Pack age styles are provided for surface-mount SOI (suffix -LW), or minimum-area surface-mount PL (suffix -EP). opper lead frames, low logic-power dis si pa tion, and low output-saturation voltages allow these drivers to source 5 ma from all outputs continuously to more than 43 (suffix -LW) or 61 (suffix -EP). Each package is available in a lead (Pb) free version, with 100% matte tin leadframe plating. Selection Guide Part Number Pb-free Packing Package Ambient Temperature, T A ( ) A681EEPTR* 800 pieces/13-in. reel PL A681EEPTR-T* Yes 40 to 85 A681ELWTR-T Yes 1000 pieces/13-in. reel SOI-W A681KLWTR-T* Yes 1000 pieces/13-in. reel SOI-W 40 to 15 A681SEPTR* 800 pieces/13-in. reel PL A681SEPTR-T Yes 0 to 85 A681SLWTR-T* Yes 1000 pieces/13-in. reel SOI-W *Variant is in production but has been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of the variant is currently restricted to existing customer applications. The variant should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: May 4, 009.

3 Absolute Maximum Ratings* haracteristic Symbol Notes Rating Units Logic Supply Voltage V DD 7 V Driver Supply Voltage V BB 60 V Input Voltage Range V IN 0.3 to V DD V ontinuous Output urrent Range I OUT 40 to 15 ma Operating Ambient Temperature T A Range K 40 to 15 º Range E 40 to 85 º Range S 0 to 85 º Maximum Junction Temperature T J (max) 150 º Storage Temperature T stg 65 to 15 º *aution: These MOS devices have input static protection (lass ) but are still susceptible to damage if exposed to extremely high static electrical charges. ALLOWABLE PAKAGE POWER DISSIPATION IN WATTS SUFFIX 'EP', R = 68 /W SUFFIX 'LW', R = 80 /W JA JA AMBIENT TEMPERATURE IN Dwg. GP-04- Thermal haracteristics haracteristic Symbol Test onditions* Value Units Package Thermal Resistance R Package EP, 1-layer PB with solder limited to mounting pads 68 º/W θja Package LW, 1-layer PB with solder limited to mounting pads 80 º/W *Additional thermal information available on the Allegro website 3

4 EP Package LW Package OUT 18 OUT OUT OUT 19 BLANKING 13 3 OUT LATHES 0 DATA OUT REGISTER 14 GROUND LOAD SUPPLY 1 V BB LK 15 LOK LOGI SUPPLY 16 ST V DD 8 REGISTER STROBE DATA IN 7 LATHES 17 OUT 10 OUT OUT 1 5 OUT OUT 8 Dwg. PP LOAD SUPPLY DATA OUT OUT 0 OUT 19 OUT 18 OUT 17 OUT 16 OUT 15 OUT 14 OUT 13 OUT 1 OUT 11 BLANKING GROUND VBB BLNK LATHES REGISTER REGISTER LATHES V DD ST 14 LK LOGI SUPPLY DATA IN OUT 1 OUT OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 OUT 9 OUT 10 STROBE LOK Dwg. PP-09-7 TYPIAL INPUT IRUIT TYPIAL OUTPUT DRIVER VDD V BB IN OUT N Dwg. EP Dwg. EP

5 TRUTH TABLE Serial Shift Register ontents Serial Latch ontents Output on tents Data lock Data Strobe Input Input I 1 I I 3... I N-1 I N Output Input I 1 I I 3... I N-1 I N Blanklng I 1 I I 3... I N-1 I N H H R 1 R... R N- R N-1 R N-1 L L R 1 R... R N- R N-1 R N-1 X R 1 R R 3... R N-1 R N R N X X X... X X X L R 1 R R 3... R N-1 R N P 1 P P 3... P N-1 P N P N H P 1 P P 3... P N-1 P N L P 1 P P 3... P N-1 P N X X X... X X H L L L... L L L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State 5

6 ELETRIAL HARATERISTIS at T A = +5 (A681S-) or over operating tem per a ture range (A681E- or A681K-), V BB = 60 V; un less otherwise noted V DD = 3.3 V V DD = 5 V haracteristic Symbol Test onditions Mln. Typ. Max. Min. Typ. Max. Units Output Leakage urrent I EX V OUT = 0 V < < μa Output Voltage V OUT(1) I OUT = -5 ma V V OUT(0) I OUT = 1 ma V Output Pull-Down urrent I OUT(0) V OUT = 5 V to V BB ma Input Voltage V IN(1). 3.3 V V IN(0) V Input urrent I IN(1) V IN = V DD < < μa I IN(0) V IN = 0 V < < μa Input lamp Voltage V IK I IN = -00 μa V Serial Data Output Volt age V OUT(1) I OUT = -00 μa V V OUT(0) I OUT = 00 μa V Maximum lock Frequency f c 10* 10* MHz Logic Supply urrent I DD(1) All Outputs High ma I DD(0) All Outputs Low ma Load Supply urrent I BB(1) All Outputs High, No Load ma I BB(0) All Outputs Low μa Blanking-to-Output Delay t dis(bq) L = 30 pf, to μs t en(bq) L = 30 pf, to μs Strobe-to-Output Delay t p(sth-ql) R L =.3 kω, L 30 pf μs t p(sth-qh) R L =.3 kω, L 30 pf μs Output Fall Time t f R L =.3 kω, L 30 pf μs Output Rise Time t r R L =.3 kω, L 30 pf μs Output Slew Rate dv/dt R L =.3 kω, L 30 pf V/μs lock-to-serial Data Out Delay t p(h-sqx) I OUT = ±00 μa ns Negative current is defi ned as coming out of (sourcing) the specifi ed device terminal. Typical data is is for design information only and is at T A = +5. * Operation at a clock frequency greater than the specifi ed minimum is possible but not warranteed. 6

7 TIMING REQUIREMENTS and SPEIFIATIONS (Logic Levels are V DD and Ground) LOK A B DATA IN DATA t p(h-sqx) DATA OUT DATA D E STROBE BLANKING LOW = ALL OUTPUTS ENABLED t p(sth-qh) t p(sth-ql) OUT N 90% 10% DATA Dwg. WP-09 HIGH = ALL OUTPUTS BLANKED (DISABLED) BLANKING t dis(bq) OUT N t en(bq) 10% t r DATA t f 90% Dwg. WP-030A A. Data Active Time Before lock Pulse (Data Set-Up Time), t su(d)... 5 ns B. Data Active Time After lock Pulse (Data Hold Time), t h(d)... 5 ns. lock Pulse Width, t w(h) ns D. Time Between lock Ac ti va tion and Strobe, t su() ns E. Strobe Pulse Width, t w(sth) ns NOTE Timing is representative of a 10 MHz clock. Higher speeds may be attainable with increased supply voltage; oper a tion at high temperatures will reduce the specifi ed max i mum clock frequency. Serial Data present at the input is trans ferred to the shift register on the logic 0 to logic 1 transition of the LOK input pulse. On suc ceed ing LOK pulses, the registers shift data information towards the DATA OUTPUT. The DATA must appear at the input prior to the rising edge of the LOK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-par al lel conver sion). The latches will continue to accept new data as long as the STROBE is held high. Ap pli ca tions where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the pnp active pull-down sink drivers are ON. The in for ma tion stored in the latches is not affected by the BLANKING input. With the BLANK ING input low, the outputs are con trolled by the state of their re spec tive latches. 7

8 EP Package, 8-Pin PL 1.45± ± A 5.1± ± ± ± ± MIN 8X SEATING PLANE 0.43± ± ±0.36 For Reference Only (reference JEDE MS-018 AB) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area 8

9 LW Package, 8-Pin SOIW ±0.0 4 ± ± ± A X 0.1 SEATING PLANE SEATING PLANE GAUGE PLANE B PB Layout Reference View 0.41 ± MAX 0.0 ±0.10 For Reference Only (Reference JEDE MS-013 AE) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Reference pad layout (reference IP SOI17P1030X65-8M) All pads a minimum of 0.0 mm from all adjacent pads; adjust as necessary to meet application process requirements and PB layout tolerances opyright , The products described here are manufactured under one or more U.S. patents or U.S. patents pending. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, assumes no responsibility for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: 9

A6818 DABiC-IV 32-Bit Serial Input Latched Source Driver

A6818 DABiC-IV 32-Bit Serial Input Latched Source Driver Features and Benefits Controlled output slew rate 60 V minimum output break down PNP active pull-downs Low-power CMOS logic and latches High-speed data storage High data-input rate Low output-saturation