DISCONTINUED PRODUCT 5810-F FOR REFERENCE ONLY. Recommended replacement A6810

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Rodney Andrews
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1 BiMOS II 0-BIT -INPUT, LATCHED SOURCE DRIVERS Data Sheet E OUT 8 OUT 7 OUT 6 GROUND LOGIC OUT 5 OUT CLK VDD ST UCN580AF V BB BLNK OUT 9 OUT 0 DATA OUT LOAD OUT OUT 2 OUT 3 Dwg. PP-029 ABSOLUTE IMUM RATINGS at T A = 25 C Logic Supply Voltage, V DD... 5 V Driver Supply Voltage, V BB V Continuous Output Current Range, I OUT ma to +5 ma Input Voltage Range, V IN V to V DD V Package Power Dissipation, P D (UCN580AF) W* (UCN580LWF) W* Operating Temperature Range, T A C to +85 C Storage Temperature Range, T S C to +50 C The UCN580AF and UCN580LWF combine a 0-bit CMOS shift register and accompanying data latches, control circuitry, bipolar sourcing outputs with DMOS active pull-downs. Designed primarily to drive vacuumfluorescent displays, the 60 V and -40 ma output ratings also allow these devices to be used in many other peripheral power driver applications. The UCN580AF/LWF feature reduced supply requirements (active DMOS pulldowns) and lower saturation voltages when compared with the original UCN580A. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 5 V supply, they will operate to at least 3.3 MHz. At 2 V, higher speeds are possible. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. A CMOS serial data output enables cascade connections in applications requiring additional drive lines. Similar devices are available as the UCN58A (2 bits), UCN582AF/EPF (20 bits), and UCN588AF/EPF (32 bits). The UCN580AF/LWF output source drivers are NPN Darlingtons capable of sourcing up to 40 ma. The DMOS active pull-downs are capable of sinking up to 5 ma. For inter-digit blanking, all of the output drivers can be disabled and the DMOS sink drivers turned on by the input high. The UCN580AF is furnished in an 8-pin dual in-line plastic package. The UCN580LWF is furnished in a wide-body, small-outline plastic package (SOIC) with gull-wing leads. Copper lead frames, reduced supply current requirements, and lower output saturation voltages allow all devices to source 25 ma from all outputs continuously, over the entire operating temperature range. All devices are also available for operation between -40 C and +85 C. To order, change the prefix from UCN to UCQ. DISCONTINUED PRODUCT *Derate linearly to 0 W at +50 C. FOR REFERENCE ONLY Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. Note that the UCN580AF (dual in-line package) and UCN580LWF (small-outline IC package) are electrically identical and share a common terminal number assignment. FEATURES High-Speed Source Drivers 60 V Minimum Output Breakdown Improved Replacements for TL480B Low Output Saturation Voltages Low-Power CMOS Logic and Latches To 3.3 MHz Data Input Rate Active DMOS Pull-Downs Recommended replacement A680 Always order by complete part number, e.g., UCN580AF.

2 0-BIT -INPUT, UCN580LWF FUNCTIONAL BLOCK DIAGRAM OUT 8 8 OUT 9 V DD LOGIC OUT 7 OUT CLK V BB OUT 0 DATA OUT LOAD -PARALLEL SHIFT DATA OUT GROUND LOGIC 5 6 VDD BLNK 4 3 MOS 7 ST 2 OUT BIPOLAR OUT 5 OUT OUT 2 OUT 3 V BB LOAD Dwg. PP-029- GROUND OUT OUT 2 OUT 3 OUT N Dwg. FP-03- TYPICAL INPUT CIRCUIT V DD ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS SUFFIX 'A', R θja = 60 C/W SUFFIX 'LW', R = 94 C/W θja AMBIENT TEMPERATURE IN C IN Dwg. EP-00-4A TYPICAL OUTPUT DRIVER V BB OUT N Dwg. GP-08C Dwg. No. A-4,29 5 Northeast Cutoff, Box 5036 Worcester, Massachusetts (508) Copyright 988, 2004 Allegro MicroSystems, Inc.

3 0-BIT -INPUT, ELECTRICAL CHARACTERISTICS at T A = +25 C, V BB = 60 V unless otherwise noted. V DD = 5 V V DD = 2 V Characteristic Symbol Test Conditions Mln. Typ. Max. Min. Typ. Max. Units Output Leakage Current I CEX V OUT = 0 V, T A = +70 C µa Output Voltage V OUT() I OUT = -25 ma V V OUT(0) I OUT = ma.0.5 V I OUT = 2 ma.0.5 V Output Pull-Down Current I OUT(0) V OUT = 5 V to V BB ma V OUT = 20 V to V BB ma Input Voltage V IN() V V IN(0) V Input Current I IN() V IN = V DD µa I IN(0) V IN = 0.8 V µa Serial Data Output Voltage V OUT() I OUT = -200 µa V V OUT(0) I OUT = 200 µa mv Maximum Clock Frequency f clk 3.3* MHz Supply Current I DD() All Outputs High µa I DD(0) All Outputs Low µa I BB() Outputs High, No Load ma I BB(0) Outputs Low µa Blanking to Output Delay t PHL C L = 30 pf, 50% to 50% ns t PLH C L = 30 pf, 50% to 50% ns Output Fall Time t f C L = 30 pf, 90% to 0% ns Output Rise Time t r C L = 30 pf, 0% to 90% ns Negative current is defined as coming out of (sourcing) the specified device pin. * Operation at a clock frequency greater than the specified minimum value is possible but not warranted.

4 0-BIT -INPUT, OUT N A C B D E F TIG REQUIREMENTS (T A = +25 C,V DD = 5 V, Logic Levels are V DD and Ground) A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time) ns B. Minimum Data Active Time After Clock Pulse (Data Hold Time) ns C. Minimum Data Pulse Width ns D. Minimum Clock Pulse Width ns E. Minimum Time Between Clock Activation and Strobe ns F. Minimum Strobe Pulse Width ns G. Typical Time Between Strobe Activation and Output Transistion ns Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency. G Dwg. No. A-2,649A Serial Data present at the input is transferred to the shift register on the logic 0 to logic transition of the input pulse. On succeeding pulses, the registers shift data information towards the DATA OUT- PUT. The DATA must appear at the input prior to the rising edge of the input waveform. Information present at any register is transferred to the respective latch when the is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the is held high. Applications where the latches are bypassed ( tied high) will require that the input be high during serial data entry. When the input is high, the output source drivers are disabled (OFF); the DMOS sink drivers are ON. The information stored in the latches is not affected by the input. With the input low, the outputs are controlled by the state of their respective latches. TRUTH TABLE Serial Shift Register Contents Serial Latch Contents Output Contents Data Clock Data Strobe Input Input I I 2 I 3... I N- I N Output Input I I 2 I 3... I N- I N Blanklng I I 2 I 3... I N- I N H H R R 2... R N-2 R N- R N- L L R R 2... R N-2 R N- R N- X R R 2 R 3... R N- R N R N X X X... X X X L R R 2 R 3... R N- R N P P 2 P 3... P N- P N P N H P P 2 P 3... P N- P N L P P 2 P 3... P N- P N X X X... X X H L L L... L L L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State 5 Northeast Cutoff, Box 5036 Worcester, Massachusetts (508)

5 0-BIT -INPUT, UCN580AF 8 Dimensions in Inches (controlling dimensions) Dimensions in Millimeters (for reference only) Dwg. MA-00-8A in NOTES:. Exact body and lead configuration at vendor s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 4. Supplied in standard sticks/tubes of 2 devices. Dwg. MA-00-8A mm

6 0-BIT -INPUT, UCN580LWF 8 0 Dimensions in Inches (for reference only) TO Dimensions in Millimeters (controlling dimensions) 0 Dwg. MA-008-8A in TO Dwg. MA-008-8A mm NOTES:. Exact body and lead configuration at vendor s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 4 devices or add TR to part number for tape and reel. 5 Northeast Cutoff, Box 5036 Worcester, Massachusetts (508)

7 0-BIT -INPUT, The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.

A5821. BiMOS II 8-Bit Serial Input Latched Driver. Discontinued Product

A5821. BiMOS II 8-Bit Serial Input Latched Driver. Discontinued Product A5821 BiMOS II 8-Bit Serial Input Latched Driver Discontinued Product These parts are no longer in production The device should not be purchased for new design applications. Samples are no longer available.