A Channel Constant-Current Latched LED Driver with Open LED Detection and Dot Correction

Transcription

1 6-Channel Constant-Current Latched D Driver Features and Benefits 3. to 5.5 V logic supply range Schmitt trigger inputs for improved noise immunity Power-On Reset (POR) Up to 8 ma constant-current sinking outputs D open circuit detection () Dot correction (DC) for adjusting D light intensity on each channel with 7-bit resolution Low-power CMOS logic and latches High data input rate up to 3 MHz Active output pull-ups with enable/disable 2 ns typical staggering delay between outputs Internal UVLO and thermal shutdown (TSD) circuitry Fault output flags for an D open circuit () or a thermal shutdown (TSD) condition Package: 32 Contact QFN (suffix ET) 5 mm 5 mm.9 mm nominal overall height Description The A6285 is designed for D display applications. This BiCMOS device includes an On/Off shift register, a Dot Correction (DC) shift register, accompanying data latches, and 6 MOS constant-current sink drivers with active pull-ups that can be enabled or disabled as required by the application. The CMOS shift registers and latches allow direct interfacing with microprocessor-based systems. With a 3.3 or 5 V logic supply, typical serial data input rates can reach up to 3 MHz. The D drive current level can be set by a single external resistor, selected by the application designer. A CMOS serial data output permits cascading of multiple devices in applications requiring additional drive lines. Individual D light intensity can be adjusted to correct for light intensity variations by using the Dot Correction feature. Open D connections can be detected, and then signaled back to the host microprocessor through the serial data output ( pin). The output flags an D open circuit () condition or a thermal shutdown (TSD) condition. A staggering delay on the load outputs during ON/OFF transitions helps to reduce ground bounce. Continued on the next page Not to scale Typical Application V DD V D V D KΩ μf Controller OE OE PE OUT A6285 OUT5 nf V DD REXT 6285-DS, Rev.

2 6-Channel Constant-Current Latched D Driver Description (continued) The device is available in a 32-lead QFN (package ET), with an exposed thermal pad. It is lead (Pb) free with % matte tin leadframe plating. Applications include the following: Display backlighting Monocolor, multicolor, or full-color D display Monocolor, multicolor, D Signboard Multicolor D lighting Selection Guide Part Number Package Packing (estimated) A6285EET-T 5 5 mm QFN, 32 pin, exposed thermal pad 73 pieces per tube A6285EETTR-T 5 5 mm QFN, 32 pin, exposed thermal pad 5 pieces per 7-in reel Absolute Maximum Ratings Characteristic Symbol Notes Min. Max. Unit Supply Voltage* V DD V OUTx Current (any single output) I O 9 ma Input Voltage Range* V I V OE, V, V, V, V.3 V DD +.3 V D Load Supply Range* V D V ESD Rating HBM (JEDEC JESD22-A4, Human Body Model).5 kv CDM (JEDEC JESD22-C, Charged Device Model). kv Operating Temperature Range (E) T A 4 85 C Junction Temperature T J (max) 5 C Storage Temperature Range T stg 55 5 C *With respect to ground (GND, PGND). 5 Northeast Cutoff Worcester, Massachusetts U.S.A ; 2

3 6-Channel Constant-Current Latched D Driver Functional Block Diagram 5 Status Info: 5 TSD VDD UVLO POR VDD ON/OFF Shift Register 5 DC Shift Register OE TSD ON/OFF Register DC Register 6 ON/OFF Register DC Register 7 3 ON/OFF Register 5 DC Register 5 UVLO PAD 7-Bit DC 7-Bit DC 5 7-Bit DC REXT GND Io Regulator PE OUT OUT OUT5 VD Inputs and Outputs Equivalent Circuits (Note: Resistor values are equivalent resistance and not tested.) Active Pull-up Cell ( of 6 Outputs),,,, Ō Ē 5 Ω VDD PE 5 ma V D VDD Ω ON Ω OUTx 5 Northeast Cutoff Worcester, Massachusetts U.S.A ; 3

4 6-Channel Constant-Current Latched D Driver Pin-out Diagram OE GND VDD REXT 24 NC 2 23 PE OUT 3 22 OUT5 OUT 4 PAD 2 OUT4 PGND 5 2 PGND OUT2 6 9 OUT3 OUT3 7 8 OUT2 OUT4 8 7 OUT 9 OUT5 PGND OUT6 OUT7 OUT8 OUT9 PGND OUT Terminal List Table Name Number Description Ō Ē 3 Output Enable input. Active low. When Ō Ē = High, all OUTx outputs are forced OFF. When Ō Ē = Low, ON/OFF of OUTx outputs are controlled by input data. GND 29 Logic supply ground. PE 23 Active Pull-up Enable. When connected to D Load Supply (V D ) = enabled, when connected to PGND = disabled. REXT 27 Reference current input/output terminal. 26 Logic input, Mode select. When = Low, then,,, are connected to ON/OFF control logic. When = High,,,, are connected to dot-correction logic. NC 2 No connection. Not internally connected. OUT 3 OUT 4 OUT2 6 OUT3 7 OUT4 8 OUT5 9 OUT6 OUT7 2 OUT8 3 Constant current outputs. OUT9 4 OUT 6 OUT 7 OUT2 8 OUT3 9 OUT4 2 OUT5 22 PGND 5,, 5, 2 Power ground. 32 Data shift clock input. Note that the internal connections are switched by input at pin. At, the shift-registers selected by shift the data. Serial Data In. Data input of serial data interface. 24 Serial Data Out. Data output of serial data interface. VDD 28 Logic Supply. 25 Error output. is open drain terminal. goes low when or TSD detected. 3 Latch Enable input. Note that the internal connections are switched by input at the pin. At, the latches selected by get new data. PAD Exposed pad for enhanced thermal dissipation; not connected internally, connect to power ground plane. 5 Northeast Cutoff Worcester, Massachusetts U.S.A ; 4

5 6-Channel Constant-Current Latched D Driver Operating Characteristics ECTRICAL CHARACTERISTICS at T A = 25 C, V DD = 3. to 5.5 V, unless otherwise noted Characteristic Symbol Test Conditions Min. Typ. 2 Max. Unit Logic Supply Voltage Range V DD Operating V D Load Supply Output Voltage V D Operating 2. V V Undervoltage Lockout V DD 5. V V DD(UV) V DD 5. V V V Output Current I DS = V, R EXT = 6 Ω ma O V DS = V, R EXT =.2 kω ma Output to Output Matching Error 4 Err V = V DS(x), R EXT = 6 Ω; All outputs on % V = V DS(x), R EXT =.2 kω; All outputs on % V Load Regulation I DS(X) = to 3 V, R EXT = 6 Ω; Oreg All outputs on +6. % Output Leakage Current I DSS V OH = 2 V.5 μa Logic Input Voltage V IH.8 V DD V DD V V IL GND.2 V DD V Logic Input Voltage Hysteresis V Ihys All digital inputs 25 9 mv Logic Input Current I I All digital inputs μa Voltage V OL I OL = ma.5 V V OH I OH = ma V DD.5 V R I EXT = 9.6 kω, V OE = 5 V 6 ma DD(OFF) R EXT =.2 kω, V OE = 5 V 7 ma Supply Current 3 All outputs on, R EXT =.2 kω, V O = V, 25 ma data transfer 3 MHz I DD(ON) All outputs on, R EXT = 6 Ω, V O = V, 26 4 ma data transfer 3 MHz Output V OUT() I OUT = 5 ma; faults asserted.4 V I OUT() V OUT = 5.5 V, open drain; faults negated μa Active Pull-up I OUT() V D = V, all outputs off 2.8 ma Thermal Shutdown Temperature T JTSD Temperature increasing 65 C Thermal Shutdown Hysteresis T JTSDhys 5 C Open D Detection Threshold V.3.4 V Reference Voltage at R EXT V EXT R EXT = 6 Ω V Tested at 25 C. Specifications are assured by design and characterization over the operating temperature range of 4 C to 85 C. 2 Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 3 Recommended operating range: V O =. to 3. V. 4 Err = (I O (min or max) I O (av)) / I O (av). 5 Northeast Cutoff Worcester, Massachusetts U.S.A ; 5

6 6-Channel Constant-Current Latched D Driver SWITCHING CHARACTERISTICS at T A = 25 C, V DD = V IH = 3. to 5.5 V, V DS = V, V IL = V, R EXT =.2 kω, I O = 4 ma, V L = 3 V, R L = 5 Ω, C L = 5 pf (see table 9) Characteristic Symbol Test Conditions Min. Typ. 2 Max. Unit Clock Frequency f 3 MHz Clock Pulse Duration t wh /t wl = High/Low 6 ns Clock Frequency (cascaded) f C 25 MHz Pulse Duration t wh = High 2 ns Setup Time Hold Time Rise Time Fall Time t su to ns t su to ns t su2 to ns t su3 to ns t h to ns t h to ns t h2 to ns t h3 to ns t r, /9% points (see figure ) 6 ns OUTx, V t DD = 5 V, DC = 27, /9% points r 3 ns (see figure 2) t f, /9% points (see figure ) 6 ns OUTx, V t DD = 5 V, DC = 27, /9% points f 3 ns (see figure 2) t pd to (see figure ) 3 ns t pd to (see figure ) 3 ns Propagation Delay Time t pd2 Ō Ē to OUT (see figure 2) 6 ns t pd3 to OUT (see figure 2) 6 ns t pd4 OUTx to (see figures 2 and 3) ns t pd5 to I OUT (DC) (see figure 2) 2 ns Sample and Read Time t to 2 66 ns Output Delay Time t d OUTx to OUT(x+) (see figure 2) 2 4 ns Tested at 25 C. Specifications are assured by design and characterization over the operating temperature range of 4 C to 85 C. 2 Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits d maximum and minimum limits. Parameter Measurement Information A6285 A A k 5 pf OUTx 5 pf Figure. Test circuit for t r, t f, t d, Figure 2. Test circuit for t r, t f, t pd2, and t d t pd3, t pd5, and t pd6 Figure 3. Test circuit for t pd4 5 Northeast Cutoff Worcester, Massachusetts U.S.A ; 6

7 6-Channel Constant-Current Latched D Driver Operating Characteristics R EXT (kω) V DS = V DC= 27 I OLC (ma) I O (ma) R EXT = 6 Ω R EXT = 8 Ω R EXT =.2 kω R EXT = 2.4 kω I O (max) (ma) Figure 4. Value of external reference resistor, REXT, versus channel Constant Output Current Thermal Characteristics V O (V) V O (V) Figure 5. Output Voltage versus Output Current at various levels of R EXT Characteristic Symbol Test Conditions Value 2 Units Package Power Dissipation P D Continuous, T A = 25 C 3.9 W Package Thermal Resistance R θja 4-layer PCB based on JEDEC standard 32 C/W Additional thermal information available on Allegro website. 2 Actual performance significantly affected by application. ALLOWAB PACKAGE POWER DISSIPATION IN WATTS Package ET, R JA = 32 C/W AMBIENT TEMPERATURE IN C Figure 6. Power Dissipation versus temperature 5 Northeast Cutoff Worcester, Massachusetts U.S.A ; 7

8 6-Channel Constant-Current Latched D Driver Functional Description Setting Maximum Channel Current The maximum output current per channel is set by a single external resistor, REXT, which is placed between the REXT pin and PGND. The voltage on REXT, V EXT, is set by an internal band gap. The maximum channel current is equivalent to the current flowing through REXT multiplied by The maximum channel output current can be calculated as: V EXT I O (max) = R EXT where: V EXT is.25 V typical, and 38.4, () R EXT is the value of the user-selected external resistor, which should not be less than 6 Ω, corresponding to 8 ma. Figure 4 shows the maximum per channel constant output current, I O (max), of OUT to OUT5, versus R EXT, the value of the, resistor between REXT terminal and ground. Dot Correction The A6285 can independently fine-adjust the current of each output channel, a feature referred to as dot correction. This feature is used to compensate for the brightness deviations of the Ds connected to the output channels, OUT through OUT5. Each of the 6 channels can be programmed with a 7-bit word. The channel output can be adjusted in 28 steps from % to % of the maximum programmable per channel output current, I O (max). Equation 2 determines the output current for each OUTx: I Ox = I O(max) DC x, (2) 27 where DC x is the programmed dot-correction value (,, 27) for each output channel. Dot correction data is entered for all channels at the same time. The complete dot correction data format consists of sixteen 7-bit words, which form a 2-bit (6 7) wide serial data packet. The data for each channel is sent in a continuous sequence, and all data is clocked in with the MSB first, as shown in figure 7. To input data into the Dot Correction register, should be set low, and must be set high. sets the input shift register to 2-bit width. After all serial data is clocked in, a rising edge on the terminal latches the data into the Dot Correction register. The timing sequence is shown in figure 9. All Channel Output Enable-Disable All OUTx channels of the A6285 can switched off using the ŌĒ pin. When ŌĒ is set high, all OUTx outputs are disabled, regardless of the on/off status of any OUTx. When ŌĒ is set to low, the on/off status of each OUTx is determined by the state of the latches in the On/Off register. ŌĒ can be PWMed to control the average current, which controls the D brightness of all outputs, in addition to the DC function. Individual Channel Output Enable-Disable Each OUTx channel can be switched on or off independently. Each of the channels can be programmed with a -bit word. On/off data is entered for all channels at the same time. The complete on/off data format consists of sixteen -bit words, which form a 6-bit wide serial data packet. The data for each channel is sent in a continuous sequence, and all data is clocked in with the MSB first, as shown in figure 8. To input data into the On/Off register, must be set low, and must be set low. allows on/off data to enter the input shift register, and sets the input shift register to 6-bit width. After all serial data is clocked in, a rising edge on the terminal latches the data into the On/Off register and moves the data at the Open Circuit Detector into the input shift register. The timing sequence is shown in figure 9. LSB DC DC.6 DC. DC 4.6 DC 5. DC OUT DC OUT2 through DC OUT4 Figure 7. Dot Correction (DC) data format LSB On/Off On/Off 4 5 On/Off MSB On/Off OUT OUT through OUT 4 OUT 5 Figure 8. Individual output on-off data format DC OUT5 MSB DC Northeast Cutoff Worcester, Massachusetts U.S.A ; 8

9 6-Channel Constant-Current Latched D Driver Delay Between Outputs The A6285 has graduated delay circuits between outputs. The fixed delay time is 2 ns (typical). OUT has no delay, OUT has a 2 ns delay, OUT2 has a 4 ns delay, and so forth. This delay prevents large in-rush currents that create ground bounce, which reduces power supply bypass capacitor requirements when the outputs turn on. The delays work during switch on and switch off of each output channel. Serial Interface Data Transfer Rate The A6285 includes a flexible serial data interface, which can be connected to a microcontroller or a digital signal processor. Only 3 pins are required to input data into the device. The rising edge of a signal shifts the data from pin to the input shift register. After all data is clocked in, a rising edge of latches the serial data to the On/Off register. All data is clocked in with the MSB first, while is set low. Multiple A6285 devices can be cascaded by connecting the pin of one device with the pin of the following device. The pin can also be connected to the microcontroller or microprocessor in order to transmit information from the A6285. Figure 9. Output on-off and Dot Correction timing 5 Northeast Cutoff Worcester, Massachusetts U.S.A ; 9

10 6-Channel Constant-Current Latched D Driver Figure shows an example application with n cascaded A6285 devices connected to a controller. The maximum number of cascaded devices depends on the application system and the data transfer rate. The minimum data input transfer rate is calculated as follows: where: f = 2 f UPDATE n, (3) f is the minimum data input frequency for and, f UPDATE is the update rate of the entire cascaded system, and n is the number of cascaded A6285 devices. Operating Modes The A6285 has two operating modes, determined by the signal: On-Off mode ( = low) Dot Correction mode ( = high) Fault Output, The open-drain output is used to report both of the fault flags, and TSD. During normal operating conditions, the internal transistor connected to the pin is turned off. The voltage on is pulled up to V DD through a external pull-up resistor. If an or TSD condition is detected, the internal transistor is turned on, and is pulled to PGND. Because is an open-drain output, multiple ICs can be ORed together and pulled- up to V DD with a single pull-up resistor, as shown in figure. This reduces the number of signals needed to report faults. To determine whether the fault is a TSD or an, can be masked by setting ŌĒ = high. However, it cannot be determined if both a TSD and an condition are present. The Truth Table is shown on page. Active Pull-up Enable, PE The A6285 provides active pull-ups on each output determined by the PE pin. When the D supply, V D, is tied to the PE pin, the active pull-ups are enabled. When the PE pin is tied to ground, the active pull-ups are disabled. The Active Pull-up Enable is also current-limited to 2.8 ma typical, preventing possible damage to the device in the event of a short-to-ground. This feature can eliminate ghosting in multiplexing applications. Undervoltage Lockout (UVLO) and Power-On Reset (POR) The A6285 includes an internal undervoltage lockout circuit that disables the outputs in the event that the logic supply voltage drops below a minimum acceptable level. This feature prevents the display of erroneous information, a function necessary for some critical applications. A Power-On Reset (POR) is performed upon recovery of the logic supply voltage after a UVLO event and at power-up. During POR, all internal shift registers and latches are set to. Thermal Shutdown Protection and Fault Flag (TSD) The A6285 provides thermal protection when the device is overheated, typically a result of excessive power being dissipated in the outputs. If the junction temperature exceeds the threshold Controller V DD k PE V D OUT A6285 V D OUT5 nf OE OE REXT OE V DD PE V D OUT A6285 V D OUT5 nf REXT V DD IC IC n 5 Figure. Schematic of cascaded A6285 devices 5 Northeast Cutoff Worcester, Massachusetts U.S.A ;

11 6-Channel Constant-Current Latched D Driver temperature, T TSDF, of 65 C (typical), all driver outputs will be turned off and a TSD fault will be flagged. The TSD flag will pull the output pin to PGND (low). After a 5 C (typical) drop in junction temperature, the outputs will turn back on and the pin will be pulled back to VDD (high). The input shift register and the latch register will remain active during a TSD event. Therefore, there is no need to reset the data in the output latches. However, the TSD cycle will continue until the thermal problem is corrected. D Open Detection () The A6285 provides D open circuit detection. This circuit flags a fault and pulls the pin to PGND (low) if any of the 6 OUTx Ds are open or disconnected from the circuit. The circuit flags a fault when all of the following conditions are met: Ō Ē is set low The voltage at each OUTx pin is sampled after being turned on V OUTx < V (.3 V typical) may be set either high or low. However, to perform a complete cycle, which includes reading the status of each OUTx, must be set low. A complete cycle is described as follows:. On/Off data is clocked into the input shift register. 2. is pulsed to move the On/Off data into the On/Off Register. The data is moved on the rising edge of. If an condition is present, the output is immediately pulled to PGND (low). 3. Data present at the Open Circuit Detector (sampled when data was moved into the On/Off Register on the previous transition of ) is immediately moved into the input shift register on the same rising edge of. If no condition was previously detected, all s are present at the Open Circuit Detector. Thus, all s are moved into the input shift register. This gives the appearance of clearing the input shift register every time On/Off data is moved into the On/Off Register, although in reality, the previous status is being moved into the input shift register. If an condition was previously detected, a for each open D will be moved from the Open Circuit Detector into the input shift register, where it can be read on the pin. 4. The existing condition is sampled within 2 μs of the outputs turning on and the resulting status data waits at the Open Circuit Detector until moved into the input shift register on the rising edge of the next pulse. 5. The cycle is repeated when new On/Off data is clocked into the input shift register. As new data is being clocked in, status data is being clocked out of the pin, where it can be read by a microprocessor. Note: It is not necessary to load new On/Off data in order to view the status waiting at the Open Circuit Detector. A second pulse will put the data into the input shift register. However, data that is presently in the input shift register will be moved into the On/Off Register, generating a blank display. Such a blank display may be undesirable; therefore, a second pulse should not be applied without first clocking in useful On/Off data for updating the display. The update interval between pulses ( to 2 ), referred to as the Sample and Read Time, t, must be at least 66 ns to allow for settling and staggered delays. Figure shows the serial data format. The truth table is shown below. LSB MSB 4 5 OUT OUT through OUT 4 OUT 5 Figure. Individual output data format Truth Table Conditions Junction Temperature Outx Voltage Output Enable, Ō Ē Fault Output T J < T TSD Outx > V H H T J < T TSD Outx < V H H T J < T TSD Outx > V L H T J < T TSD Outx < V L L T J > T TSD Outx > V H L T J > T TSD Outx < V H L T J > T TSD Outx > V L L T J > T TSD Outx < V L L 5 Northeast Cutoff Worcester, Massachusetts U.S.A ;

12 6-Channel Constant-Current Latched D Driver Application Information Load Supply Voltage (V D ) These devices are designed to operate with driver voltage drops (V DS ) of. to 3.V, with one or more D forward voltages, V F, of.2 to 4. V. If higher voltages are dropped across the driver, package power dissipation will increase significantly. To minimize package power dissipation, it is recommended to use the lowest possible load supply voltage, V D, or to set any series voltage dropping, V DROP, according to the following formula: V DROP = V D V F V DS, with V DROP = I O R DROP for a single driver or for a Zener diode (V Z ), or for a series string of silicon diodes (approximately.7 V per diode) for a group of drivers (see figure 3). If the available voltage source will cause unacceptable power dissipation and series resistors or diodes are undesirable, a voltage regulator can be used to provide V D. For reference, typical D forward voltages are: D Type V F (V) White 3.5 to 4. Blue 3. to 4. Green.8 to 2.2 Yellow 2. to 2. Amber.9 to 2.65 Red.6 to 2.25 Infrared.2 to.5 Pattern Layout The logic and power grounds should be kept separate, terminated at one location. The exposed metal pad must be connected to a large power ground plane, allowing the copper to dissipate heat. Where multiple devices are cascaded, multilayer boards are recommended. REXT should be placed as close as possible to the device, keeping a short distance between the REXT pin and ground. Decoupling capacitors should be used liberally.. μf should be placed on the logic supply pin, and μf placed between the common VD line and the device ground at least at every second device. Package Power Dissipation (P D ) The maximum allowable package power dissipation based on package type is determined by: P D(max) = (5 T A ) / R θja, where R θja is the thermal resistance of the package mounted on the circuit board, determined experimentally. Power dissipation levels based on the package are shown in the Package Thermal Characteristics section (see page 7). The actual package power dissipation is determined by: P D(act) = DC (V DS I O 6) + (V DD I DD ), where DC is the duty cycle. The value 6 represents the maximum number of available device outputs. When the load supply voltage, V D, is greater than 3 to 5 V, and P D(act) > P D(max), an external voltage reducer (V DROP ) must be used (see figure 2). Reducing the percent duty cycle, DC, will also reduce power dissipation. Figure 2. Typical application voltage drops 5 Northeast Cutoff Worcester, Massachusetts U.S.A ; 2

13 6-Channel Constant-Current Latched D Driver Package ET, 5 mm x 5 mm, 32-pin QFN with Exposed Thermal Pad 5. ± A ± X D.8 C SEATING PLANE C ±. C PCB Layout Reference View B 3.4 A All dimensions nominal, not for tooling use (reference JEDEC MO-22VHHD-6) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown Terminal # mark area B Exposed thermal pad (reference only, terminal # identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC735 QFN5P5X5X-33V6M); All pads a minimum of.2 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD5-5) D Coplanarity includes exposed thermal pad and terminals Copyright 27-28, The products described here are manufactured under one or more U.S. patents or U.S. patents pending. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, assumes no responsibility for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: 5 Northeast Cutoff Worcester, Massachusetts U.S.A ; 3