A8499. High Voltage Step-Down Regulator

Transcription

1 Features and Benefits 8 to 0 V input range Integrated DMOS switch Adjustable fixed off-time Highly efficient Adjustable. to 4 V output Description The A8499 is a step down regulator that will handle a wide input operating voltage range. The A8499 is supplied in a low-profile 8-lead SOI with exposed pad (package LJ). Applications include: Printer power supplies onsumer equipment power supplies Package: 8-Lead SOI with exposed thermal pad (suffix LJ) Approximate Scale : Typical Application +4 V Efficiency vs. Output urrent R kω A μf D 3 00 μf 0 V L 47 μh R 7.8 kω R 0. kω VOUT 3.3 V /. A ESR OUT 0 μf 0 V 3 0. μf Efficiency % I OUT (ma) V OUT (V) 3.3 ircuit for 4 V step down to 3.3 V at. A. Efficiency data from circuit shown in left panel.data is for reference only. A8499-DS, Rev.

2 + A8499 Functional Block Diagram Boot harge V IN VOUT L D ESR OUT µ Switch Disable Switch PWM lamp I_Peak + I_Demand + OMP Bias Supply is connected to VOUT when V OUT target is between 3.3 and V UVLO TSD Soft Start Ramp Generation. V Ab so lute Max i mum Rat ings Supply Voltage, V IN...0 V Input Voltage, V BIAS to 7 V Switch Voltage, V... V Input Voltage, V to 7 V Junction Temperature, T J(max)... 0 Storage Temperature, T S... to 0 Operating Ambient Temperature, T A... 0 to 8 Package Thermal haracteristics* Package R θja ( /W) PB LJ 3 4-layer * Additional information is available on the Allegro Web site Ordering Information Use the following complete part numbers when ordering: Part Number a Packing b Description A8499SLJTR-T a Leadframe plating 00% matte tin. b ontact Allegro for additional packing options. 3 in. reel, 3000 pieces/reel LJ package, SOI surface mount with exposed thermal pad

3 ELETRIAL HARATERISTIS, at T A =, V IN = 8 to 0 V (unless noted otherwise) haracteristics Symbol Test onditions Min. Typ. Max. Units V = LOW, I OUT = 0 ma, V IN = 4 V V BIAS = V OUT (see note 3 ) ma Quiescent urrent I (Q) V = LOW, I OUT = 0 ma, V IN = 4 V V BIAS < 3 V ma V = HIGH 00 μa Input urrent I BIAS V BIAS = V OUT 3. ma T A =, I OUT = A mω Buck Switch On Resistance R DS(on) T A =, I OUT = A.6 Ω Fixed Off-Time Proportion Based on calculated value % Feedback Voltage V V Output Voltage Regulation I OUT = 0 ma to A 3 3 % Feedback Input Bias urrent I na Soft Start Time t ss 0 ms V > 0. V. 3 A Buck Switch urrent Limit I L V < 0. V 0.. A Open ircuit Voltage V O Output disabled.0 7 V Input Voltage Threshold V (0) LOW level input (Logic 0), output enabled.0 V Input urrent I (0) V = 0 V 0 μa Undervoltage Threshold V UVLO V IN rising V Undervoltage Hysteresis V UVLOHYS V IN falling 0.7. V Thermal Shutdown Temperature T JTSD Temperature increasing 6 Thermal Shutdown Hysteresis T J Recovery = T JTSD T J. Negative current is defined as coming out of (sourcing) the specified device pin.. Specifications over the junction temperature range of 0º to º are assured by design and characterization. 3. is connected to VOUT node when V OUT target level is between 3.3 and V. 3

4 Functional Description The A8499 is a fixed off-time, current-mode controlled buck switching regulator. The regulator requires an external clamping diode, inductor, and filter capacitor, and operates in both continuous and discontinuous modes. An internal blanking circuit is used to filter out transients resulting from the reverse recovery of the external clamp diode. Typical blanking time is 00 ns. The value of a resistor between the pin and ground determines the fixed off-time (see graph in the t off section). V OUT. The output voltage is adjustable from. to 4 V, based on the combination of the value of the external resistor divider and the internal. V ±3% reference. The voltage can be calculated with the following formula: V OUT = V ( + R/R) () Light Load Regulation. To maintain voltage regulation during light load conditions, the switching regulator enters a cycle-skipping mode. As the output current decreases, there remains some energy that is stored during the power switch minimum on-time. In order to prevent the output voltage from rising, the regulator skips cycles once it reaches the minimum on-time, effectively making the off-time larger. Soft Start. An internal ramp generator and counter allow the output to slowly ramp up. This limits the maximum demand on the external power supply by controlling the inrush current required to charge the external capacitor and any dc load at startup. Internally, the ramp is set to 0 ms nominal rise time. During soft start, current limit is. A minimum. The following conditions are required to trigger a soft start: V IN > 6 V pin input falling edge Reset of a TSD (thermal shut down) event V BIAS. To improve overall system efficiency, the regulator output, V OUT, is connected to the input to supply the operating bias current during normal operating conditions. During start up the circuitry is run off of the supply. should be connected to VOUT when the V OUT target level is between 3.3 and V. If the output voltage is less than 3.3 V, then the A8499 can operate with an internal supply and pay a penalty in efficiency, as the bias current will come from the high voltage supply,. can also be supplied with an external voltage source. No power-up sequencing is required for normal opperation. ON/OFF ontrol. The pin is externally pulled to ground to enable the device and begin the soft start sequence. When the is open circuited, the switcher is disabled and the output decays to 0 V. Protection. The buck switch will be disabled under one or more of the following fault conditions: V IN < 6 V pin = open circuit TSD fault When the device comes out of a TSD fault, it will go into a soft start to limit inrush current. t OFF. The value of a resistor between the pin and ground determines the fixed off-time. The formula to calculate t OFF (μs) is: R t OFF =, (). 0 0 where R (kω) is the value of the resistor. Results are shown in the following graph: t OFF (µs) t ON. From the volt-second balance of the inductor, the turn-on time, t ON, can be calculated approximately by the equation: (V t ON = OUT + V f + I OUT R L ) t OFF (3) V IN I OUT R DS(on) I OUT R L V OUT where Resistance vs. Off-Time R (kω) V f is the voltage drop across the external Schottky diode, R L is the winding resistance of the inductor, and R DS(on) is the on-resistance of the switching MOSFET. 4

5 The switching frequency is calculated as follows: f (4) SW = t ON + t OFF Shorted Load. If the voltage on the pin falls below 0. V, the regulator will invoke a 0.8 A typical overcurrent limit to handle shorted load condition at the regulator output. For low output voltages at power up and in the case of a shorted output, the offtime is extended to prevent loss of control of the current limit due to the minimum on-time of the switcher. The extension of the off-time is based on the value of the multiplier and the voltage, as shown in the following table: V (V) Multiplier < 0. 8 t OFF < t OFF < 0.7 t OFF > 0.7 t OFF omponent Selection L. The inductor must be rated to handle the total load current. The value should be chosen to keep the ripple current to a reasonable value. The ripple current, I RIPPLE, can be calculated by: I RIPPLE = V L(OFF) t OFF / L () V L(OFF) = V OUT + V f + I L(AVG) R L (6) Example: Given V OUT = V, V f = 0. V, V IN = 4 V, I LOAD = 0. A, power inductor with L = 80 μh and R L = 0. Ω Rdc at, t OFF = 7 μs, and R DS(on) = Ω. Substituting into equation 6: V L(OFF) = V + 0. V+ 0. A 0. Ω =.8 V Substituting into equation : I RIPPLE =.8 V 7 μs / 80 μh = ma The switching frequency, f SW, can then be estimated by: f SW = / ( t ON + t OFF ) (7) t ON = I RIPPLE L / V L(ON) (8) V L(ON) = V IN I L(AVG) R DS(on) I L(AVG) R L V OUT (9) Substituting into equation 9: V L(ON) = 4 V 0. A Ω 0. A 0. Ω V = 36 V Substituting into equation 8: t ON = ma 80 μh / 36 V =. μs Substituting into equation 7: f SW = / (7 μs +. μs) = 3 khz Higher inductor values can be chosen to lower the ripple current. This may be an option if it is required to increase the total maximum current available above that drawn from the switching regulator. The maximum total current available, I LOAD(MAX), is: I LOAD(MAX) = I L(MIN) t OFF / L () where I L(MIN) is. A, from the Electrical hracteristics table. D. The Schottky catch diode should be rated to handle. times the maximum load current. The voltage rating should be higher than the maximum input voltage expected during all operating conditions. The duty cycle for high input voltages can be very close to 00%. OUT. The main consideration in selecting an output capacitor is voltage ripple on the output. For electrolytic output capacitors, a low-esr type is recommended. The peak-to-peak output voltage ripple is simply I RIPPLE ESR. Note that increasing the inductor value can decrease the ripple current. The ESR should be in the range from 0 to 00 mω. R Selection. orrect selection of R values will ensure that minimum on time of the switcher is not violated and prevent the switcher from cycle skipping. For a given V IN to V OUT ratio, the R value must be greater than or equal to the value defined by the curve in the chart R Value versus V IN / V OUT, on the next page. Note. The curve represents the minimum R value. When calculating R, be sure to use V IN (max) / V OUT (min). Resistor tolerance should also be considered, so that under no operating conditions the resistance on the pin is allowed to go below the minimum value.

6 A8499 R Value versus V IN /V OUT Violation of Minimum On-Time 0.0 / VOUT Minimum Value of R Safe Operating Area R (k ) Typical Application ircuit + V 0.0 μf 0. μf μf/ V R 30. kω A 8499 D B340 L 47 μh R 0 kω R 3.6 kω VOUT.0 V /.8 A OUT 330 μf/ 6.3V (Aluminum) V step down to.0 V at.8 A Pin-out Diagram 3 4 Pad Terminal List Table Pin Name Pin Description Pin Number Gate drive boost node On/off control logic input Off-time setting 3 Ground 4 N No connect N/A N No connect N/A Feedback for adjustable regulator Bias supply input 6 Buck switching node 7 Supply input 8 Pad Exposed pad for thermal dissipation Pad 6

7 Package LJ 8-Pin SOI ± NOM A B 3.90 ± ± REF X NOM Branded Face SEATING PLANE.70 MAX BS SEATING PLANE GAUGE PLANE A Terminal # mark area B BS 3.30 PB Layout Reference View For Reference Only; not for tooling use (reference MS-0BA) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown Exposed thermal pad (bottom surface); dimensions may vary with device Reference land pattern layout (reference IP73 SOI7P600X7-9AM); all pads a minimum of 0.0 mm from all adjacent pads; adjust as necessary to meet application process requirements and PB layout tolerances; when mounting on a multilayer PB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDE Standard JESD-) opyright 00-03, reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, assumes no responsibility for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: 7