2981 and Channel Source Drivers

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Phebe Mosley
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Features and Benefits TTL, DTL, PMOS, or CMOS compatible inputs 5 ma output source current capability Transient-protected outputs Output breakdown voltage to 5 DIP or SOIC packaging Packages: 18-pin

1 Features and Benefits TTL, DTL, PMOS, or CMOS compatible inputs 5 ma output source current capability Transient-protected outputs Output breakdown voltage to 5 DIP or SOIC packaging Packages: 18-pin DIP (suffix A) 18- and -pin SOICW (suffix LW) Description Recommended for high-side switching applications that benefit from separate logic and load grounds, these devices encompass load supply voltages to 5 and output currents to -5 ma. These 8-channel source drivers are useful for interfacing between low-level logic and high-current loads. Typical loads include relays, solenoids, lamps, stepper and/or servo motors, print hammers, and LEDs. All devices may be used with 5 logic systems TTL, Schottky TTL, DTL, and 5 CMOS. The device packages offered are electrically interchangeable, and will withstand a maximum output off voltage of 5, and operate to a minimum of 5. All devices in this series integrate input current limiting resistors and output transient suppression diodes, and are activated by an active high input. The suffix A indicates an 18-lead plastic dual in-line package with copper lead frame for optimum power dissipation. Under normal operating conditions, these devices will sustain 1 ma continuously for each of the eight outputs at an ambient temperature of +5 C and a supply of 15. The suffix LW packages are provided in a -lead widebody SOIC package with improved thermal characteristics. The AELW drivers are available for operation over an extended temperature range to -4 C. These packages are Pb (lead) free (suffix -T ), with 1% matte-tin leadframe plating. Not to scale Simplified Block Diagram 18-pin A Package -pin LW Package (NC pins omitted for 18-pin package) 931L

2 Selection Guide 1 Part Number Pb-free Package Packing Ambient Temperature ( C) AELW-T Yes -pin SOICW 37 per tube AELWTR-T Yes -pin SOICW 1 per reel 4 to 85 ASLW-T Yes -pin SOICW 37 per tube ASLWTR-T Yes -pin SOICW 1 per reel UDN981A-T Yes 18-pin DIP 1 per tube to 85 UDNA-T Yes 18-pin DIP 1 per tube 1Pb-based variants are being phased out of the product line. Some variants cited in this footnote are in production but have been determined to be LAST TIME BUY. This classifi cation indicates that sale of this device is currently restricted to existing customer applications. The variants should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change April 3, 7. Deadline for receipt of LAST TIME BUY orders: August 4, 7; these variants include: UDNLW, UDNLW-T, UDNLWTR, UDNLWTR-T, UDQLW-T, and UDQLWTR-T. Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Output oltage Range CE 5 to 5 UDN981 5 Input oltage IN A, UDN Output Current I OUT 5 ma Package Power Dissipation P D See graph Range E 4 to 85 ºC Operating Ambient Temperature T A Range S to 85 ºC Maximum Junction Temperature T J (max) 15 ºC Storage Temperature T stg 55 to 15 ºC

4 ELECTRICAL CHARACTERISTICS 1 at T A = +5 C (unless otherwise specified). Characteristic Symbol ariant Test Conditions Test Fig. Min. Typ. Max. Units Output Leakage Current I CEX All IN =.4, S = 5, T A = +7 C 1 μa Output Sustaining oltage CE(SUS) All I OUT = -45 ma 35 IN =.4, I OUT = -1 ma Collector-Emitter CE(SAT) All IN =.4, I OUT = -5 ma Saturation oltage IN =.4, I OUT = -35 ma 1.8. Input Current I IN(ON) 981 IN = μa IN = μa IN = μa IN = ma Output Source Current 981 IN =.4, CE =. -35 ma l OUT (Outputs Open) IN =.4, CE =. -35 ma Supply Current Leakage Current I S All IN =.4 *, S = ma Clamp Diode Current I R All R = 5, IN =.4 * 5 5 μa Clamp Diode Forward oltage F All I F = 35 ma Turn-On Delay t ON All.5 E IN to.5 E OUT, = 1Ω, S = μs Turn-Off Delay 3 t OFF All 1Negative current is defi ned as coming out of (sourcing) the specifi ed device terminal. All inputs simultaneously..5 E IN to.5 E OUT, = 1Ω, S = 35, See Note 5. 1 μs 3Turn-off delay is infl uenced by load conditions. Systems applications well below the specifi ed output loading may require timing considerations for some designs, i.e., multiplexed displays or when used in combination with sink drivers in a totem pole confi guration. 4

5 TEST FIGURES Figure 1 Figure Figure 3 S S S CE ma I IN ma OPEN IN μa I CEX IN I OUT IN Dwg. No. A-11,83 Dwg. No. A-11,84 Dwg. No. A-11,85 Figure 4 Figure 5 Figure 6 S S OPEN I S ma I R μa OPEN OPEN IN IN F I F Dwg. No. A-11,86 Dwg. No. A-11,87 Dwg. No. A-11,88 5

6 Allowable peak collector current as a function of duty cycle UDN981A and UDNA ALLOWABLE PEAK COLLECTOR CURRENT IN ma AT 5 C RECOMMENDED MAXIMUM OUTPUT CURRENT = 15 S NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY ALLOWABLE PEAK COLLECTOR CURRENT IN ma AT 7 C RECOMMENDED MAXIMUM OUTPUT CURRENT NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY = 15 S PER CENT DUTY CYCLE Dwg. No. A-11,17B PER CENT DUTY CYCLE Dwg. No. A-11,18B Input current as a function of input voltage Typical electrosensitive printer application.5 ELECTRODES. IN INPUT CURRENT, I IN (ma) MAXIMUM TYPICAL INPUT OLTAGE (OLTS) IN IN 3 IN 4 IN 5 IN 6 IN 7 IN 8 S Dwg. No. A-11,115B Dwg. No. A-11,113A 6

7 A Package, 18-Pin DIP A MAX.13 All dimensions nominal, not for tooling use (reference JEDEC MS-1 AC) Dimensions in inches Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area.18 LW Package, 18-Pin SOICW º A X.1 C SEATING PLANE C SEATING PLANE GAUGE PLANE MAX. All dimensions nominal, not for tooling use Dimensions in millimeters (reference JEDEC MS-13 AB) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area 7

8 LW Package, -Pin SOICW 1.8 4º A X.1 C SEATING PLANE C SEATING PLANE GAUGE PLANE All dimensions nominal, not for tooling use Dimensions in millimeters (reference JEDEC MS-13 AC) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown.65 MAX. A Terminal #1 mark area Copyright 1977, 7, The products described here are manufactured under one or more U.S. patents or U.S. patents pending. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: 8

Protected Quad Power Driver

Protected Quad Power Driver Features and Benefits 700 ma output current per channel Independent overcurrent protection for each driver Thermal protection for device and each driver Low output-saturation voltage Integral output flyback