Discontinued Product

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Quentin Sutton
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1 Discontinued Product This device is no longer in production. The device should not be purchased for new design applications. Samples are no longer available. Date of status change: October, for the AEUA-T and the ALUA-T use the ALUA-T for the AELHLT-T and the ALLHLT-T use the ALLHLX-T for the ALUA-T use the ALUA-T for the ALLHLT-T use the ALLHLX-T for the AEUA-T and the ALUA-T use the ALUA-T for the ALLHLT-T use the ALLHLX-T NOTE: For detailed information on purchasing options, contact your local Allegro field applications engineer or sales representative. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information included herein is believed to be accurate and reliable. However, assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.

2 Features and Benefits Temperature-stable quiescent output voltage Precise recoverability after temperature cycling Output voltage proportional to magnetic flux density Ratiometric rail-to-rail output Improved sensitivity.5 to 5.5 V operation Immunity to mechanical stress Solid-state reliability Robust EMC protection Packages: pin SOTW (suffix LH), and pin SIP (suffix UA) Description The AX family of linear Hall-effect sensor ICs are optimized, sensitive, and temperature-stable. These ratiometric Hall-effect sensor ICs provide a voltage output that is proportional to the applied magnetic field. The AX family has a quiescent output voltage that is 5% of the supply voltage and output sensitivity options of.5 mv/g,. mv/g, and 5m V/G. The features of this family of devices are ideal for use in the harsh environments found in automotive and industrial linear and rotary position sensing systems. Each device has a BiCMOS monolithic circuit which integrates a Hall element, improved temperature-compensating circuitry to reduce the intrinsic sensitivity drift of the Hall element, a small-signal high-gain amplifier, and a rail-to-rail lowimpedance output stage. A proprietary dynamic offset cancellation technique, with an internal high-frequency clock, reduces the residual offset voltage normally caused by device overmolding, temperature dependencies, and thermal stress. The high frequency clock allows for a greater sampling rate, which results in higher accuracy and faster signal processing capability. This technique produces devices that have an extremely stable quiescent output voltage, are immune to mechanical stress, and have precise Continued on the next page Not to scale Functional Block Diagram V+ VCC Dynamic Offset Cancellation Amp Filter Out VOUT. μf Gain Offset Trim Control GND A-DS, Rev.

3 Description (continued) recoverability after temperature cycling. Having the Hall element and an amplifier on a single chip minimizes many problems normally associated with low-level analog signals. Output precision is obtained by internal gain and offset trim adjustments made at end-of-line during the manufacturing process. The AX family is provided in a -pin single in-line package (UA) and a -pin surface mount package (LH). Each package is available in a lead (Pb) free version (suffix, T), with a % matte tin plated leadframe. Selection Guide Part Number Packing Mounting Ambient, T A (ºC) Sensitivity, Typ. (mv/g) AELHLT-T 7-in. reel, pieces/reel Surface Mount to AEUA-T Bulk, 5 pieces/bag SIP through hole 5. ALLHLT-T 7-in. reel, pieces/reel Surface Mount to 5 ALUA-T Bulk, 5 pieces/bag SIP through hole ALLHLT-T 7-in. reel, pieces/reel Surface Mount to 5. ALUA-T Bulk, 5 pieces/bag SIP through hole AEUA-T Bulk, 5 pieces/bag SIP through hole to ALLHLT-T 7-in. reel, pieces/reel Surface Mount.5 to 5 ALUA-T Bulk, 5 pieces/bag SIP through hole Contact Allegro for additional packing options. This variant is in production, however, it has been deemed Pre-End of Life. The product is approaching end of life. Within a minimum of months, the device will enter its final, Last Time Buy, order phase. Status change: January,. Suggested replacements: for the AELHLT-T and the ALLHLT-T use the ALLHLX-T, for the ALLHLT-T use the ALLHLX-T, and for the ALLHLT-T use the ALLHLX-T. Variant is in production but has been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of the variant is currently restricted to existing customer applications. The variant should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: January,. Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Supply Voltage V CC * Additional current draw may be observed at voltages above the minimum supply Zener clamp voltage, V Z(min), due to the Zener diode 8 V turning on. Output Voltage V OUT 8 V Reverse Supply Voltage V RCC. V Reverse Output Voltage V ROUT. V Output Sink Current I OUT ma Operating Ambient Temperature T A Range L to 5 ºC Maximum Junction Temperature T J (max) 5 ºC Storage Temperature T stg 5 to 7 ºC Worcester, Massachusetts 5- U.S.A ;

4 Pin-out Drawings Package LH Package UA Terminal List Symbol Number Package LH Package UA Description VCC Connects power supply to chip VOUT Output from circuit GND Ground Worcester, Massachusetts 5- U.S.A ;

5 DEVICE CHARACTERISTICS over operating temperature (T A ) range, unless otherwise noted Characteristic Symbol Test Conditions Min. Typ. Max. Units Electrical Characteristics; V CC = 5 V, unless otherwise noted Supply Voltage V cc(op) Operating; Tj < 5 C V Supply Current I cc B =, I out = 5. 8 ma Quiescent Voltage V out(q) B =, T A = ºC, I out = ma V Output Voltage V out(h) B = +X, I out = ma.7 V V out(l) B = X, I out = ma. V Output Source Current Limit I out(lm) B = X, V out..5 ma Supply Zener Clamp Voltage V Z I cc = ma = I cc(max) + 8. V Output Bandwidth BW khz Clock Frequency f C 5 khz Output Characteristics; over V CC range, unless otherwise noted A; C bypass =. μf, no load Noise, Peak-to-Peak V N A; C bypass =. μf, no load mv mv A; C bypass =. μf, no load mv Output Resistance R out I out ± ma.5 Ω Output Load Resistance R L I out ± ma, VOUT to GND.7 kω Output Load Capacitance C L VOUT to GND nf Negative current is defi ned as conventional current coming out of (sourced from) the specifi ed device terminal. Typical data is at T A = C. They are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specifi ed maximum and minimum limits. In these tests, the vector X is intended to represent positive and negative fi elds sufficient to swing the output driver between fully OFF and saturated (ON), respectively. It is NOT intended to indicate a range of linear operation. Noise specifi cation includes both digital and analog noise. Worcester, Massachusetts 5- U.S.A ;

6 MAGNETIC CHARACTERISTICS, over operating temperature range, T A ; V CC = 5 V, I out = ma; unless otherwise noted Characteristics Symbol Test Condition Min Typ Max Units A; T A = ºC mv/g Sensitivity 5 Sens A; T A = ºC mv/g A; T A = ºC mv/g Delta V out(q) as a function of temperature V out(q)(δt) Defi ned in terms of magnetic flux density, B ± G Ratiometry, V out(q) V out(q)(δv) ±.5 % Ratiometry, Sens ΔSens (ΔV) ±.5 % Positive Linearity Lin+ ±.5 % Negative Linearity Lin ±.5 % Symmetry Sym ±.5 % UA Package Delta Sens at T A = max 5 ΔSens (TAmax) From hot to room temperature % Delta Sens at T A = min 5 ΔSens (TAmin) From cold to room temperature % Sensitivity Drift Sens Drift T A = C; after temperature cycling and over time ± % LH Package Delta Sens at T A = max 5 ΔSens (TAmax) From hot to room temperature 5 5 % Delta Sens at T A = min 5 ΔSens (TAmin) From cold to room temperature % Sensitivity Drift Sens Drift T A = C; after temperature cycling and over time ± % Additional information on characteristics is provided in the section Characteristics Defi nitions, on the next page. Negative current is defi ned as conventional current coming out of (sourced from) the specifi ed device terminal. Typical data is at T A = C, except for ΔSens, and at x.x Sens. Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specifi ed maximum and minimum limits. In addition, the typical values vary with gain. G = millitesla. 5 After 5ºC pre-bake and factory programming. Sensitivity drift is the amount of recovery with time. Worcester, Massachusetts 5- U.S.A ; 5

7 Characteristic Defi nitions Quiescent Voltage Output. In the quiescent state (no magnetic field), the output equals one half of the supply voltage over the operating voltage range and the operating temperature range. Due to internal component tolerances and thermal considerations, there is a tolerance on the quiescent voltage output both as a function of supply voltage and as a function of ambient temperature. For purposes of specification, the quiescent voltage output as a function of temperature is defined in terms of magnetic flux density, B, as: V out(q)(τα ) V out(q)(ºc) ΔV out(q)(δτ) = () Sens (ºC) This calculation yields the device s equivalent accuracy, over the operating temperature range, in gauss (G). Sensitivity. The presence of a south-pole magnetic field perpendicular to the package face (the branded surface) increases the output voltage from its quiescent value toward the supply voltage rail by an amount proportional to the magnetic field applied. Conversely, the application of a north pole will decrease the output voltage from its quiescent value. This proportionality is specified as the sensitivity of the device and is defined as: Sens = V out( B) V out(+b) The stability of sensitivity as a function of temperature is defined as: B Sens (ΤΑ ) Sens (ºC) ΔSens (ΔΤ) = % Sens (ºC) () () Ratiometric. The AX family features a ratiometric output. The quiescent voltage output and sensitivity are proportional to the supply voltage (ratiometric). The percent ratiometric change in the quiescent voltage output is defined as: V out(q)(vcc ) V out(q)(5v) ΔV out(q)(δv) = % V CC 5 V and the percent ratiometric change in sensitivity is defined as: Linearity and Symmetry. The on-chip output stage is designed to provide a linear output with a supply voltage of 5 V. Although application of very high magnetic fields will not damage these devices, it will force the output into a non-linear region. Linearity in percent is measured and defined as: and output symmetry as: () Sens (VCC ) Sens (5V) ΔSens (ΔV) = % (5) V CC 5 V V out(+b) V out(q) () Lin+ = % (V out(+b / ) V out(q) ) V out( B) V out(q) (7) Lin = % (V out( B / ) V out(q) ) V out(+b) V out(q) (8) Sym = % V out(q) V out( B) Worcester, Massachusetts 5- U.S.A ;

8 Typical Characteristics ( pieces, fabrication lots) Average Supply Current (I CC ) vs Temperature Vcc = 5 V - - ICC (ma) 5 Lin+ (%) Average Positive Linearity (Lin+) vs Temperature V cc = 5 V - 5 Lin (%) Average Negative Linearity (Lin ) vs Temperature V cc = 5 V Average Ratiometry, V OUT(q)(ΔV) vs Temperature.5 to 5. V 5.5 to 5. V.8.. Average Ratiometry, ΔSens (ΔV), vs Temperature.5 to 5.V 5.5 to 5.V Ratiometry (%) Ratiometry (%) Continued on the next page... Worcester, Massachusetts 5- U.S.A ; 7

9 Typical Characteristics, continued ( pieces, fabrication lots).575 Average Absolute Quiescent Output Voltage, V out(q), vs Temperature V cc = 5 V Quiescent Output Voltage, Vout(q), vs Vcc T A = C Vout(q) (V) Vout(q) (V) Vcc (V) 5.5 Average Absolute Sensitivity, Sens, vs Temperature Vcc = 5 V 5.5 Average Sensitivity, Sens, vs V cc T A = C Sens (mv/g) A A A 5 Sens (mv/g) Vcc (V) Vout(q)(ΔT) (G) Average Delta Quiescent Output Voltage, Vout(q)(ΔT), vs Temperature Δ in readings at each temperature are relative to C Vcc = 5 V ΔSens (%) Average Delta Sensitivity, ΔSens, vs Temperature Δ in readings at each temperature are relative to C V cc = 5 V - 5 Worcester, Massachusetts 5- U.S.A ; 8

10 THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Value Units Package Thermal Resistance R θja *Additional thermal information available on Allegro website. Package LH, -layer PCB with copper limited to solder pads 8 ºC/W Package LH, -layer PCB with. in. of copper area each side connected by thermal vias ºC/W Package UA, -layer PCB with copper limited to solder pads 5 ºC/W Power Derating Curve V CC(max) Maximum Allowable V CC (V) 5 -layer PCB, Package LH (R JA = 8 ºC/W) -layer PCB, Package UA (R JA = 5 ºC/W) -layer PCB, Package LH (R JA = ºC/W) V CC(min) 8 8 Temperature (ºC) Power Dissipation, PD (mw) Power Dissipation versus Ambient Temperature -layer PCB, Package LH (R JA = ºC/W) -layer PCB, Package UA (R JA = 5 ºC/W) -layer PCB, Package LH (R JA = 8 ºC/W) 8 8 Temperature ( C) Worcester, Massachusetts 5- U.S.A ; 9

11 Power Derating The device must be operated below the maximum junction temperature of the device, T J(max). Under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors affecting operating T J. (Thermal data is also available on the Allegro MicroSystems Web site.) The Package Thermal Resistance, R JA, is a figure of merit summarizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. Its primary component is the Effective Thermal Conductivity, K, of the printed circuit board, including adjacent devices and traces. Radiation from the die through the device case, R JC, is relatively small component of R JA. Ambient air temperature, T A, and air motion are significant external factors, damped by overmolding. The effect of varying power levels (Power Dissipation, P D ), can be estimated. The following formulas represent the fundamental relationships used to estimate T J, at P D. P D = V IN I IN () T = P D R JA () Example: Reliability for V CC at T A = 5 C, package UA, using minimum-k PCB. Observe the worst-case ratings for the device, specifically: R JA = 5 C/W, T J(max) = 5 C, V CC(max) = 5.5 V, and I CC(max) = 8 ma. Calculate the maximum allowable power level, P D(max). First, invert equation : T max = T J(max) T A = 5 C 5 C = 5 C This provides the allowable increase to T J resulting from internal power dissipation. Then, invert equation : P D(max) = T max R JA = 5 C 5 C/W = 9 mw Finally, invert equation with respect to voltage: V CC(est) = P D(max) I CC(max) = 9 mw 8 ma =. V The result indicates that, at T A, the application and device can dissipate adequate amounts of heat at voltages V CC(est). Compare V CC(est) to V CC(max). If V CC(est) V CC(max), then reliable operation between V CC(est) and V CC(max) requires enhanced R JA. If V CC(est) V CC(max), then operation between V CC(est) and V CC(max) is reliable under these conditions. T J = T A + ΔT () For example, given common conditions such as: T A = C, V CC = V, I CC = ma, and R JA = C/W, then: P D = V CC I CC = V ma = 8 mw T = P D R JA = 8 mw C/W = 7 C T J = T A + T = C + 7 C = C A worst-case estimate, P D(max), represents the maximum allowable power level (V CC(max), I CC(max) ), without exceeding T J(max), at a selected R JA and T A. Worcester, Massachusetts 5- U.S.A ;

12 Package LH, -Pin (SOT-W) D A ± D D MIN REF. BSC Seating Plane Gauge Plane B.95 PCB Layout Reference View 8X REF Branded Face. ±. NNT A.95 BSC Active Area Depth,.8 mm REF. ± For Reference Only; not for tooling use (reference dwg. 88) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown C Standard Branding Reference View N = Last two digits of device part number T = Temperature code B Reference land pattern layout All pads a minimum of. mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances C Branding scale and appearance at supplier discretion D Hall element, not to scale Worcester, Massachusetts 5- U.S.A ;

13 Package UA, -Pin SIP E. B C.5 ± MAX.5 REF. E A E Branded Face.79 REF 5 Mold Ejector Pin Indent NNT D Standard Branding Reference View = Supplier emblem N = Last two digits of device part number T = Temperature code 5.75 ± For Reference Only; not for tooling use (reference DWG-99) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A B C D E Dambar removal protrusion (X) Gate burr area Active Area Depth,.5 mm REF Branding scale and appearance at supplier discretion Hall element, not to scale NOM Copyright -, reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, assumes no responsibility for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: Worcester, Massachusetts 5- U.S.A ;

A1321, A1322, and A1323

A1321, A1322, and A1323 Features and enefits Temperature-stable quiescent output voltage Precise recoverability after temperature cycling Output voltage proportional to magnetic flux density Ratiometric rail-to-rail output Improved