VK1622A RAM Mapping 32 8 LCD Controller for I/O uc Features

Transcription

1 VK1622A Features Operating voltage:2.7v~5.2v Built-in R oscillator 1/4 bias, 1/8 duty, frame frequency is 64Hz Max 32 8 patterns, 8 commons, 32 segments Built-in internal resistor type bias generator 3-wire serial interface 8 kinds of time base/wdt selection Time base or WDT overflow output Built-in LD display RAM R/W address auto increment Two selection buzzer frequencies (2KHz/4KHz) Power down command reduces power consumption Software configuration feature Data mode and command mode instructions Three data accessing modes VLD pin to adjust LD operating voltage ascade application General Description VK1622A is a peripheral device specially de-signed for I/O type u used to expand the dis-play capability. The max, display segment of the device are 256 patterns (32 8). It also sup-ports serial interface, buzzer sound, watchdog timer or time base timer functions. The VK1622A is a memory mapping and multi-function LD controller. The software configuration feature of the VK1622A make it suitable for multiple LD applications include-ing LD modules and display subsystems. Only three lines are required for the interface be-tweenthe host controller and the VK1622A. The S162X series have many kinds of products that match various applications. Block Diagram 第 1 页共 13 页

2 Pin Assignment VK1622A 第 2 页共 13 页

3 VK1622A PAD Assignment PAD 坐标 Pad No Name X Y Pad No Name X Y 1 SB SEG RDB SEG WRB SEG DATA SEG GND SEG OSI SEG SEG VLD SEG IRQB SEG BZ SEG 第 3 页共 13 页

4 VK1622A 11 BZB SEG T SEG T SEG T SEG OM SEG OM SEG OM SEG OM SEG OM SEG OM SEG OM SEG OM SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG Pad Description Pad Name I/O Description No 1 S I 2 RD I 3 WR I hip selection input with pull-high resistor. When the S is logic high, the data and command read from or write to the VK1622A are disabled. The serial interface circuit is also reset. But if the S is at logic low level and is input to the S pad, the data and command transmission between the host controller and the VK1622A are all enabled. READ clock input with pull-high resistor. Data in the RAM of the VK1622A are clocked out on the rising edge of the RD signal. The clocked out data will appear on the data line. The host con-troller can use the next falling edge to latch the clock out data. WRITE clock input with pull-high resistor. Data on the DATA line are latched into the VK1622A on the rising edge of the WR signal. 4 DATA I/O Serial data input/output with pull-high resistor 5 VSS - Negative power supply, Ground 6 OSI I If the system clock comes from an external clock source, the ex-ternal clock source should be connected to the OSI pad. 7 - Positive power supply 8 VLD I LD operating voltage input pad. 9 IRQ O Time base or watchdog timer overflow flag, NMOS open drain output 10, 11 BZ, BZ O 2KHz or 4KHz tone frequency output pair 12~14 T1~T3 I Not connected 15~22 OM0~OM7 O LD common outputs 23~54 SEG0~SEG63 O LD segment outputs Absolute Maximum Ratings 第 4 页共 13 页

5 Supply voltage -0.3V to 5.5V Input voltage VSS-0.3V to +0.3V VK1622A Storage temperature..-50 to 125 Operating temperature..-25 to 7 Note: These are stress ratings only. Stresses exceeding the range specified under Absolute maxi-mum ratings may cause substantial damage to the device. Functional operation of this de-vice at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabilit 第 5 页共 13 页

6 D.. haracteristics Symbol Parameter V DD SG1622A Test conditions onditions Ta=25 Min Typ Max Unit V DD Operating voltage V I DD1 I DD2 I STB V IL V IH I OL1 I OH1 I OL1 I OH1 I OL2 I OH2 I OL3 I OH3 R PH Operating current Operating current Standby current Input low voltage Input high voltage BZ, BZ, IRQ BZ, BZ DATA DATA LD common sink current LD common source current LD segment sink current LD segment source current Pull-high resistor 3V No load/ld ON ua 5V On-chip R oscillator ua 3V No load/ld OFF ua 5V On-chip R oscillator ua 3V No load ua 5V Power down mode ua 3V V DATA, WR, S, RD 5V V 3V V DATA, WR, S, RD 5V V 3V V OL =0.3V ma 5V V OL =0.5V ma 3V V OH =2.7V ma 5V V OH =4.5V ma 3V V OL =0.3V ua 5V V OL =0.5V ua 3V V OH =2.7V ua 5V V OH =4.5V ua 3V V OL =0.3V ua 5V V OL =0.5V ua 3V V OH =2.7V ua 5V V OH =4.5V ua 3V V OL =0.3V ua 5V V OL =0.5V ua 3V V OH =2.7V ua 5V V OH =4.5V ua 3V KΩ DATA, WR, S, RD 5V KΩ 深圳市永嘉电子有公司第 6 页共 13 页

7 SG1622A A.. haracteristics Ta=25 Symbol Parameter f SYS1 f SYS2 f LD1 f LD2 V DD Test conditions onditions Min Typ Max Unit System clock 3V On-chip R oscillator KHz 5V KHz System clock 3V External clock source KHz 5V KHz LD frame frequency 3V On-chip R oscillator Hz 5V Hz LD frame frequency 3V External clock source Hz 5V Hz t OM LD common period - N: number of OM - n/f LD - sec f LK1 f LK2 t S t LK tr, tf t su th t su1 t h1 Serial data clock (WR pin) 3V Duty cycle 50% KHz 5V KHz Serial data clock (RD pin) 3V Duty cycle 50% KHz 5V KHz Serial interface reset pulse S - Width (figure 3) ns 3V Write mode WR, RD input pulse width Read mode us (figure 1) Write mode V Read mode us Rise/fall time serial data 3V - lock width (figure 1) 5V ns Setup time for DATA to WR, 3V - RD clock width (figure 2) 5V ns Hold time for DATA to WR, 3V - RD clock width (figure 2) 5V ns Setup time for S to WR, RD 3V - lock width (figure 2) 5V ns Hold time for S to WR, RD 3V - lock width (figure 2) 5V ns 深圳市永嘉电子有公司第 7 页共 13 页

8 SG1622A WR,RD LOK S WR,RD LOK Functional Description Display memory-ram structure The static display RAM is organized into 64 4 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LD driver. Data in the RAM can be ac-cessed by the READ, WRITE and READ-MOD-IFY-WRITE commands. The following is a map-ping from the RAM to the LD patterns. Time base and watchdog timer-wdt The time base generator and WDT share the same divided (/256) counter. TIMER DIS/EN/LR, WDT DIS/EN/LR and IRQ EN/DIS are inde-pendent from each other. Once the WDT time-out occurs, the IRQ pin will remain at logic low level until the LR WDT or the IRQ DIS command is issued. OM 7 tf 90% 50% 10% 50% tsu1 50% FIRST lock OM 6 tlk Figure 3 OM 5 tr Figure 1 LAST lock th1 OM 4 tlk tcs OM 3 OM 2 OM 1 OM SEG0 3 0 GND GND GND DB WR,RD LOK 0 50% tsu VALID DATA 50% Figure 2 th GND GND SEG1 7 4 SEG SEG Address 7 bits (A5,A4..,A0) SEG D3 D2 D1 D0 Data Addr D3 D2 D1 D Data 4 bits (D3,D2,D1,D0) Data Addr 深圳市永嘉电子有公司第 8 页共 13 页

9 lock Source Time Base /256 SG1622A TIMER EN/DIS WDT EN/DIS IRQ LR Timer WDT /4 D K R Q IRQ EN/DIS LR WDT Timer and WDT configurations If an external clock is selected as the source of system frequency, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is re-moved. Buzzer tone output A simple tone generator is implemented in the VK1622A. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone. ommand format The VK1622A can be configured by the software setting. There are two mode commands to con-figure the VK1622A resource and to transfer the LD display data. The following are the data mode ID and the command mode ID: Operation Mode ID READ Date 110 WRITE Date 101 READ-MODIFY-WRITE Date 101 OMMAND ommand 100 If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive com-mand or the non-successive address data mode, the S pin should be set to 1, and the previous operation mode will be reset also. The S pin returns to 0, a new operation mode ID should be issued first. Name ommand ode Function TONE OFF X Turn-off tone output TONE 4K 010X-XXXX-X Turn-on tone output, tone frequency is 4KHz TONE 2K 0110-XXXX-X Turn-on tone output, tone frequency is 2KHz Title 4 5 Size B Date: File: Number 12-Jun-2006 E:\ 规格书 \ 规格图 \ 规格图 -0\Z 深圳市永嘉电子有公司第 9 页共 13 页

10 SG1622A Timing Diagrams 深圳市永嘉电子有公司第 10 页共 13 页

11 SG1622A Application ircuits S D RD VR WR DATA VLD u R BZ IRQ BZ Piezo OM0-OM7 SEG0-SEG31 1/4 bias,1/8 duty LD panel Note: The connection of IRQ and RD pin can be selected depending on the requirement of the u. The volatage applied to VLD pin must be lower than. Adjust VR to fit LD display, at =5V, VLD=4V, VR=15KΩ±20%. 深圳市永嘉电子有公司第 11 页共 13 页

12 Adjust R (external pull-high resistance)to fit user s time base clock. ommand Summary SG1622A Name ID ommand ode D/ Function Def READ 110 A5A4A3A2A1A0D0D1D2D3 D Read data from the RAM WRITE 101 A5A4A3A2A1A0D0D1D2D3 D Write data to the RAM READ- MODIFY- WRITE SYS DIS A5A4A3A2A1A0D0D1D2D3 D Read and write data to the RAM X 深圳市永嘉电子有公司第 12 页共 13 页 Turn off both system oscillator And LD bias generator SYS EN X Turn on system oscillator LD OFF X Turn off LD display Yes LD ON X Turn on LD display TIMER DIS X Disable time base output Yes WDT DIS X Disable WDT time-out flag output Yes TIMER EN X Enable time base output WDT EN X Enable WDT time-out flag output TONE OFF X Turn off tone outputs Yes LR TIMER X lear the contents of the time base Generator LR WDT X lear the contents of the WDT stage R 32K 100 EXT 32K XX-X XX-X System clock source, on-chip R Oscillator System clock source, external lock source TONE 4K X-XXXX-X Tone frequency output: 4KHz TONE 2K XXXX-X Tone frequency output: 2KHz Yes IRQ DIS X-0XXX-X Disable IRQ output IRQ EN X-1XXX-X Enable IRQ output F1 100 F2 100 F4 100 F8 100 F F X-0000-X 101X-0001-X 101X-0010-X 101X-0011-X 101X-0100-X 101X-0101-X Time base clock output: 1Hz The WDT time-out flag after: 4S Time base clock output: 2Hz The WDT time-out flag after: 2S Time base clock output: 4Hz The WDT time-out flag after: 1S Time base clock output: 8Hz The WDT time-out flag after: 1/2S Time base clock output: 16z The WDT time-out flag after: 1/4S Time base clock output: 32Hz The WDT time-out flag after: 1/8S F X-0110-X Time base clock output: 64Hz Yes Yes Yes

13 F X-0111-X SG1622A The WDT time-out flag after: 1/16S Time base clock output: 128Hz The WDT time-out flag after: 1/32S TEST X Test mode, user don t use NORMAL X Normal mode Yes Note: X: Don t care A5~A0: RAM address D3~D0: RAM data D/: Data/ommand mode Def: Power in reset denault All the bold forms, namely 110, 101 and 100, are mode commands. Of these, 100 indicates the command mode ID. If successive commands have been issued, the command mode ID ex-cept for the first command will be omitted. The source of the tone frequency and of the time base/wdt clock frequency can be derived from an on-chip 32KHz R oscillator or an external 32KHz clock. alculation of the frequency is based on the sys-tem frequency sources as stated above. It is recommended that the host controller should ini-tialize the VK1622A after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the VK1622A. Yes 深圳市永嘉电子有公司第 13 页共 13 页