DS1202, DS1202S. Serial Timekeeping Chip FEATURES PIN ASSIGNMENT. ORDERING INFORMATION DS pin DIP DS1202S 16 pin SOIC DS1202S8 8 pin SOIC

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1 DS22, DS22S Serial Timekeeping Chip FEATURES Real time clock counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap year compensation 2 x 8 RAM for scratchpad data storage Serial for minimum pin count volt full operation Uses less than 3 na at 2 volts Single-byte or multiple-byte (burst mode) data transfer for read or write of clock or RAM data 8-pin DIP or optional 6-pin SOIC for surface mount Simple 3-wire interface TTL-compatible (V CC = 5V) Optional industrial temperature range - C to +85 C OERING INFORMATION DS22 8 pin DIP DS22S 6 pin SOIC DS22S8 8 pin SOIC PIN ASSIGNMENT X X2 GND X X2 GND X X2 GND PIN DIP PIN SOIC (28 mil) 6 PIN SOIC V CC V CC V CC PIN DESCRIPTION No Connection X, X KHz Crystal Input GND Ground Reset Data Input/Output Serial Clock V CC Power Supply Pin DESCRIPTION The DS22 Serial Timekeeping Chip contains a real time clock/calendar and 2 bytes of static RAM. It communicates with a microprocessor via a simple serial interface. The real time clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with less than 3 days, including corrections for leap year. The clock operates in either the 2-hour or 2-hour format with an AM/PM indicator. Interfacing the DS22 with a microprocessor is simplified by using synchronous serial communication. Only three wires are required to communicate with the clock/ram: () (Reset), (2) (Data line), and (3) (Serial clock). Data can be transferred to and from the clock/ Copyright 995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. 95 /

2 RAM one byte at a time or in a burst of up to 2 bytes. The DS22 is designed to operate on very low power and retain data and clock information on less than microwatt. load the command word into the shift register, additional clocks will output data for a read or input data for a write. The number of clock pulses equals eight plus eight for byte mode or eight plus up to 92 for burst mode. OPERATION The main elements of the Serial Timekeeper are shown in Figure : shift register, control logic, oscillator, real time clock, and RAM. To initiate any transfer of data, is taken high and eight bits are loaded into the shift register providing both address and command information. Data is serially input on the rising edge of the. The first eight bits specify which of 32 bytes will be accessed, whether a read or write cycle will take place, and whether a byte or burst mode transfer is to occur. After the first eight clock cycles have occurred which COAND BYTE The command byte is shown in Figure 2. Each data transfer is initiated by a command byte. The MSB (Bit 7) must be a logic. If it is zero, further action will be terminated. Bit 6 specifies clock/calendar data if logic or RAM data if logic. Bits one through five specify the designated registers to be input or output, and the LSB (Bit ) specifies a write operation (input) if logic or read operation (output) if logic. The command byte is always input starting with the LSB (bit ). DS22 BLOCK DIAGRAM Figure KHz X X2 REAL TIME CLOCK OSCILLATOR AND DIVIDER INPUT SHIFT REGISTERS DATA BUS COAND AND CONTROL LOGIC ADDRESS BUS 2 X 8 RAM ADDRESS/COAND BYTE Figure RAM CK A A3 A2 A A 95 2/

3 RESET AND CLOCK CONTROL All data transfers are initiated by driving the input high. The input serves two functions. First, turns on the control logic which allows access to the shift register for the address/command sequence. Second, the signal provides a method of terminating either single byte or multiple byte data transfer. A clock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, data must be valid during the rising edge of the clock and data bits are output on t he falling edge of clock. All data transfer terminates if the input is low and the pin goes to a high impedance state. Data transfer is illustrated in Figure 3. DATA INPUT Following the eight cycles that input a write command byte, a data byte is input on the rising edge of the next eight cycles. Additional cycles are ignored should they inadvertently occur. Data is input starting with bit. DATA OUTPUT Following the eight cycles that input a read command byte, a data byte is output on the falling edge of the next eight cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written. Additional cycles retransmit the data bytes should they inadvertently occur so long as remains high. This operation permits continuous burst mode read capability. Data is output starting with bit. BU MODE Burst mode may be specified for either the clock/calendar or the RAM registers by addressing location 3 decimal (address/command bits one through five = logical one). As before, bit six specified clock or RAM and bit specifies read or write. There is no data storage capacity at locations 8 through 3 in the Clock/Calendar Registers or locations 2 through 3 in the RAM registers. hen writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred. However, when writing to RAM in burst mode it is not necessary to write all 2 bytes for the data to transfer. Each byte that is written to will be transferred to RAM regardless of whether all 2 bytes are written or not. CLOCK/CALENDAR The clock/calendar is contained in eight write/read registers as shown in Figure. Data contained in the clock/ calendar registers is in binary coded decimal format (BCD). CLOCK HALT FLAG Bit 7 of the seconds register is defined as the clock halt flag. hen this bit is set to logic, the clock oscillator is stopped and the DS22 is placed into a low-power standby mode with a current drain of not more than nanoamps. hen this bit is written to logic, the clock will start. AM-PM/2-2 MODE Bit 7 of the hours register is defined as the 2- or 2-hour mode select bit. hen high, the 2-hour mode is selected. In the 2-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 2-hour mode, bit 5 is the second hour bit (2-23 hours). RITE PROTECT REGISTER Bit 7 of write protect register is the write protect bit. The first seven bits (bits -6) are forced to zero and will always read a zero when read. Before any write operation to the clock or RAM, bit 7 must be zero. hen high, the write protect bit prevents a write operation to any other register. CLOCK/CALENDAR BU MODE The clock/calendar command byte specifies burst mode operation. In this mode the eight clock/calendar registers can be consecutively read or written (see Figure ) starting with bit of address. RAM The static RAM is 2 x 8 bytes addressed consecutively in the RAM address space. RAM BU MODE The RAM command byte specifies burst mode operation. In this mode, the 2 RAM registers can be consecutively read or written (see Figure ) starting with bit of address. 95 3/

4 REGISTER SUARY A register data format summary is shown in Figure. CRYSTAL SELECTION A KHz crystal, Daiwa Part No. DT26S, Seiko Part No. DS-VT-2 or equivalent, can be directly connected to the DS22 via pins 2 and 3 (X, X2). The crystal selected for use should have a specified load capacitance (CL) of 6 pf. The crystal is connected directly to the X and X2 pins. There is no need for external capacitors or resistors. Note: X and X2 are very high impedance nodes. It is recommended that they and the crystal be guard ringed with ground and that high frequency signals be kept away from the crystal area. For more information on crystal selection and crystal layout considerations, please consult Application Note 58, Crystal Considerations with Dallas Real Time Clocks. DATA TRANSFER SUARY Figure 3 SINGLE BYTE TRANSFER R/ A A A2 A3 A R/C ADDRESS COAND DATA INPUT/OUTPUT BU MODE TRANSFER R/ R/C ADDRESS COAND DATA BYTE DATA BYTE N FUTION BYTE N n CLOCK 8 72 RAM /

5 REGISTER ADDRESS/DEFINITION Figure REGISTER ADDRESS A. CLOCK REGISTER DEFINITION SEC 59 CH SEC SEC MIN 59 MIN MIN HR 2 2/ 23 2 A/P HR HR DATE 28/ DATE DATE MONTH 2 M MONTH DAY 7 DAY YEAR 99 YEAR YEAR CONTROL P FORCED TO ZERO CLOCK BU B. RAM RAM RAM DATA RAM 23 RAM DATA 23 RAM BU 95 5/

6 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground.3V to +7.V Operating Temperature C to 7 C Storage Temperature 55 C to +25 C Soldering Temperature 26 C for seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOENDED DC OPERATING CONDITIONS ( C to 7 C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Voltage V CC V Logic Input V IH 2. V CC +.3 V V CC =2.V Logic Input V IL V CC =5V V DC ELECTRICAL CHARACTERISTICS ( C to 7 C; V CC = 2. to 5.5V*) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage I LI +5 µa 6 Leakage I LO +5 µa 6 V CC =2V.6 Logic Output V OH V CC =5V 2. V 2 V CC =2V. Logic Output V OL V CC =5V. V CC =2V. Active Supply Current I CC V CC =5V.2 V CC =2V.3 Timekeeping Current I CC V CC =5V V CC =2V Leakage Current I CC2 V CC =5V V 3 ma 5 µa na *Unless otherwise noted. CAPACITAE (t A = 25 C) PARAMETER SYMBOL CONDITION TYP MAX UNITS NOTES Input Capacitance C I 5 pf Capacitance C pf Crystal Capacitance C X 6 pf 95 6/

7 AC ELECTRICAL CHARACTERISTICS ( C to 7 C; V CC = 2. to 5.5V*) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES V CC =2V 2 Data to CLK Setup t DC V CC =5V 5 ns 7 V CC =2V 28 CLK to Data Hold t CDH V CC =5V 7 V CC =2V 8 CLK to Data Delay t CDD V CC =5V 2 V CC =2V CLK Low Time t CL V CC =5V 25 V CC =2V CLK High Time t CH V CC =5V 25 V CC =2V.5 CLK Frequency f CLK V CC =5V DC 2. V CC =2V 2 CLK Rise and Fall t R, t F V CC =5V 5 V CC =2V to CLK Setup t CC V CC =5V V CC =2V CLK to Hold t CCH V CC =5V 25 V CC =2V Inactive Time t CH V CC =5V V CC =2V 28 to High Z t CDZ V CC =5V 7 ns 7 ns 7, 8, 9 ns 7 ns 7, 2 MHz 7, 2 ns µs 7 ns 7 µs 7 ns 7 *Unless otherwise noted. 95 7/

8 TIMING DIAGRAM: READ DATA TRANSFER Figure 5 RESET t CC CLOCK t CDH t CDD t DC t CDZ DATA INPUT/ OUTPUT 7 COAND BYTE TIMING DIAGRAM: RITE DATA TRANSFER Figure 6 t CH RESET t CC t CL t R t F t CCH CLOCK t CDH t CH t DC DATA INPUT/ OUTPUT 7 COAND BYTE NOTES:. All voltages are referenced to ground. 2. Logic one voltages are specified at a source current of ma at V CC =5V and. ma at V CC =2V, V OH =V CC for capacitive loads. 3. Logic zero voltages are specified at a sink current of ma at V CC =5V and.5 ma at V CC =2V.. I CC is specified with open, set to a logic, and clock halt flag= (oscillator enabled). 5. I CC is specified with the pin open, high, =2 MHz at V CC =5V; =5 KHz, V CC =2V and clock halt flag= (oscillator enabled). 6.,, and all have KΩ pulldown resistors to ground. 7. Measured at V IH =2.V or V IL =.8V and ms maximum rise and fall time. 8. Measured at V OH =2.V or V OL =.V. 9. Load capacitance = 5 pf. 95 8/

9 . I CC2 is specified with,, and open. The clock halt flag must be set to logic one (oscillator disabled).. At power up, must be at a logic until V CC 2 volts. Also, must be at a logic when is driven to a logic one state. 2. If t CH exceeds ms with in a logic one state, then I CC may briefly exceed I CC specification. DS22 SERIAL TIMEKEEPER 8 PIN DIP 8 5 PKG 8 PIN DIM MIN MAX B A IN..36. B IN A C IN..2. D IN C E IN..5. F IN... K G E F G IN..9. H IN J IN..8.2 K IN..5.2 D J H 95 9/

10 DS22S SERIAL TIMEKEEPER 6 PIN SOIC K G F B H phi J L PKG 6-PIN DIM MIN MAX A C A IN B IN E C IN E IN F IN G IN..5 BSC.27 BSC H IN J IN K IN L IN phi 8 95 /

11 DS22S8 8 PIN SOIC 2 MIL K G B H J F 8 deg. typ. L PKG 8-PIN E A C DIM MIN MAX A IN B IN C IN E IN F IN G IN..5 BSC.27 BSC H IN J IN K IN L IN /