INTRODUCTION FEATURES ORDERING INFORMATION APPLICATIONS LOW POWER DTMF RECEIVER 18 DIP 300A

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1 LOW POWER DTMF RECEIVER INTRODUCTION The is a complete Dual Tone Multiple Frequency (DTMF) receiver that is fabricated by low power CMOS and the Switched- Capacitor Filter technology. This LSI consists of band split filters, which separates counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. It decodes all DTMF tone pairs into a bits digital code. The externally required components are minimized by on chip provision of a differential input AMP, clock oscillator and latched three state interface. The on chip clock generator requires only a low cost TV crystal as an external component. DIP 00A 0 SOP FEATURES Detects all standard tones. Low power consumption: mw (Typ) Single power supply: V Uses inexpensive.mhz crystal Three state outputs for microprocessor interface Good quality and performance for using in exchange system Power down mode/input inhibit ORDERING INFORMATION Device Package Operating X0-D0B0 DIP 00A C + C X0-S0B0 0 SOP APPLICATIONS PABX Central Office Paging Systems Remote Control Credit Card Systems Key Phone System Answering Phone Home Automation System Mobile Radio Remote Data Entry

2 LOW POWER DTMF RECEIVER PIN CONFIGURATION IN+ V DD IN+ 0 V DD IN- IN- 9 GS GS V REF DSO V REF DSO I IN Q I IN NC PDN Q PDN Q OSC Q NC Q OSC Q OSC Q GND 9 0 OE OSC 9 Q GND 0 OE (-DIP) (0-SOP) PIN DESCRIPTION Pin No Symbol Description IN + Non inverting input of the internal amp. IN Inverting input of the internal amp. GS Gain Select. The output used for gain adjustment of analog input signal with a feedback resistor. V REF Reference Voltage output (V DD /, Typ) can be used to bias the internal amp input of V DD /. I IN Input inhibit. High input states inhibits the detection of tones. This pin is pulled down internally. PDN Control input for the stand-by power down mode. Power down occurs when the signal on this input is in high states. This pin is pulled down internally.

3 LOW POWER DTMF RECEIVER PIN DESCRIPTION (Continued) Pin No Symbol Description, OSC OSC 9 GND Ground pin. Clock input/output. A inexpensive.9mhz crystal connected between these pins completes internal oscillator. Also, external clock can be used. 0 OE Output Enable input. Outputs Q-Q are CMOS push-pull when OE is High and open circuited (High impedance) when disabled by pulling OE low. Internal pull up resistor built in. - Q - Q Three state data output. When enabled by OE, these digital outputs provide the hexadecimal code corresponding to the last valid tone pair received. DSO Delayed Steering Output. Indicates that valid frequencies have been present for the required guard time, thus constituting a valid signal. Presents a logic high when a received tone pair has been registered and the output latch is updated. Returns to logic low when the voltage on falls below V TH. Early Steering Outputs. Indicates detection of valid tone output a logic high immediately when the digital algorithm detects a recognizable tone pair. Any momentary loss of signal condition will cause to return to low. Steering Input/Guard Time Output. A voltage greater the V TS detected at SI causes the device to register the detected tone pair and update the output latch. A voltage less than V TS frees the device to accept a new tone pair. The GTO output acts to reset the external steering time constant, and its state is a function of and the voltage on SI V DD Power Supply (+V, Typ) ABSOLUTE MAXIMUM RATINGS Characteristics Symbol Value Unit Power Supply Voltage V DD V Analog Input Voltage Range V I (A) 0. V DD + 0. V Digital Input Voltage Range V I (D) 0. V DD + 0. V Output Voltage Range V O 0. V DD + 0. V Current On Any Pin I I 0 V Operating Temperature T OPR 0 + ma Storage Temperature T STG C

4 LOW POWER DTMF RECEIVER ELECTRICAL CHARACTERISTICS (V DD = V, Ta = C, unless otherwise noted) Characteristic Symbol Test Conditions Min. Typ. Max. Unit Operating Voltage V DD.. V Operating Current I DD ma Power Dissipation P D mw Input Voltage Low V IL. V Input Voltage High V IH. V Input Leakage Current I I (LKG) V IN = GND or V DD 0. m Pull Up Current On OE Pin I PU OE = GND. µa Analog Input Impedance R I f IN = KHz 0 MΩ Steering Input Threshold Voltage V TH.. V Output Voltage Low V OL No Load 0.0 V V OH No Load.9 V Output Current (Sinking) I O (SINK) V OL = 0.V. ma Output Current (Sourcing) I O (SOURCE) V OH =.V ma V REF Output Voltage V O (REF).. V V REF Output Resistance R O (REF) 0 KΩ Analog Input Offset Voltage V IO mv Power Supply Rejection Ratio PSRR Gain Setting Amp at KHz 0 db Common Mode Rejection Ratio CMRR.0V < V IN <.0V 0 db Open Loop Voltage Gain G V Gain Setting Amp at KHz db Open Loop Unit Gain Bandwidth BW. MHz Analog Output Voltage Swing V O (P-P) R L = 00K. V P-P Acceptable Capacitive Load C L GS 00 pf Acceptable Resistive Load R L GS 0 KΩ Analog Input Common Mode Voltage Range Valid Input Signal Range (each tone of composite signal) V CM No Load.0 V P-P V I(VAL) 9.0 dbm Dual Tone Twist Accept TW ±0 db Acceptable Frequency Deviation f ±.% ± Hz Frequency Deviation Reject f R ±.%

5 LOW POWER DTMF RECEIVER ELECTRICAL CHARACTERISTICS (Continued) (V DD = V, Ta = C, unless otherwise noted) Characteristic Symbol Test Conditions Min. Typ. Max. Unit Third Tone Tolerance Trd db Noise Tolerance TN db Dial Tone Tolerance DT db Crystal Clock Frequency f CK.9.9. MHz Maximum Clock Input Rise Time t R(MAX) External Clock 0 ns Maximum Clock Input Fall Time t F(MAX) External Clock 0 ns Acceptable Clock Input Duty Cycle D CK External Clock % Acceptable Capacitive Load D L OSC PIN 0 pf Tone Present Detect Time t DET(P) ms Tone Absent Detect Time t DET(A) 0.. ms Minimum Tone Duration Accept t TDA(MIN) User Adjustable 0 ms Minimum Tone Duration Reject t TDR(MAX) User Adjustable 0 ms Acceptable Interdigit Pause t IDP(A) User Adjustable 0 ms Rejectable Interdigit Pause t IDP(R) User Adjustable 0 ms Propagation Delay Time SI to Q t D(SI-Q) OE = High µs Propagation Delay Time SI to DSO t D(SI-D) OE = High µs Output Data Setup Q to DSO t SU OE = High. µs Propagation Delay Time OE to Q (Enable) Propagation Delay Time OE to Q (Disable) t D(QE-Q)EN RL = 0K, CL = 0pF 0 0 ns t D(QE-Q)DIS RL = 0K, CL = 0pF 00 ns NOTES:. Digit sequence consists of all DTMF tones.. Tone duration = 0mS, Tone pause = 0mS.. Nominal DTMF frequencies are used.. Both tones in the composite signal have an equal amplitude.. Tone pair is deviated by ±.% ± Hz.. Bandwidth limited (KHz) Gaussian Noise.. The precise dial tone frequencies are (0Hz and 0Hz) ± %.. For an error rate of better than in Referenced to lowest level frequency component in DTMF signal. 0. Minimum signal acceptance level is measured with specified maximum frequency deviation.. This item also applies to a third tone injected onto the power supply.. Referenced to Fig. Input DTMF tone level at -dbm.

6 f LOW POWER DTMF RECEIVER TEST CIRCUIT * 0 # 9 X - tal 9 ST0C KS00 0 R VCC 00K R 00K 0.µF X - tal Fig. 9 0 KT0 R C 00K LED HLHCTLS0 0 9 VCC V CC V CC b c LT RDO ABI d GND HLLS VCC g a c d 0 9 VCC R0 R9 R R R R R 0 9 g f com a b a d com c dp VCC LTSR Figure. Test Circuit

7 LOW POWER DTMF RECEIVER TIMING DIAGRAM ttdr (MAX) ttda (MIN) tidp (A) tidp (R) DTMF #n DTMF #n + DTMF #n + DTMF INPUT tdet (P) tdet (A) tpgt tagt VTH tsu DECODED TONE # (n - ) Q - Q td (SI-D) DSO td (OE-Q) EN td (OE-Q) DIS OE Figure. Timing Diagram

8 LOW POWER DTMF RECEIVER DIGITAL OUTPUT Outputs Q-Q are CMOS push pull when enabled (EO = High) and open circuited (high impedance) when disabled by pulling EO = Low. These digital outputs provide the hexadecimal code corresponding to the DTMF signals. The table below describes the hexadecimal. NO Low Frequency High Frequency OE Q Q Q Q 9 09 H H H H H H H 0 H H H 0 0 * 9 09 H 0 # 9 H 0 0 A 9 H 0 B 0 H 0 C H D 9 H ANY - - L Z Z Z Z NOTE: Z : High Impedance H : High Logic Level L : Low Logic Level

9 LOW POWER DTMF RECEIVER APPLICATION CIRCUIT +V IN+ V DD 0.uF 00K IN- 0.uF 00K.MHz GS V REF I IN PDN OSC DSO Q Q Q 00K 0nF C 0nF 00K R 00K C R R.K R IN+ IN- GS R 00K 0K VREF + _ OSC Q GND OE All resistors are % tolerance All capacitors are % tolerance Figure. Single Ended Input Configuration R = RR/(R+R), VOLTAGE GAIN = R/R INPUT IMPEDANCE : R + (/wc) All resistors are % tolerance All resistors are % tolerance All capacitors are % tolerance Figure. Differential Ended Input Configuration 9

10 LOW POWER DTMF RECEIVER V DD C C R R R R t PGT = (RC) In (V DD /V DD -V TH ) t AGT = (RPC) In (V DD /V TST ) R P = RR/(R + R) Decreasing t AGT (t PGT > t AGT ) t PGT = (RPC) In (V DD /V DD -V TH ) t AGT = (RC) In (V DD /V TH ) R P = RR (R + R) Decreasing t PGT (t PGT < t AGT ) Figure. Guard Time Adjustment OSC OSC 0pF.9MHz OSC OSC TO OSC of next Figure. Oscillator Connection 0

11 This datasheet has been downloaded from: Datasheets for electronic components.