Current-mode PWM controller

Transcription

1 DESCRIPTION The is available in an 8-Pin mini-dip the necessary features to implement off-line, fixed-frequency current-mode control schemes with a minimal external parts count. This technique results in improved line regulation, enhanced load response characteristics, and a simpler, easier to design control loop. Topological advantages include inherent pulse-by-pulse current limiting. Protection circuitry includes built-in undervoltage lock-out and current limiting. Other features include fully-latched operation, a % trimmed bandgap reference, and start-up current less than ma. These devices feature a totem-pole output designed to source and sink high peak current from a capacitive load, such as the gate of a power MOSFET. Consistent with N-channel power devices, the output is low in the OFF-state. FEATURES Low start-up current ( ma) Automatic feed-forward compensation Pulse-by-pulse current limiting Enhanced load response characteristics Undervoltage lock-out with hysteresis Double pulse suppression High current totem-pole output Internally-trimmed bandgap reference 00kHz operation, guaranteed min PIN CONFIGURATIONS NC NC NC N Package TOP VIEW D Package TOP VIEW APPLICATIONS Off-line switched mode power supplies DC-to-DC converters GROUND NC V C GROUND POWER GROUND BLOCK DIAGRAM () () (9) V V UVLO V S/R V REF 8().0V 0mA.V INTERNAL BIAS () OSC (0) CURRENT SENSE () () () ERROR AMP + R R V S R CURRENT SENSE ARATOR PWM LATCH Pin numbers in parentheses refer to the D package. (8) August,

2 ORDERING INFORMATION DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG # 8-Pin Plastic Dual In-Line Package (DIP) 0 to +0 C N 00B -Pin Plastic Small Outline (SO) Package 0 to +0 C D 00B ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT Supply voltage (I CC <0mA) Self-Limiting Supply voltage (low impedance source) 0 V I OUT Output current, ± A Output energy (capacitive load) µj Analog inputs (Pin, Pin ) -0. to. V Error amp output sink current 0 ma P D Power dissipation at T A 0 C W (derate.mw/ C for T A >0 C) T STG Storage temperature range - to +0 C T SOLD Lead temperature (soldering, 0sec max) NOTES:. All voltages are with respect to Pin ; all currents are positive into the specified terminal.. See section in application note on Power Dissipation Calculation.. This parameter is guaranteed, but not 00% tested in production. 00 C August, 99 0

3 DC AND AC ELECTRICAL CHARACTERISTICS 0 T J 0 C for ; =V; R T =0kW; C T =.nf, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS Reference section Min Typ Max V OUT Output voltage T J = C, I O =ma V Line regulation V IN V 0 mv Load regulation I O 0mA mv UNIT Temp. stability mv/ C Total output variation Line, load, temp..8.8 V V NOISE Output noise voltage 0Hz f 0kHz, T J = C 0 µv Oscillator section Error amp section Long-term stability T J = C, 000 Hrs. mv Output short-circuit T J = ma Output short-circuit -<T J 0 C ma Initial accuracy T J = C khz Voltage stability V 0. % Temp. stability T MIN T J T MAX % Amplitude V PIN peak-to-peak. V Input voltage V Pin =.V..0.8 V I BIAS Input bias current µa A VOL V O V 90 db Unity gain bandwidth T J = C 0. MHz Unity gain bandwidth T MIN <T J <T MAX 0. MHz PSRR Power supply rejection ratio V 0 0 db I SINK Output sink current V PIN =.V, V PIN =.V ma I SOURCE Output source current V PIN =.V, V PIN =V ma V OUT High V PIN =.V, R L =k to ground V V OUT Low V PIN =.V, R L =k to Pin V Current sense section Gain,.8. V/V Maximum input signal V PIN =V 0.9. V PSRR Power supply rejection ratio V 0 db I BIAS Input bias current - -0 µa Delay to output 0 00 ns August, 99 0

4 DC AND AC ELECTRICAL CHARACTERISTICS 0 T J 0 C for ; = ; R T =0kΩ; C T =.nf, unless otherwise specified SYMBOL PARAMETER TEST CONDITIONS Output section V OL V OH Output Low-Level Output High-Level Min Typ Max I SINK =0mA I SINK =00mA.. I SOURCE =0mA. I SOURCE =00mA. t R Rise time C L =nf 0 0 ns t F Fall time C L =nf 0 0 ns Undervoltage lockout section PWM section Start threshold.. V Min. operating voltage after turn on V Maximum duty cycle Minimum duty cycle 0 Total standby current Start-up current 0. ma I CC Operating supply current V PIN =V PIN =0V ma zener voltage I CC =ma V Maximum operating frequency section Maximum operating frequency for all functions operating cycle-by-cycle NOTES:. These parameters, although guaranteed, are not 00% tested in production.. Parameter measured at trip point of latch with V PIN =0.. Gain defined as: A V PIN ; 0 V V PIN 0.8V PIN UNIT V V % 00 khz UNDERVOLTAGE LOCKOUT ERROR AMP CONFIGURATION ON/OFF COMMAND TO REST OF IC.V + 0.mA I CC V ON V OFF V 0V Z I Error AMP can source or sink up to 0.mA. <ma <ma V OFF V ON During Undervoltage Lock-Out, the output driver is biased to a high impedance state. Pin should be shunted to ground with a bleeder resistor to prevent activating the power switch with output leakage current. August, 99 0

5 CURRENT SENSE CIRCUIT I S ERROR AMP R R V CURRENT SENSE ARATOR R S R CURRENT SENSE Peak current (I S ) is determined by the formula: I S MAX.0V R s A small RC filter may be required to suppress switch transients. TYPICAL PERFORMANCE CHARACTERISTICS Output Saturation Characteristics 00 Error Amplifier Open-Loop Frequency Response SATURATION VOLTAGE (V) VOLTAGE GAIN (db) Av PHASE (DEG) CURRENT, SOURCE OR SINK (A) k 0k 00k M 0M FREQUENCY (Hz) August, 99 0

6 OPEN-LOOP LABORATORY TEST FIXTURE R T A.k N 00k 8 0.µF ERROR AMP ADJUST.k k ADJUST 0.µF k W C T High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to Pin in a single point ground. The transistor and k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to Pin. SHUTDOWN TECHNIQUES.k 8.k 00 SHUTDOWN SHUTDOWN TO CURRENT SENSE RESISTOR Shutdown of the can be accomplished by two methods; either raise Pin above V or pull Pin below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to Block Diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at Pins and/or is removed. In the examples shown, an externally-latched shutdown may be accomplished by adding an SCR which will be reset by cycling below the lower UVLO threshold (0V). At this point all internal bias is removed, allowing the SCR to reset. August, 99 0

7 OFF-LINE FLYBACK REGULATOR. W T USD + - 0µF 0V k W.k W 0.0µF 00V N 00µF 0V DC (V A) OUT AC INPUT N V 0k 0.0µF 0µF 0V N 80pF.k.k 0k 00pF 8 0k OUT CUR SEN 0pF 0k k UFN 0.8 NOTES: T: Coilcraft E-0-B Primary 9 turns single AWG Secondary turns parallel AWG control 9 turns parallel AWG8 0.0µF 0.00µF ISOLATION BOUNDARY SPECIFICATIONS Input line voltage: 90V AC to 0V AC Input frequency: 0 or 0Hz Switching frequency: 0kHz±0% Output power: W maximum Output voltage: V±% Output current: to A Line regulation: 0.0%/V Load regulation: 8%/A * W, V IN =90V AC : 0% V IN =0V AC : % Output short-circuit current:.a average This circuit uses a low-cost feedback scheme in which the DC voltage developed from the primary-side control winding is sensed by the error amplifier. Load regulation is therefore dependent on the coupling between secondary and control windings, and on transformer leakage inductance. For applications requiring better load regulation, a UC90 Isolated Feedback Generator can be used to directly sense the output voltage. August, 99 0

8 SYNCHRONIZATION AND MAXIMUM DUTY CYCLE CLAMP V 8 R A RESET DISCH R B NE OUT TRIG THRESH C NOTES: f. (R A R B ) C TO OTHER s R B D MAX R A R B August, 99 0

9 This datasheet has been download from: Datasheets for electronics components.