MB1504/MB1504H/MB1504L ASSP SERIAL INPUT PLL FREQUENCY SYNTHESIZER

Size: px

Start display at page:

Download "MB1504/MB1504H/MB1504L ASSP SERIAL INPUT PLL FREQUENCY SYNTHESIZER"

Earl Clarke
5 years ago
Views:

1 D4 23 5E DATA HEET MB54/MB54H/MB54L AP ERIAL INPUT PLL FREQUENCY YNTHEIZER ERIAL INPUT PLL FREQUENCY YNTHEIZER WITH 52MHz PRECALER The Fujitsu MB54/MB54H/MB54L, utilizing BI-CMO technology, is a single chip serial input PLL frequency synthesizer with pulse-swallow function. The MB54 series contains a 52MHz two modulus prescaler that can select either 32/33 or 64/65 divide ratio; control signal generator; 6-bit shift register; 5-bit latch; programmable reference divider (binary 4-bit programmable reference counter); -bit switch counter; phase comparator with phase inverse function; charge pump; crystal oscillator; 9-bit shift register; 8-bit latch; and a programmable divider (binary 7-bit swallow counter and binary -bit programmable counter). The MB54 operates from a low supply voltage (3 typ) and consumes low power (3mW at 52MHz). MB54 Product Line MB54 P oltage OOP oltage Lock up Time 8 max 8.5 max Middle speed Output Width Middle High-level Output Current Middle Low-level Output Current Middle PLATIC PACKAGE DIP-6P-M4 MB54H max. max High speed Low High Low MB54L 8 max 8.5 max Low speed High Low High FEATURE High operating frequency: f IN MAX =52MHz ( IN MIN =.2 P-P ) On-chip prescaler Low power supply voltage: 2.7 to 5.5 (3. typ) Low power supply consumption: 3mW (3., 52MHz operation) erial input 8-bit programmable divider consisting of: Binary 7-bit swallow counter (Divide ratio: to 27) Binary -bit programmable counter (Divide ratio: 6 to 247) erial input 5-bit programmable reference divider consisting of: Binary 4-bit programmable reference counter (Divide ratio: 8 to 6383) -bit switch counter (W) ets divide ratio of prescaler 2 types of phase detector output On-chip charge pump (Bipolar type) Output for external charge pump Wide operating temperature: T A = 4 C to +85 C PLATIC PACKAGE FPT-6P-M6 This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Copyright 994 by FUJITU LIMIED

2 2 MB54 MB54H MB54L PIN AIGNMENT OC IN 6 ØR OC OUT 2 5 ØP P 3 4 f P CC 4 5 ( TOP IEW ) 3 2 f r FC GND 6 LE LD 7 Data f in 8 9 Clock ABOLUTE MAXIMUM RATING (see NOTE) Rating ymbol Condition alue Unit CC.5 to +7. Power upply oltage PH MB54H CC to 2. P, PL MB54/54L CC to. Output oltage OUT.5 to CC +.5 Open-drain Output OOPH MB54H.5 to. OOP, OOPL MB54/54L.5 to 9. Output Current I OUT + ma torage Temperature T TG 55 to +25 C NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

3 3 MB54 MB54H MB54L MB54/MB54H/MB54L BLOCK DIAGRAM CC GND Bit hift Register 6-Bit hift Register 5-Bit Latch 3 f r LE 5-Bit Latch 2 FC 7 LD OC IN Crystal Oscillator Circuit Programmable Reference Divider Binary 4-Bit Reference Counter -bit W Phase Comparator 6 5 ØR ØP OC OUT 2 9-Bit hift Register 9-Bit hift Register Charge Pump 3 P 5 f IN 8 Prescaler Circuit 7-Bit Latch 8-Bit Latch -Bit Latch 4 f P Programmable Divider Data Control -Bit Latch Binary 7-Bit wallow Counter Binary -Bit Programmable Counter Clock 9 Control Circuit

4 4 MB54 MB54H MB54L PIN DECRIPTION Pin No. Pin Name I/O Descriptions 2 OC IN OC OUT I O Oscillator input Oscillator output A crystal is placed between OC IN and OC OUT. 3 P Power supply input for charge pump 4 CC Power supply voltage input 5 O Charge pump output The phase characteristics can be inversed depending upon the FC input. 6 GND Ground 7 LD O Phase comparator output This pin outputs high when the phase is locked. While the phase difference of f r and f p exists, the output level goes low. 8 f IN I Prescaler input The connection with an external CO should be an AC connection. 9 Clock I Clock input for 9-bit shift register and 6-bit shift register Each rising edge of the clock shifts one bit of data into the shift registers. Data I erial data of binary code input The last bit of the data is a control bit. The last data bit specifies which latch is activated. When the last bit is high level and LE is high-level, data is transferred to the 5-bit latch. When the last bit is low level and LE is high level, data is transferred to the 8-bit latch. LE I Load enable input (with internal pull up resistor) When LE is high level (or open), data stored in the shift register is transferred to the latch depending on the control data. 2 FC O Phase selecting input of phase comparator (with internal pull up resistor) When FC is low level, the charge pump and phase detector characteristics can be inversed. 3 f r O Monitor pin of phase comparator input It is the same as the programmable reference divider output. 4 f P O Monitor pin of phase comparator input It is the same as the programmable divider output. 5 6 ØP ØR O O Outputs for external charge pump The phase characteristics can be inversed depending on the FC input. The ØP pin is an N-channel open-drain output.

5 5 FUNCTIONAL DECRIPTION MB54 MB54H MB54L ERIAL DATA INPUT erial data input is input using the Data pin, Clock pin and LE pin. The 5-bit programmable reference divider and 8-bit programmable divider are controlled, respectively. On rising edge of the clock, one bit of the data shifts into the internal shift registers. When load enable (LE) is high level (or open), data stored in the shift registers is transferred to the 5-bit latch or 8-bit latch depending upon the control bit level. Control data H : Data is transferred into the 5-bit latch. Control data L : Data is transferred into the 8-bit latch. PROGRAMMABLE REFERENCE DIIDER The programmable reference divider consists of a 6-bit shift register, 5-bit latch and 4-bit reference counter. erial 6-bit data format is shown below. Data input Last data input Control bit LB Divide ratio of prescaler setting bit MB First data input C W Divide ratio of programmable reference counter setting bits 4-BIT PROGRAMMABLE REFERENCE COUNTER DIIDE RATIO Divide ratio R Divide ratio less than 8 is prohibited Divide ratio R: 8 to 6383 W: Divide ratio of prescaler setting bit W= H : 32 W= L : 64 to 4 : Divide ratio of programmable reference counter setting bits (8 to 6383) C: Control bit (control bit is set to high)

6 6 MB54 MB54H MB54L FUNCTIONAL DECRIPTION PROGRAMMABLE DIIDER The programmable divider consists of a 9-bit shift register, 8-bit latch, 7-bit swallow counter and -bit programmable counter. erial 9-bit data format is shown below. Last data input Control bit LB Data input MB First data input C Divide ratio of swallow counter setting bits Divide ratio of programmable counter setting bits 7-BIT WALLOW COUNTER DIIDE RATIO -BIT PROGRAMMABLE COUNTER DIIDE RATIO Divide ratio A Divide ratio N Divide ratio A : to 63 Divide ratio less than 6 is prohibited Divide ratio N : 6 to to 8 : Divide ratio of programmable counter setting bits (6 to 247) to 7 : Divide ratio of swallow counter setting bits ( to 27) C: Control bit (control bit is set to low) Data is input from the MB.

7 7 MB54 MB54H MB54L ERIAL DATA INPUT TIMING Data 8=MB 7 9 =LB C: Control bit *(W) (4) (8) (7) () (C: Control bit) Clock LE t t 2 t 3 t 4 t 5 t t 5 µs On the rising edge of the clock, one bit of the data shifts into the shift registers. Data in ( ) is used for setting the divide ratio of the programmable reference divider. PHAE CHARACTERITIC The FC pin (pin 2) is provided to inverse the phase comparator characteristics. The characteristics of the internal charge pump output ( ), and phase detector outputs (ØR, ØP) can be inversed depending upon the FC input data. Outputs are shown below. f r >f p f r <f p f r =f p FC=H (or open) FC=L ØR ØP ØR ØP H L L L H Z L H Z H Z L Z Z L L L Z CO CHARACTERITIC CO OUTPUT FREQUENCY 2 Note: Z=(High impedance) CO INPUT OLTAGE Depending upon CO characteristics, FC pin should be set accordingly: When CO characteristics are like, FC should be set high or open circuit; When CO characteristics are like 2, FC should be set Low.

8 8 MB54 MB54H MB54L RECOMMENDEPERATING CONDITION Parameter Power upply oltage Open-drain Output Input oltage ymbol CC alue Min Typ Max PH MB54H CC. P, PL MB54 MB54L CC 8.5 OOPH MB54H CC. OOP, OOPL MB54 MB54L CC 8.5 IN GND CC Unit Operating Temperature T A C HANDLING PRECAUTION This device should be transported and stored in anti-static containers. This is a static-sensitive device; take proper anti-ed precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats. Always turn the power supply off before inserting or removing the device from its socket. Protect leads with a conductive sheet when handling or transporting PC boards with devices.

9 9 ELECTRICAL CHARACTERITIC ( CC =2.7 to 5.5, T A = 4 to +85 C) MB54 MB54H MB54L Parameter Pin Name ymbol Condition alue Min Typ Max Unit Power upply Current CC I CC * 6 ma Operating Frequency f IN OC IN f IN f OC * MHz MHz Pf IN CC =2.7 to 4. 6 Input ensitivity f IN Pf IN dbm CC =4. to 5.5 dbm OC IN IN.5 P-P High-level Input oltage Low-level Input oltage Except f IN and OC IN IH IL.7x CC.3x CC High-level Input Current Low-level Input Current Data, Clock I IH I IL.. µa µa Input Current OC IN LE, FC I IN I LE ±5 6 µa µa High-level Output oltage Low-level Output oltage Except and OC OUT OH OL CC = N-channel Open-drain Cutoff Current ØP I OFF CC P 8. µa High-level Output Current Except I OH. ma and Low-level Output Current OC OUT I OL. ma High-level Output Current Low-level Output Current Leakage Current I DOHH I DOH I DOHL I DOLH I DOL I DOLL I DOZ Note: * CC =3., f IN =52MHz, f OC =2MHz crystal. Inputs are grounded except f IN, and outputs are open. *2 Input coupling capacitor pf is connected., ØP MB54H MB54 MB54L MB54H MB54 MB54L CC =3 P =2, T A =+25 C CC =3 P =6, T A =+25 C CC =3 P =2, T A =+25 C CC =3 P =6, T A =+25 C CC =3 P =2, T A =+25 C ma ma ma ma ma ma µa

10 MB54 MB54H MB54L TYPICAL CHARACTERITIC CURE CHARGE PUMP CHARACTERITIC MB54/MB54H MB54L 3.6kΩ kω P 2kΩ kω P 24.8kΩ 2kΩ 2kΩ GND kω GND LOCK UP TIME MEAUREMENT /div ns/div Low unlock condition Lock (533MHz) High unlock condition Lock (58MHz) MB54H MB54L DO PIN OUTPUT CURRENT CURE (TYPICAL) OH vs. I OH OL vs. I OL High-level Output oltage OH () MB54L MB54 MB54H Low-level Output oltage OL () 2.. MB54 MB54H MB54L High-level Output Current I OH (ma). 2 Low-level Output Current I OL (ma)

11 PIN OUTPUT WAEFORM AT LOCK CONDITION MB54 MB54H MB54L Output Waveform /div ns/div MB54 MB54H MB54L

12 2 MB54 MB54H MB54L PHAE CHARACTERITIC ( f vs. OUTPUT ENERGY) 5 5 Energy (En) 2t MB54H MB54 MB54L 5 Time f (ns) P k k Oscilloscope CC = P =3. f IN f OC =2MH z f r =f P =46.9kHz ÉÉ ÉÉ ÉÉ É (+) Energy ( ) Energy

13 3 INPUT ENITIITY MB54 MB54H MB54L Input ensitivity vs. Input Frequency (upply oltage Dependence) Input ensitivity P fin (dbm) Input ensitivity P fin (dbm) 2 3 Guaranteed Operating Area CC =4. to 5.5 CC =2.7 to 4. CC =5.5 CC = Input Frequency f IN (GHz) CC =2.7 Input ensitivity vs. Input Frequency (Temperature Dependence) 2 3 Guaranteed Operating Area CC =4. to 5.5 CC =2.7 to 4. T A = 4 C T A =+25 C T A =+85 C T A =+25 C PG pf 5Ω CC.µ X tal P Oscilloscope Input Frequency f IN (GHz) CC =3. PG pf 5Ω.µ CC X tal P Oscilloscope

14 4 MB54 MB54H MB54L INPUT IMPEDANCE TET CIRCUIT Pin Output Current (I OH, I OL ) Measurement CC P OC IN f IN MB54 I OL I OH

15 5 Lock up Time Measurement MB54 MB54H MB54L f IN MB54 LPF CO 2.8MHz Controller (Divide ratio setting) Oscilloscope (MΩ, pf) LPF Circuit kω 4kΩ 4kΩ kω.µf µf µf to CO CC =3, P =8 f CO =Low unlock condition f CO =High unlock condition tep to Lock condition (533MHz) tep to Lock condition (58MHz) Phase Characteristics Measurement CC P P G OC IN MB54 fr kω kω Oscilloscope (MΩ, pf) P G f IN fp CC =3, P =3 f=fr fp Energy (En)= 2 t

16 6 MB54 MB54H MB54L TYPICAL APPLICATION EXAMPLE kω PX (6) LPF CO OUTPUT 2kΩ Charge Pump election (Internal or external) 2kΩ kω FROM CONTROLLER ØR ØP f P f r FC LE Data Clock kΩ 47kΩ MB OC IN OC OUT p CC GND LD f IN X tal pf CC (3) 6 3 kω C C 2.µF 33kΩ LOCK DET..µF kω p, PX : 8 max. C, C 2 : Depends on crystal oscillator LE,FC : With internal pull up resistor ØP : Open drain output

17 7 PACKAGE DIMENION MB54 MB54H MB54L 6-LEAD PLATIC DUAL IN-LINE PACKAGE (Case No.: DIP-6P-M4) ( ) 5 MAX INDEX-.244±..3(7.62) (6.2±.25) TYP INDEX ( ) ( ).±.2 (.25±.5).72(4.36)MAX.8(3.)MIN.5(.27) MAX 99 FUJITU LIMITED D633-2C.(2.54) TYP.2(.5)MIN.8±.3 (.46±.8) Dimensions in inches (millimeters)

18 8 MB54 MB54H MB54L PACKAGE DIMENION ( ) 6-LEAD PLATIC FLAT PACKAGE (Case No.: FPT-6P-M6).89(2.25)MAX (MOUNTING HEIGHT).2(.5)MIN (TANFF HEIGHT) INDEX.37±.6 (7.8±.4).29±.2 B (5.3±.3) ( ).5(.27) TYP.8±.4 (.45±.) Ø.5(.3) M.2±.8 (.5±.2) ( ) A Details of A part.6(.4) Details of B part.6(.5).4(.).35(8.89) REF 99 FUJITU LIMITED F65-2C.8(.2).7(.8) MAX.27(.68) MAX.8(.2).7(.8) MAX.27(.68) MAX Dimensions in inches (millimeters)

19 9 For further information please contact: MB54 MB54H MB54L Japan FUJITU LIMITED Electronic Devices International Operations Department KAWAAKI PLANT, 5 Kamikodanaka, Nakahara ku, Kawasaki shi, Kanagawa 2, Japan Tel: (44) FAX: (44) North and outh America FUJITU MICROELECTRONIC, INC. emiconductor Division 3545 North First treet an Jose, CA , UA Tel: (48) FAX: (48) /945 Europe FUJITU MIKROELEKTRONIK GmbH Am iebenstein 6-, 6333 Dreieich-Buchschlag, Germany Tel: (63) 69- FAX: (63) Asia Pacific FUJITU MICROELECTRONIC AIA PTE LIMITED No.5 Bras Basah Road, Plaza By The Park, #6-4 to #6-7 ingapore 78 Tel: FAX: FUJITU LIMITED Printed in Japan

MB1512 SERIAL INPUT PLL FREQUENCY SYNTHESIZER

MB1512 SERIAL INPUT PLL FREQUENCY SYNTHESIZER ept. Edition.a DATA HEET MB2 ERIA INPUT P FREQUENCY YNTHEIER OW POWER ERIA INPUT P YNTHEIER WITH.GH PRECAER The Fujitsu MB2, utilizing BI-CMO technology, is a single chip serial input P synthesizer with