LINEAR IC CMOS 8 BIT 4-CHANNEL D/A CONVERTER MB86022

Transcription

1 DS0303aE DATA SHEET LINEAR IC CMOS 8 BIT -CHANNEL D/A CONERTER MB860 CMOS 8-BIT -CHANNEL D/A CONERTER The Fujitsu MB860 is a 8-bit -channel Digital to Analog Converter which is fabricated with Fujitsu CMOS Technology. The data latch and output buffer circuitry are provided on each channel which can operate independently selected by bit data. PLASTIC PACKAGE DIP-P-M03 Resolution Conversion Rate Digital Input oltage : 8-Bits (-channels) : 00k sps : TTL Level PLASTIC PACKAGE FPT-P-M0 Power Supply oltage : +5 Low Power Dissipation : mw typ. at +5 Each channel operates independently On-chip Data Initialization & Power Down Function Reference voltage mode selection: On-chip or External generation Easy to take interface with micro processor (Parallel Data Input) D0 D D D3 D D5 D6 D7 C0 C WR CE PIN ASSIGNMENT (TOP IEW) RESET PD DD R R AO0 AO AO AO3 N.C. AG DG This device contai circuitry to protect the inputs agait damage due to high static voltages or electric fields. However, it is advised that normal precautio be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Quick Pro TM is a trademark of FUJITSU LIMITED Copyright 995 by FUJITSU LIMITED

2 MB860 ABSOLUTE MAXIMUM RATINGS (See NOTE) Parameter Rating Symbol Pin Name Unit Min Typ Max Power supply voltage DD DD GND0.3 7 Digital input voltage DI All digital input pi GND0.3 DD +0.3 Analog input voltage, R,R GND0.3 DD +0.3 Analog output voltage AO AO0,AO,AO,AO3 GND0.3 DD +0.3 Analog output current I AO AO0,AO,AO,AO3 0 0 ma Storage temperature Tstg 0 5 C NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditio as detailed in the operational sectio of this data sheet. Exposure to absolute maximum rating conditio for extended periods may affect device reliability.

3 MB860 BLOCK DIAGRAM D0 to D7 8 8-bit Data Latch 8-bit DAC + AO3 Buffer Amp. 8-bit Data Latch 8-bit DAC + AO Buffer Amp. C0,C WR CE Channel Select & Control Logic 8-bit Data Latch 8-bit DAC + Buffer Amp. AO 8-bit Data Latch 8-bit DAC + AO0 RESET PD Buffer Amp. R R REF Circuit DD DG AG 3

4 MB860 PIN DESCRIPTION System Pin Number Symbol Descriptio Power Supply DD Power Supply oltage 5 3 DG AG 3 PD GND for Digital System GND for Analog System Power down control signal pin. The circuit is set power down when this pin goes to L. This pin is pulled up by high resistance. TTL interface. RESET Reset input signal pin. The data at all channels is initialized when this pin goes to L. At this time, the D/A output is set at D(A)=8. This pin is pulled up by high resistance. TTL interface. CE WR Chip enable signal pin. The data can be written when this pin goes to L. This pin is pulled up by high resistance. TTL interface. Data write pin. The data from D0 to D7 is written when the rising edge (L H) of this pin. TTL interface. 9 C0 Channel selection signal pin. Channels are selected by following table. TTL interface. Digital Input 0 C C C0 Channel L L 0 L H H L H H 3 3 D0 D D Data input signal pin. The digital data is read by the channel which is selected by C0 and C pi when the rising edge of WR (L H), and analog output is shown correspond to that digital code. D0 is LSB and D7 is MSB. Code is set at when reset. TTL interface. D3 5 D 6 D5 7 D6 8 D7 Analog Input 0 R R Reference voltage (H level) input pin. DD is given by internal reference voltage circuitry to this pin when internal reference voltage mode. In this case, the capacitor between this pin and AG pin is required to limit noise generation. In case of external reference voltage mode, the reference voltage should be given from this pin. Middle point of reference voltage input pin. Reference voltage (H level) input pin. DD is given by internal reference voltage circuitry to this pin when internal reference voltage mode. In this case, the capacitor between this pin and AG pin is required to limit noise generation. In case of external reference voltage mode, the reference voltage should be given from this pin.

5 MB860 (Continued) System Pin Number Symbol Descriptio 6 AO3 Analog output pin of channel 3. This pin is set to highimpedance state at Power Down. Analog 7 AO Analog output pin of channel. This pin is set to highimpedance state at Power Down. Output 8 AO Analog output pin of channel. This pin is set to highimpedance state at Power Down. 9 AO0 Analog output pin of channel 0. This pin is set to highimpedance state at Power Down. 5 N.C. No connection pin 5

6 MB860 RECOMMENDED OPERATING CONDITIONS Parameter Symbol Pin Name alue Min Typ Max Unit Power supply voltage DD DD Digital input voltage DI All digital input pi 0 DD Analog input voltage R R Analog output load resistance Analog output load capacitance R AL C AL AO0, AO, AO, AO kω pf Operating temperature Ta 0 70 C 6

7 MB860 ELECTRICAL CHARACTERISTICS Parameter Symbol Pin Name I DD Power supply current DD I DD Conditio PD= H No load PD= L ( DD =.75 to 5.5, Ta=0 C to 70 C) alue Unit Min Typ Max ma 0.5 ma Digital input L oltage H oltage L Current H Current IL IH I IL I IH All digital input pi D0 to D7, WR DI =GND DI = DD DD µa µa Pull up current WR H Width WR L Width Digital input L width DATA Set up time DATA Set up time CE Set up time DATA Hold time DATA Hold time CE Hold time I PLU t WHWR t WLWR t WLRP t SD t SD t SCE t HD t HD t HCE PD, CE, RESET WR WR RESET, PD D0 to D7, WR C0, C, WR CE, WR D0 to D7, WR C0, C, WR CE, WR DI =GND µa 7

8 MB860 (Continued) ( DD =.75 to 5.5, Ta=0 C to 70 C) alue Parameter Symbol Pin Name Conditio Min Typ Max Unit Rising time t r WR 0 50 Falling time t f WR 0 50 Rising time t r D0 to D7, C0, C, CE, RESET, 0 50 PD Falling time t f D0 to D7, C0, C, CE, RESET, 0 50 PD Resolution Res 8 bits Analog output Min. voltage Analog output Max. voltage Analog input resistance AOL AOL AOH AOH R I AO0, AO, AO, AO3 R, R Input code D(A)= 0 Input code D(A)= 55 No external R input R=open R=open External R input R= R= No external R input R=open R=open External R input R= R= (Typ.) 0. (Typ.) 0. (Typ.) 0. (Typ.) 0. _ DD x _ 383 x DD 5 8 (Typ.) +0. (Typ.) +0. (Typ.) +0. (Typ.) kω Linearity error LE AO0, No external R input.5.5 R=open Differential AO, D R=open linearity error LE AO, Full scale change Setting time t S AO3 () 5 LSB LSB µs 8

9 MB860 FUNCTION DESCRIPTION TRUTH TABLE PD RESET CE WR C0, C D0 to D7 Function 0 x x x Power down 0 x x x Initialization No data input No analog output change 0 Channel selectiion Data input Analog output change Fig. DATA SET TIMING DIAGRAM D0 to D7 C0, C CE WR Data is read. Analog output is changed. Data is not read. Analog output is not changed. 9

10 MB860 SETTING OF ANALOG OUTPUT OLTAGE Data Analog Output oltage D(A) D7 D6 D5 D D3 D D D0 R=Open R=Open (No external R input) R= R=Open (External R input) R= R= (External R input) 55 _ 383 x DD 5 x DD x 7 + _ DD 56 8 x _ 38 5 x DD x DD x 6 + _ DD 56 8 x _ 38 5 x DD _ DD 5 x (D(A)8) + _ DD x DD x 5 + _ DD 56 x DD x (D(A) 8) 56 _ + DD 8 x x (D(A)8) _ 57 5 x DD x DD + _ DD _ DD _ DD 7 0 _ 55 5 x DD x DD 56 x () + _ DD 8 x () _ 5 5 x DD x DD x () + _ DD 56 x () _ 30 5 x DD x DD 56 x (6) + _ DD x (6) _ 9 5 x DD x DD 56 x (7) + _ DD 8 x (7) _ DD DD ( ) + LSB _ DD 5 x DD 56 8 * Code is set at when reset mode. 0

11 MB860 ANALOG OUTPUT OLTAGE RANGE Fig. ON-CHIP REFERENCE OLTAGE MODE (NO EXTERNAL R INPUT) DD 3 x DD LSB _ DD 5 AOH _ 383 xdd 5 _ DD D/A Output range AOL _ DD AG (R=, R=/x DD ) Fig. 3 EXTERNAL REFERENCE OLTAGE MODE DD LSB _ x DD 56 (R) _ DD AOH _ x DD x 7 + _ DD 56 D/A Output range AOL ( DD ) AG (R=, R= ) Fig. EXTERNAL REFERENCE OLTAGE MODE DD LSB 8 (R) AOH _ 7 x ( ) + 8 (R) D/A Output range AOL ( ) + AG

12 MB860 TYPICAL APPLICATION CIRCUIT FOR EACH MODE Fig. 5 ON-CHIP REFERENCE OLTAGE MODE D0 to D7 C0 C WR CE N.C. RESET PD +5 ( DD ) + µf AO0 to 3 + µf Fig. 6 EXTERNAL REFERENCE OLTAGE MODE D0 to D7 C0 C WR CE N.C. RESET PD +5 ( DD ) + µf AO0 to 3 (R=, R=/x DD ) Fig. 7 EXTERNAL REFERENCE OLTAGE MODE D0 to D7 C0 C WR CE N.C. RESET PD +5 ( DD ) AO0 to 3 (R=, R= )

13 MB860 TIMING DIAGRAM WR IH IL t r t WHWR t f t WLWR D0 to D7 IH IL t r t SD t HD t f C0, C IH IL t r t SD t HD t f CE IH IL t f t SCE t HCE t r ±LSB AO0 to AO3 t S ±LSB RESET, PD IH IL t WLRP 3

14 MB860 PACKAGE DIMENSIONS -LEAD PLASTIC DUAL IN-LINE PACKAGE (CASE No.: DIP-P-M03) 5 MAX INDEX-.60±.00 (6.60±0.5).300(7.6) TYP INDEX ( ).00±.00 (0.5±0.05).050(.7) MAX ( ).7(.36)MAX.8(3.00)MIN.00(.5) TYP (.7 0 ).08±.003 (0.6±0.08).00(0.5)MIN 99 FUJITSU LIMITED D07S-3C Dimeio in inches (millimeters)

15 MB860 -LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-P-M0) (5. ) (.80) MAX (MOUNTING HEIGHT).00(0.05) MIN (STAND OFF HEIGHT) INDEX.0±.06 (0.0±0.0).99±.0 (7.60±0.30).36±.0 (9.0±0.30).050(.7) TYP.08±.00 (0.5±0.0).005(0.3) M.00±.008 (0.50±0.0) ( ) Details of A part A.008(0.0) 99 FUJITSU LIMITED F008S-C.00(0.0).550(3.97) REF.0(0.60).007(0.8) MAX.07(0.68) MAX Dimeio in inches (millimeters) All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a mea of illustrating typical semiconductor applicatio. Complete Information sufficient for cotruction purposes is not necessarily given. The Information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no respoibility for inaccuracies. The Information contained in this document does not convey any licee under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specificatio without notice. No part of this publication may be copied or reproduced in any form or by any mea, or traferred to any third party without prior written coent of Fujitsu. 5

16 MB860 For further information please contact: Japan FUJITSU LIMITED Electronic Devices International Operatio Department KAWASAKI PLANT, 05 Kamikodanaka, Nakaharaku, Kawasakishi, Kanagawa, Japan Tel: (0) FAX: (0) North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 355 North First Street San Jose, CA 95380, USA Tel: (08) FAX: (08) 390/905 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebetein DreieichBuchschlag, Germany Tel: (0603) 6900 FAX: (0603) 690 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LIMITED No. 5 Bras Basah Road, Plaza By The Park, #060 to #0607 Singapore 078 Tel: FAX: I950 FUJITSU LIMITED Printed in Japan 6