HCF4044B QUAD NAND 3-STATE R-S LATCH

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1 QUAD NAND 3-STATE R-S LATCH QUIESCENT CURRENT SPECIFIED UP TO 20V 3-LEVEL OUTPUTS WITH COMMON OUTPUT ENABLE SEPARATE SET AND RESET INPUT FOR EACH LATCH 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT I I = 100nA (MAX) AT V DD = 18V T A = 25 C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION The HCF4044B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. The HCF4044B is a quad cross-coupled 3-state CMOS NAND latch. Each latch has a separate Q output and individual SET and RESET input. The Q outputs are DIP ORDER CODES SOP PACKAGE TUBE T & R DIP HCF4044BEY SOP HCF4044BM1 HCF4044M013TR controlled by a common ENABLE input. A logic "1" or "high" on the ENABLE inputs connects the latch states to the Q outputs. A logic "0" or "low" on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common bussing of the outputs. PIN CONNECTION September /9

2 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 4, 6, 12, 14 S1 to S4 Set Inputs 3, 7, 11, 15 R1 to R4 Reset Inputs 5 ENABLE Enable Input 13, 9, 10, 1 Q1 to Q4 Outputs 2 NC Not Connected 8 V SS Negative Supply Voltage 16 V DD Positive Supply Voltage TRUTH TABLE INPUTS ENABLE Sn Rn OUTPUT Qn L X X Z H L H H H X L L H L H LATCHED X : Don"t Care FUNCTIONAL DIAGRAM 2/9

3 LOGIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V DD Supply Voltage -0.5 to +22 V V I DC Input Voltage -0.5 to V DD V I I DC Input Current ± 10 ma P D Power Dissipation per Package 200 mw Power Dissipation per Output Traistor 100 mw T op Operating Temperature -55 to +125 C T stg Storage Temperature -65 to +150 C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditio is not implied. All voltage values are referred to V SS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit V DD Supply Voltage 3 to 20 V V I Input Voltage 0 to V DD V T op Operating Temperature -55 to 125 C 3/9

4 DC SPECIFICATIONS Test Condition Value Symbol Parameter V I (V) V O (V) I O (µa) V DD (V) T A = 25 C -40 to 85 C -55 to 125 C Min. Typ. Max. Min. Max. Min. Max. Unit I L Quiescent Current 0/ / / / V OH High Level Output 0/5 < Voltage 0/10 < /15 < V OL V IH V IL I OH I OL Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current Output Sink Current 5/0 < /0 < /0 < /4.5 < /9 < /13.5 < /0.5 < /1 < /1.5 < /5 2.5 < /5 4.6 < / < / < /5 0.4 < / < / < I I Input Leakage Current 0/18 Any Input 18 ±10-5 ±0.1 ±1 ±1 µa I OZ 3-State Output 0/18 0/18 18 ±10-4 ±0.4 ±12 ±12 µa C I Input Capacitance Any Input pf The Noise Margin for both "1" and "0" level is: 1V min. with V DD =5V, 2V min. with V DD =10V, 2.5V min. with V DD =15V µa V V V V ma ma 4/9

5 DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25 C, C L = 50pF, R L = 200KΩ, t r = t f = 20 ) Symbol t PLH t PHL t PZH t PZL (*) Typical temperature coefficient for all V DD value is 0.3 %/ C. TEST CIRCUIT Parameter Propagation Delay Time (SET or RESET to Q) 3-State Propagation Delay Time (Enable to Q) Test Condition Value (*) Unit V DD (V) Min. Typ. Max t PLZ t PHZ 3-State Propagation Delay Time (Disable to Q) t TLH t THL Traition Time t W Pulse Width (Set or Reset) C L = 50pF or equivalent (includes jig and probe capacitance) R L = 200KΩ R T = Z OUT of pulse generator (typically 50Ω) 5/9

6 WAVEFORM 1 : PROPAGATION DELAY TIMES (f=1mhz; 50% duty cycle) WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIMES (f=1mhz; 50% duty cycle) 6/9

7 Plastic DIP-16 (0.25) MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. a B b b D E e e F I L Z P001C 7/9

8 SO-16 MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A a a b b C c1 45 (typ.) D E e e F G L M S 8 (max.) PO13H 8/9

9 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no respoibility for the coequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licee is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificatio mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom 9/9

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