MB GHz TWO MODULUS PRESCALER
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1 Sept Edition 3.0b ATA SHEET MB GHz TWO MOULUS PRESALER 2.7GHz TWO MOULUS PRESALER The Fujitsu MB510 is an ultra high speed, two modulus prescaler that forms a Phase Locked Loop (PLL) when combined with a frequency synthesizer such as the Fujitsu MB87001A. It divides the input frequency by the modulus of 128/144 or 256/272, and operates at a low power supply current of 10mA at 5.0V. Through the use of Fujitsu s Advanced Process Technology, the MB510 achieves extremely small stray capacitance from its internal elements. FEATURES High Frequency Operation: Power issipation: 2.7GHz max. 50mW typ. Pulse Swallow Function: 128/144, 256/272 Wide Operation Temperature: Stable Output Amplitude: Built in Termination Resistor -40 to +85 V = 1.6V p p typ. PLASTI PAKAGE FPT-08P-M01 omplete PLL synthesizer circuit with the Fujitsu MB87001A PLL synthesizer I P ASSIGNMENT Package Standard 8-pin Flat Package (Suffix: PF) ABSOLUTE MAXIMUM RATGS (See Note) Rating Symbol Value Unit TOP VIEW 6 N M Supply Voltage 0.5 to +7.0 V 4 5 GN Voltage V 0.5 to V Output urrent I O 10 ma Storage Temperature T STG 55 to +125 Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. opyright 1995 by FUJITSU LIMITE and FUJITSU MIROELETRONIS,.
2 M PUT BUFFER M PUT BUFFER H H M H L ivide Ratio 1/128 1/144 L L Note: H 1/256 L 1/272 : H =, L = open M: H = 2.0V to, L = GN to 0.8V Figure 1. MB510 Block iagram P ESRIPTION Pin Number Symbol Function 1 2 Supply Voltage 3 ivide Ratio ontrol (See ivide Ratio Table) 4 Output 5 GN Ground 6 M Modulus ontrol (See ivide Ratio Table) 7 N Non onnection 8 omplementary 2
3 REOMMENE OPERATG ONITIONS Parameter Symbol Value Min. Typ. Max. MB510 Unit Supply Voltage V Output urrent I O 1.2 ma Ambient Temperature T A Load apacitance L 8 pf ELETRIAL HARATERISTIS (Recommended Operating onditions unless otherwise noted) Parameter Symbol ondition Value Min. Typ. Max. Unit Supply urent I ma Output Amplitude V O resistor. Built-in a termination Load capacitance = 8pF Frequency f With input coupling capacitor V p p MHz f = 10 to 2200MHz Signal Amplitude P f = 2200 to 2700MHz 4 10 dbm High Level Voltage for M Low Level Voltage for M High Level Voltage for Low Level Voltage for High Level urrent for M Low Level urrent for M V IHM 2.0 V V ILM 0.8 V V IHS * V V ILS Open V I IHM V IH = 2.0V 0.4 ma I ILM V IL = 0.8V 0.2 ma Modulus Set-up Time M to t SET ns Note: *esign Guarantee 3
4 = +5.0V + 10% Sampling scope input point for input waveform 3 P.G. 1 Sampling scope prober point for output waveform 50Ω 2 M GN L M 1 : 2 : 3 : 0.1µF L : 8pF (including scope and jig capacitance) Figure 2. Test ircuit MIMUM PUT SIGNAL AMPLITUE (mvp p) = 5.0V T A = PUT FREUENY (MHz) Figure 3. Signal Amplitude vs. Frequency 4
5 TIMG HART (2 MOULUS) Example: ivide ratio = 128/ M t SET t SET Note: When divide of 144 is selected, positive pulse is applied by 16 to 80. The typical set up time is 16 ns from the M signal input to the timing of change of prescaler divide ratio. 1 V SX (Max. 8V) 2 X1 10KΩ 12KΩ VO PUT lock ata LE 47K 0.047µF 47K 47K MB 87001A KΩ 33KΩ 12KΩ 10KΩ MB KΩ X1 : 12.8MHz X tal : 5V + 10% V SX : 8V max. 1, 2 : depends on crystal oscillator Lock et. 10KΩ Figure 4. Typical Application Example 5
6 PAKAGE IMENSIONS (Suffix: PF) 8-LEA PLASTI FLAT PAKAGE (ASE No: FPT-08P-M01) (2.25) MAX (SEATE HEIGHT).002(0.05) M (STAN OFF) EX ( ) ( ) (1.27) TYP.150(3.81) REF A ( ).005(0.13) M ( ) etails of A part.008(0.20).004(0.10).020(0.50).007(0.18) MAX.027(0.68) MAX 1988 FUJITSU LIMITE F08002S-3 Imensions in inches (millimeters) All Rights Reserved. ircuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. omplete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. 6
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