MB1512 SERIAL INPUT PLL FREQUENCY SYNTHESIZER

Transcription

1 ept. Edition.a DATA HEET MB2 ERIA INPUT P FREQUENCY YNTHEIER OW POWER ERIA INPUT P YNTHEIER WITH.GH PRECAER The Fujitsu MB2, utilizing BI-CMO technology, is a single chip serial input P synthesizer with pulse-swallow function. The MB2 contains a. GH two modulus prescaler that can select of either 4/ or 2/2 divide ratio, control signal generator, -bit shift register, -bit latch, programmable reference divider (binary 4-bit programmable reference counter), -bit switch counter, phase comparator with phase conversion function, charge pump, crystal oscillator, -bit shift register, -bit latch, programmable divider (binary 7-bit swallow counter and binary -bit programmable counter) and analog switch to speed up lock up time. It operates with a supply voltage of typ. and achieves very low supply current of ma typ. realized through the use of Fujitsu Advanced Process Technology. High operating frequency: f IN MAX =.GH (P IN MIN =dbm) Pulse swallow function: 4/ or 2/2 Power supply voltage: CC =4. to. ow supply current: I CC =ma typ. erial input -bit programmable divider consisting of: Binary 7-bit swallow counter: to 27 Binary -bit programmable counter: to 247 erial input -bit programmable reference divider consisting of: Binary 4-bit programmable reference counter: to 33 -bit switch counter (W) sets divide ratio of prescaler On-chip analog switch achieves fast lock up time 2types of phase detector output On-chip charge pump (Bipolar type) Output for external charge pump Wide operating temperature: 4 C to + C 2-pin Plastic hrink mall Outline Package ABOUTE MAXIMUM RATING (ee NOTE) Rating ymbol alue Unit Power upply oltage Output oltage Open-drain oltage Output Current torage Temperature NOTE: CC OUT T TG. to +7. P CC to.. to CC +. OOP. to. I OUT ± to +2 C Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ma OC IN NC OC- OUT P CC GND D NC f in PATIC PACKAGE FPT-2P-M3 PIN AIGNMENT Top iew ØR NC ØP f OUT BIW FC E Data NC Clock This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Copyright 4 by FUJITU IMITED and FUJITU MICROEECTRONIC, INC.

2 MB2 MB2 BOCK DIAGRAM OC IN -BIT HIFT REGITER PHAE COMPARATOR 2 R OC OUT P CC 3 4 CRYTA OCIATOR -BIT HIFT REGITER -BIT ATCH -BIT ATCH PROGRAMMABE REFERENCE DIIDER BINARY 4-BIT REFERENCE COUNTER W f r MONITOR FREQUENCY CHANGING CIRCUIT CHARGE PUMP ANAOG WITCH E 7 P f OUT BIW FC GND 7 4 E D -BIT HIFT REGITER -BIT HIFT REGITER CONTRO -BIT ATCH 3 Data -BIT ATCH Clock 7-BIT ATCH -BIT ATCH f IN PRECAER PROGRAMMABE DIIDER BINARY 7BIT WAOW COUNTER BINARY -BIT PROGRAMMABE COUNTER f p CONTRO CIRCUIT 2

3 MB2 PIN DECRIPTION Pin No. Pin Name I/O Description 3 OC IN OC OUT I O Oscillator input. Oscillator output. A crystal is placed between OC IN and OC OUT. 4 P Power supply input for charge pump and analog switch. CC Power supply voltage input. O Charge pump output. The characteristics of charge pump is reversed depending upon FC input. 7 GND Ground. 2 D f IN Clock O NC No connection. I I NC No connection. Phase comparator output. Normally this pin outputs high level. While the phase difference of f r and f p exists, this pin outputs low level. Prescaler input. The connection with an external CO should be AC connection. Clock input for -bit shift register and -bit shift register. On rising edge of the clock shifts one bit of data into the shift registers. 3 Data I Binary serial data input. The last bit of the data is a control bit which specified destination of shift registers. When this bit is high level and E is high level, the data stored in shift register is transferred to -bit latch. When this bit is low level and E is high level, the data is transferred to -bit latch. 4 E 7 2 FC BIW f OUT ØP ØR I I O O O O oad enable input (with internal pull up resistor). When E is high or open, the data stored in shift register is transferred into latch depending upon the control bit. At the time, internal charge pump output to be connected to BIW pin because internal analog switch becomes ON state. Phse select input of phase comparator (with internal pull up resistor). When FC is low level, the characteristics of charge pump, phase comparator is reversed. FC input signal is also used to control f out pin (test pin) output level, f r or f p. Analog switch output. Usually BIW pin is set high-impedance state. When internal analog switch is ON (E pin is high level), this pin outputs internal charge pump state. Minitor pin of phase comparator input. f out pin outputs either programmable reference divider output (f r ) or programmable divider output (f p ) depending upon FC pin input level. FC=H: It is the same as f r output level. FC=: It is the same as f p output level. Outputs for external charge pump. The characteristics are reversed according to FC input. P pin is N-channel open drain output. 2 NC No connection. 3

4 MB2 FUNCTIONA DECRIPTION ERIA DATA INPUT erial data input is achieved by three inputs, such as Data pin, Clock pin and E pin. erial data input controls -bit programmable reference divider and -bit programmable divider, respectively. Binary serial data is input to Data pin. On rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high level or open, stored data is transferred into latch depending upon the control bit. Control data H data is transferred into -bit latch. Control data data is transferred into -bit latch. PROGRAMMABE REFERENCE DIIDER Programmable reference divider consists of -bit shift register, -bit latch and 4-bit reference counter. erial -bit data format is shown below. Control bit B Divide ratio of prescaler setting bit MB C W Divide ratio of programmable reference counter setting bit 4-BIT PROGRAMMABE REFERENCE COUNTER DIIDE RATIO Divide Ratio R NOTE: Divide ratio less than is prohibited. Divide ratio: to 33 W: This bit selects divide ratio of prescaler. W=H : 4/ W= : 2/2 to 4: These bits select divide ratio of programmable reference divider. C: Control bit (sets as high level). Data is input from MB side. PROGRAMMABE DIIDER Programmable divider consists of -bit shift register, -bit latch, 7-bit swallow counter and -bit programmable counter. erial -bit data format is shown following page. 4

5 MB2 Control bit B MB C Divide ratio of swallow counter setting bit Divide ratio of programmable counter setting bit 7-BIT WAOW COUNTER DIIDE RATIO Divide Ratio A NOTE: Divide ratio: to 27 -BIT PROGRAMMABE COUNTER DIIDE RATIO Divide Ratio N Ø NOTE: Divide ratio less than is prohibited. Divide ratio: to 247 to 7: wallow counter divide ratio setting bit. ( to 27) to : Programmable counter divide ratio setting bit. ( to 247) C: Control bit (sets as low level). Data is input from MB side. PUE WAOW FUNCTION f CO = [(PxN)+A] xf OC R f CO :Output frequency of external voltage controlled oscillator (CO) N: Preset divide ratio of binary -bit programmable counter ( to 247) A: Preset divide ratio of binary 7-bit swallow counter ( A 27, A<N) f OC :Output frequency of the external reference frequency oscillator R: Preset divide ratio of binary 4-bit programmable reference counter ( to33) P: Preset modulus of external dual modulus prescaler (4 or 2)

6 MB2 ERIA DATA INPUT TIMING t t µs Data =MB *(W) 7 (4) () (7) =B () C: CONTRO BIT (C: CONTRO BIT) Clock E t t 2 t 3 t 4 t NOTE: Parenthesis data is used for setting divide ratio of programmable reference divider. On rising edge of clock shifts one bit of data in the shift register. PHAE CHARACTERITIC FC pin is provided to change phase characteristics of phase comparator. Characteristics of internal charge pump output level ( ), phase comparator output level (ØR, ØP) are reversed depending upon FC pin input level. Also, monitor pin (f out ) output level of phase comparator is controlled by FC pin input level. The relation between outputs (, ØR, ØP) and FC input level are shown below. f r >f p f r <f p f r =f p H FC=H or open ØR H ØP f out (f r ) (f r ) (f r ) H ØR H FC= ØP f out (f p ) (f p ) (f p ) CO CHARACTERITIC CO OUTPUT FREQUENCY CO INPUT OTAGE 2 Note: =(High impedance) Depending upon CO characteristics, FC pin should be set accordingly: When CO characteristics are like, FC should be set high or open circuit; When CO characteristics are like 2, FC should be set ow.

7 MB2 f r f P D H f r >f p f r =f p f r <f p f r <f p f r <f p NOTE: Phase difference detection range: 2π to +2π pike appearance depends on charge pump characteristics. Also, the spike is output in order to diminish dead band. When f r >f p or f r <f p, spike might not appear depending upon charge pump characteristics. ANAOG WITCH ON/OFF of analog switch is controlled by E input signal. When the analog switch is ON, internal charge pump output ( ) to be connected to BIW pin. When the analog switch is OFF, BIW pin is set to high-impedance state. E=H (Changing the divide ratio of internal prescaler) : Analog switch=on E= (Normal operating mode) : Analog switch=off PF time constant is decreased in order to insert a analog switch between PF and PF2 when channel of P is changing. Thus, lock up time is decreased, that is, fast lock up time is achieved. CHARGE PUMP PF- PF-2 CO ANAOG W BIW (CONTRO IGNA E) RECOMMENDEPERATING CONDITION alue Parameter ymbol Min Typ Max Unit Power upply oltage CC P 4... CC. Input oltage I GND CC Operating Temperature T A 4 C 7

8 MB2 EECTRICA CHARACTERITIC Parameter ymbol Condition Power upply Current I CC Note alue Unit Min Typ Max. 2. ma Operating Frequency f in OC IN f in f OC Note MHz MHz Input ensitivity f in Pf in OC IN OC. dbm PP High-level Input oltage ow-level Input oltage Except fi n and OC IN IH I CC x.7 CC x.3 High-level Input Current ow-level Input Current Data Clock I IH I I.. µa µa Input Current OC IN E, FC I OC I E ± µa µa High-level Output Current ow-level Output Current Except and OC- OUT OH O CC = N-channel Open Drain Cutoff Current, ØP I OFF CC P. µa Output Current Except and OC- OUT I OH I O.. ma ma Analog witch On Resistor R ON 2 Ω NOTE : f in =.GHz, OC IN =2MHz, CC =. Inputs are grounded and outputs are open. NOTE 2: AC coupling. Minimum operating frequency is measured when a capacitor pf is connected.

9 MB2 TET CIRCUIT CC = p =.µf X tal P G p F Ω Oscilloscope

10 MB2 TYPICA APPICATION EXAMPE kω PX () PF CO OUTPUT 2kΩ 2kΩ kω Charge Pump election (Internal or external) FROM CONTROER ØR ØP f OUT BIW FC E Data Clock kΩ 47kΩ MB OC IN OC OUT p CC GND D f in X tal p CC () kω C C 2.µF 33kΩ OCK DET.µF kω p, PX : max. C, C 2 : Depends on crystal oscillator E,FC : With internal pull up resistor ØP : Open drain output

11 MB2 PACKAGE DIMENION.2±.4 (.±.) 2-EAD PATIC FAT PACKAGE (Case No. : FPT-2P-M3) (.2. ).4(.) (MOUNTING HEIGHT) INDEX.73±.4 (4.4±.).22±. (.4±.2) A.23(.4) NOM.2±.47 (.±.2) ( ) ( ) Details of A part.4±.4 (TANFF (.±.) HEIGHT).23(.) REF :This dimension does not include resin protruction. to.2±. (.±.2) FUJITU IMITED F22-2C All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete Information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. Dimensions in inches (millimeters) The Information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu.

12 MB2 For further information please contact: Japan FUJITU IMITED Electronic Devices International Operations Department KAWAAKI PANT, Kamikodanaka, Nakaharaku, Kawasakishi, Kanagawa 2, Japan Tel: (44) FAX: (44) North and outh America FUJITU MICROEECTRONIC, INC. emiconductor Division 34 North First treet an Jose, CA 34-4, UA Tel: (4) 22 FAX: (4) 43244/4 Europe FUJITU MIKROEEKTRONIK GmbH Am iebenstein -, 333 Dreieich-Buchschlag, Germany Tel: (3) - FAX: (3) -22 Asia Pacific FUJITU MICROEECTRONIC AIA PTE IMITED No. Bras Basah Road, Plaza By The Park, #-4 to #-7 ingapore 7 Tel: 33- FAX: 33- FUJITU IMITED Printed in Japan 2