Divide by: 128/129-64/65 dual modulus low power ECL prescaler SA701 PIN CONFIGURATION

Transcription

1 ivide by: 128/129-64/65 dual modulus low power ESCRIPTION The is an advanced dual modulus (ivide By 128/129 or 64/65) low power. The minimum supply voltage is 2.7V and is compatible with the CMOS UMA15 synthesizer from Philips and other logic circuits. The low supply current allows application in battery operated low-power equipment. Maximum input signal frequency is 1.1GHz for cellular and other land mobile applications. There is no lower frequency limit due to a fully static design. The circuit is implemented in ECL technology on the UBiC process. The circuit will be available in an 8-pin SO package with 15 mil package width and in 8-pin dual in-line plastic package, and is pin compatible with Fujitsu MB51, Plessey SP874 and Motorola FEATURES Low voltage operation Low current consumption Operation up to 1.1GHz ES hardened P CONFIGURATION V CC APPLICATIONS Cellular phones Cordless phones RF LANs Test and measurement Military radio VHF/UHF mobile radio VHF/UHF hand-held radio N, Package nc GN Figure 1. Pin Configuration SR533 ORERG FORMATION ESCRIPTION TEMPERATURE RANGE ORER COE WG # 8-Pin Plastic ual In-Line Package (IP) -4 to +85 C N SOT Pin Plastic Small Outline (SO) package (Surface-mount) -4 to +85 C SOT96-1 ABSOLUTE MAXIMUM RATGS SYMBOL PARAMETER RATG UNITS V CC Supply voltage -.3 to +7. V V Voltage applied to any other pin -.3 to (V CC +.3) V I O Output current 1 ma T STG Storage temperature range -65 to +125 C T A Operating ambient temperature range -55 to +125 C θ JA Thermal impedance package N package C/W 1993 Jun

2 ivide by: 128/129-64/65 dual modulus low power BLOCK IAGRAM Figure 2. Block iagram SR Jun 17 71

3 ivide by: 128/129-64/65 dual modulus low power C ELECTRICAL CHARACTERISTICS The following C specifications are valid for T A = 25 C and V CC = 3.V; unless otherwise stated. Test circuit Figure 4. SYMBOL PARAMETER TEST CONITIONS LIMITS M TYP MAX UNITS V CC Power supply voltage range f = 1GHz, input level = dbm V I CC Supply current No load 4.5 ma V OH Output high level I = 1.2mA V CC -1.4 V V OL Output low level V CC -2.6 V V IH input high threshold 2. V CC V V IL input low threshold.3.8 V V IH input high threshold 2. V CC V V IL input low threshold.3.8 V I IH input high current V = V CC = 6V.1 5 µa I IL input low current V = V, V CC = 6V 1 3 µa I IH input high current V = V CC = 6V 35 1 µa I IL input low current V = V, V CC = 6V 5.1 µa AC ELECTRICAL CHARACTERISTICS The following AC specifications are valid for V CC = 3.V, f = 1GHz, input level = dbm, T A = 25 C; unless otherwise stated. Test circuit Fig. 4. SYMBOL PARAMETER TEST CONITIONS LIMITS M TYP MAX V Input signal amplitude 1 1pF input coupling.5 2. V P-P f Input signal frequency irect coupled input GHz UNITS 1pF input coupling 1.1 GHz R I ifferential input resistance C measurement 5 kω V O Output voltage V CC = 5.V 1.6 V P-P V CC = 3.V 1.2 V P-P Modulus set-up time 1 5 ns Modulus hold time 1 ns Propagation time 1 ns NOTES: 1. Maximum limit is not tested, however, it is guaranteed by design and characterization. 2. For f < 5MHz, minimum input slew rate of 32V/µs is required. ESCRIPTION OF OPERATION The comprises a frequency divider circuit implemented using a divide by 4 or 5 synchronous prescaler followed by a 5 stage synchronous counter, see BLOCK IAGRAM. The normal operating mode is for (Modulus Sewitch) input to be set low and (Modulus Control) input to be set high in which case the circuit comprises a divide by 128. For divide by 129 the signal is forced low, causing the prescaler circuit to switch into divide by 5 operation for the last cycle of the synchronous counter. Similarly, for divide by 64 and 65 the will generate those respective moduli with the signal forced high, in which the fourth stage of the synchronous divider is bypassed. A truth table for the modulus values is given below: For minimization of propagation delay effects, the second divider circuit is synchronous to the divide by 4/5 stage output. The prescaler input is positive edge sensitive, and the output at the final count is a falling edge with propagation delay relative to the input. The rising edge of the output occurs at the count 64 for modulus 128/129 or count 32 for modulus 64/65 with delay. The input is not designed for synchronous switching. The and inputs are TTL compatible threshold inputs operating at a reduced input current. CMOS and low voltage interface capability are allowed. The input has an internal pull-down simplifying modulus group selection. With open the divide by 128/129 mode is selected and with connected to V CC divide by 64/65 is selected. The prescaler input is differential and ECL compatible. The output is single-ended ECL compatible. Table 1. Modulus Jun 17 72

4 ivide by: 128/129-64/65 dual modulus low power AC TIMG CHARACTERISTICS =. IVIE BY 128/129 OPERATION =. IVIE BY 128/129 OPERATION = 1. IVIE BY 64/65 OPERATION = 1. IVIE BY 64/65 OPERATION. SR535 Figure 3. AC Timing Characteristics 1993 Jun 17 73

5 ivide by: 128/129-64/65 dual modulus low power R1 C1 1pF C2 1pF R2 V CC V CC NC C3.1µF GN R3 2.2kΩ C4 5pF Figure 4. Test Circuit SR536 FREUENCY (MHz) MIMUM PUT POWER (dbm) V CC = 3.V 4 C 25 C 85 C Figure 5. Minimum Inpuower vs Frequency and Temperature SR Jun 17 74

6 ivide by: 128/129-64/65 dual modulus low power 5 FREUENCY (MHz) MIMUM PUT POWER (dbm) T A = 25 C 2.7V 3.V 6.V 35 4 SR538 Figure 6. Minimum Inpuower vs Frequency and V CC 6 85 C C I CC (ma) C V CC (V) Figure 7. Supply Current vs Supply Voltage and Temperature With No Load SR Jun 17 75

7 ivide by: 128/129-64/65 dual modulus low power j1 j.5 j2 j.2 j5 V CC = 3V T A = 25 C PUT R3 4Ω L4 6nH 3 C2.4pF R1 3Ω C1.9pF j.2 j5 9 6 EUIVALENT PUT IMPEANCE j.5 12 j2 j1 Figure 8. Typical N Package Input Impedance SR54 j1 j.5 j2 j.2 j5 V CC = 3V T A = 25 C PUT R3 2Ω L4 3nH 3 5 C2.2pF R1 3Ω C1.9pF j.2 j5 9 6 EUIVALENT PUT IMPEANCE j.5 12 j2 j1 Figure 9. Typical Package Input Impedance SR Jun 17 76