Preliminary Technical Information IXDI514 / IXDN Ampere Low-Side Ultrafast MOSFET Drivers
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1 Preliminary Technical Information IXI / IXN Ampere Low-Side Ultrafast MOSFET rivers Features Built using the advantages and compatibility of CMOS and IXYS HMOS TM processes Latch-Up Protected over entire Operating Range High Peak Output Current: A Peak Wide Operating Range:.V to V - C to + C Extended Operating Temperature High Capacitive Load rive Capability: nf in <ns Matched Rise And Fall Times Low Propagation elay Time Low Output Impedance Low Supply Current Two rivers in Single Chip Applications riving MOSFETs and IGBTs Motor Controls Line rivers Pulse Generators Local Power ON/OFF Switch Switch Mode Power Supplies (SMPS) C to C Converters Pulse Transformer river Class Switching Amplifiers Power Charge Pumps General escription The IXI and IXN are high speed high current gate drivers specifically designed to drive the largest IXYS MOSFETs & IGBTs to their minimum switching time and maximum parctical frequency limits. The IXI and IXN can source and sink Amps of Peak Current while producing voltage rise and fall times of less than ns. The inputs of the rivers are compatible with TTL or CMOS and are virtually immune to latch up over the entire operating range! Patented* design innovations eliminate cross conduction and current "shoot-through". Improved speed and drive capabilities are further enhanced by very quick & matched rise and fall times. The IXI is configured as a Inverting Gate river, and the IXN is configured as a Non-Inverting Gate river. The IXI and IXN are each available in the -Pin P- IP (PI) package, the -Pin SOIC (SIA) package, and the 6-Lead FN () package, (which occupies less than 6% of the board area of the -Pin SOIC). *United States Patent 6,97,7 Ordering Information Part Number escription Package Type Packing Style Pack Qty IXIPI A Low Side Gate river I.C. -Pin PIP Tube IXISIA A Low Side Gate river I.C. -Pin SOIC Tube 9 IXISIAT/R A Low Side Gate river I.C. -Pin SOIC Tape and Reel IXI A Low Side Gate river I.C. 6-Lead FN x Waffle Pack 6 IXIT/R A Low Side Gate river I.C. 6-Lead FN Tape and Reel IXNPI A Low Side Gate river I.C. -Pin PIP Tube IXNSIA A Low Side Gate river I.C. -Pin SOIC Tube 9 IXNSIAT/R A Low Side Gate river I.C. -Pin SOIC Tape and Reel IXN A Low Side Gate river I.C. 6-Lead FN x Waffle Pack 6 IXNT/R A Low Side Gate river I.C. 6-Lead FN Tape and Reel Configuration Inverting Non-Inverting NOTE: All parts are lead-free and RoHS Compliant Copyright 6 IXYS CORPORATION All rights reserved First Release S9967(/7)
2 IXI / IXN Figure - IXI Inverting A Gate river Functional Block iagram IN ANTI-CROSS CONUCTION CIRCUIT * P N OUT Figure - IXN A Non-Inverting Gate river Functional Block iagram IN ANTI-CROSS CONUCTION CIRCUIT * * P N OUT * United States Patent 6,97,7 Copyright 6 IXYS CORPORATION All rights reserved
3 Absolute Maximum Ratings () Operating Ratings () Parameter Value Supply Voltage V All Other Pins -. V to V CC +.V Junction Temperature C Storage Temperature -6 C to C Lead Temperature ( Sec) C IXI / IXN Parameter Value Operating Supply Voltage.V to V Operating Temperature Range - C to C Package Thermal Resistance * -Pin PIP (PI) θ J-A (typ) C/W -Pin SOIC (SIA) θ J-A (typ) C/W 6-Lead FN () θ J-A (typ) - C/W 6-Lead FN () θ J-C (max). C/W 6-Lead FN () θ J-S (typ). C/W Electrical T A = o C () Unless otherwise noted,.v V CC V. All voltage measurements with respect to. IX_ configured as described in Test Conditions. Symbol Parameter Test Conditions Min Typ Max Units V IH High input voltage.v V CC V. V V IL Low input voltage.v V CC V. V V IN Input voltage range - V CC +. V I IN Input current V V IN V CC - µa V OH High output voltage V CC -. V V OL Low output voltage. V R OH Output resistance I OUT = ma, V CC = V 6 Output high R OL Output resistance I OUT = ma, V CC = V 6 Output Low I PEAK Peak output current V CC is V A I C Continuous output Limited by package power A current dissipation t R Rise time C L =nf =V ns t F Fall time C L =nf =V ns t ONLY On-time propagation C L =nf =V 9 ns delay t OFFLY Off-time propagation C L =nf =V 9 ns delay V CC Power supply voltage. V I CC Power supply current V IN =.V V IN = V V IN = + V CC () ma µa µa IXYS reserves the right to change limits, test conditions, and dimensions.
4 IXI / IXN Electrical temperatures over - o C to o C () Unless otherwise noted,.v V CC V, Tj < o C All voltage measurements with respect to. IX_ configured as described in Test Conditions. All specifications are for one channel. Symbol Parameter Test Conditions Min Typ Max Units V IH High input voltage.v V CC V.7 V V IL Low input voltage.v V CC V. V V IN Input voltage range - V CC +. V I IN Input current V V IN V CC - µa V OH High output voltage V CC -. V V OL Low output voltage. V R OH Output resistance V CC = V. Output high R OL Output resistance V CC = V. Output Low I C Continuous output A current t R Rise time C L =,pf =V ns t F Fall time C L =,pf =V ns t ONLY On-time propagation C L =,pf =V 6 ns delay t OFFLY Off-time propagation delay C L =,pf =V 6 ns V CC Power supply voltage. V I CC Power supply current V IN =.V V IN = V V IN = + V CC () ma µa µa Notes:. Operating the device beyond the parameters listed as Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.. The device is not intended to be operated outside of the Operating Ratings.. Electrical Characteristics provided are associated with the stated Test Conditions.. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily to highlight any specific performance limits within which the device is guaranteed to function. Copyright 6 IXYS CORPORATION All rights reserved
5 IXI / IXN * The following notes are meant to define the conditions for the θ J-A, θ J-C and θ J-S values: ) The θ J-A (typ) is defined as junction to ambient. The θ J-A of the standard single die -Lead PIP and -Lead SOIC are dominated by the resistance of the package, and the IX_XX are typical. The values for these packages are natural convection values with vertical boards and the values would be lower with natural convection. For the 6-Lead FN package, the θ J-A value supposes the FN package is soldered on a PCB. The θ J-A (typ) is C/W with no special provisions on the PCB, but because the center pad provides a low thermal resistance to the die, it is easy to reduce the θ J-A by adding connected copper pads or traces on the PCB. These can reduce the θ J-A (typ) to C/W easily, and potentially even lower. The θ J-A for FN on PCB without heatsink or thermal management will vary significantly with size, construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no thermal management. ) θ J-C (max) is defined as juction to case, where case is the large pad on the back of the FN package. The θ J-C values are generally not published for the PIP and SOIC packages. The θ J-C for the FN packages are important to show the low thermal resistance from junction to the die attach pad on the back of the FN, -- and a guardband has been added to be safe. ) The θ J-S (typ) is defined as junction to heatsink, where the FN package is soldered to a thermal substrate that is mounted on a heatsink. The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily available IMS in the U.S. or Europe, and not a premium Japanese IMS. A mil dialectric with a thermal conductivity of.w/mc was assumed. The result was given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the FN package. Pin escription SYMBOL FUNCTION ESCRIPTION VCC Supply Voltage Positive power-supply voltage input. This pin provides power to the entire chip. The range for this voltage is from.v to V. IN Input Input signal-ttl or CMOS compatible. OUT Output river Output. For application purposes, this pin is connected, through a resistor, to Gate of a MOSFET/IGBT. Ground The system ground pin. Internally connected to all circuitry, this pin provides ground reference for the entire chip. This pin should be connected to a low noise analog ground plane for optimum performance. CAUTION: Follow proper ES procedures when handling and assembling this component. Figure - Characteristics Test iagram.v V uf V IX_ nf pf V IXI IXI V IXN IXN Agilent 7A Current Probe
6 IXI / IXN Figure - Timing iagrams Inverting (IXI) Timing iagram V 9% INPUT.V % V PWMIN tonly tf toffly tr VCC 9% OUTPUT % V Non-Inverting (IXN) Timing iagram V 9% INPUT.V % V PWMIN tonly tr toffly tf 9% OUTPUT % V IXYS reserves the right to change limits, test conditions, and dimensions. Copyright 6 IXYS CORPORATION All rights reserved 6
7 Typical Performance Characteristics IXI / IXN Fig. Rise Time vs. Supply Voltage Fig. 6 Fall Time vs. Supply Voltage Rise Time (ns) CL=, pf 7, pf Fall Time (ns) CL=, pf 7, pf,6 pf,6 pf 6 Fig. 7 Supply Voltage (V) Rise And Fall Times vs. Case Temperature C L = nf, V cc = V 6 Fig. Rise Time vs. Load Capacitance Supply Voltage (V) t R V V V Time (ns) t F Rise Time (ns) V V 6V Temperature ( C) Fig. 9 Fall Time vs. Load Capacitance k k k k k Fig.. Load Capacitance (pf) Max / Min Input vs. Case Temperature V CC =V C L =nf Fall Time (ns) V V V V 6VV Max / Min Input (V) Minimum Input High Maximum Input Low k k k k k Load Capacitance (pf) Temperature ( o C) 7
8 IXI / IXN Fig. Supply Current vs. Load Capacitance Fig. =V Supply Current vs. Frequency =V CL= nf Supply Current (ma) MHz MHz khz khz Supply Current (ma) nf pf pf khz Fig. k k k Load Capacitance (pf) Supply Current vs. Load Capacitance =V. Fig. Frequency (khz) Supply Current vs. Frequency =V Supply Current (ma) MHz MHz khz Supply Current (ma) CL = nf nf pf pf khz Fig. khz k k k Load Capacitance (pf) Supply Current vs. Load Capacitance =V. Fig. 6 Frequency (khz) Supply Current vs. Frequency =V Supply Current (ma) MHz MHz khz Supply Current (ma) CL= nf nf pf pf khz khz k k k Load Capacitance (pf). Frequency (khz) Copyright 6 IXYS CORPORATION All rights reserved
9 IXI / IXN Fig. 7 Propagation elay vs. Supply Voltage C L =nf V IN =V@kHz Fig. Propagation elay vs. Input Voltage C L =nf V CC =V Propagation elay (ns) t OFFLY t ONLY Propagation elay (ns) t ONLY t OFFLY 6 Supply Voltage (V) 6 Input Voltage (V) Fig. 9 Propagation elay vs. Case Temperature C L = pf, V CC = V Fig..6 Quiescent Supply Current vs. Case Temperature V CC =V V IN =V@kHz Time (ns) t ONLY t OFFLY Quiescent Supply Current (ma) Temperature ( C) Temperature ( o C) Fig. P Channel Output Current vs. Case Temperature V CC =V C L =.uf Fig. N Channel Output Current vs. Case Temperature V CC =V C L =.uf 6 7 P Channel Output Current (A) N Channel Output Current (A) Temperature ( o C) Temperature ( o C) 9
10 IXI / IXN Fig. Enable Threshold vs. Supply Voltage. Fig. High State Output Resistance vs. Supply Voltage Enable Threshold (V) 6 High State Output Resistance (Ohm) Supply Voltage (V). Supply Voltage (V) Fig. Low-State Output Resistance Fig. 6 vs. Supply Voltage Low-State Output Resistance (Ohms) Supply Voltage (V) P Channel Output Current (A) V CC vs. P Channel Output Current C L =.uf V IN =-V@kHz Fig. 7 vs. N Channel Output Current C L =.uf V IN =-V@kHz N Channel Output Current (A) 6 6 Copyright 6 IXYS CORPORATION All rights reserved
11 IXI / IXN PIN CONFIGURATIONS PIN IP (PI) PIN SOIC (SIA) PIN IP (PI) PIN SOIC (SIA) VCC IN NC I X VCC I 7 OUT 6 OUT VCC IN NC I X VCC N 7 OUT 6 OUT 6 LEA FN () (Bottom View) 6 LEA FN () (Bottom View) VCC OUT 6 I X I IN N/C VCC OUT 6 I X N IN N/C NOTE: Solder tabs on bottoms of FN packages are grounded Supply Bypassing, Grounding Practices And Output Lead inductance When designing a circuit to drive a high speed MOSFET utilizing the IX_, it is very important to observe certain design criteria in order to optimize performance of the driver. Particular attention needs to be paid to Supply Bypassing, Grounding, and minimizing the Output Lead Inductance. Say, for example, we are using the IX_ to charge a pf capacitive load from to volts in ns. Using the formula: I= V C / t, where V=V C=pF & t=ns, we can determine that to charge pf to volts in ns will take a constant current of A. (In reality, the charging current won t be constant, and will peak somewhere around A). SUPPLY BYPASSING In order for our design to turn the load on properly, the IX_ must be able to draw this A of current from the power supply in the ns. This means that there must be very low impedance between the driver and the power supply. The most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is an order of magnitude larger than the load capacitance. Usually, this would be achieved by placing two different types of bypassing capacitors, with complementary impedance curves, very close to the driver itself. (These capacitors should be carefully selected and should have low inductance, low resistance and high-pulse current-service ratings). Lead lengths may radiate at high frequency due to inductance, so care should be taken to keep the lengths of the leads between these bypass capacitors and the IX_ to an absolute minimum. GROUNING In order for the design to turn the load off properly, the IX_ must be able to drain this A of current into an adequate grounding system. There are three paths for returning current that need to be considered: Path # is between the IX_ and its load. Path # is between the IX_ and its power supply. Path # is between the IX_ and whatever logic is driving it. All three of these paths should be as low in resistance and inductance as possible, and thus as short as practical. In addition, every effort should be made to keep these three ground paths distinctly separate. Otherwise, the returning ground current from the load may develop a voltage that would have a detrimental effect on the logic line driving the IX_. OUTPUT LEA INUCTANCE Of equal importance to Supply Bypassing and Grounding are issues related to the Output Lead Inductance. Every effort should be made to keep the leads between the driver and its load as short and wide as possible. If the driver must be placed farther than (mm) from the load, then the output leads should be treated as transmission lines. In this case, a twistedpair should be considered, and the return line of each twisted pair should be placed as close as possible to the ground pin of the driver, and connected directly to the ground terminal of the load.
12 IXI / IXN PRELIMINARY TECHNICAL INFORMATION A b b b c E E e ea eb L The product presented herein is under development. The Technical Specifications offered are derived from data gathered during objective characterizations of preliminary engineering lots; but also may yet contain some information supplied during a pre-production design evaluation. IXYS reserves the right to change limits, test conditions, and dimensions without notice. E H e B A A B C E e H h L M N h X N L C M.7±. [.99±.].97±. [.±.]. [.9] S.^.; o[ S.^.;o]. [.].9 [.].9 [.9]. [.7].7 [.]. [.]. [.] IXYS Corporation Bassett St; Santa Clara, CA 9 Tel: -9-7; Fax: sales@ixys.net IXYS Semiconductor GmbH Edisonstrasse ; -66; Lampertheim Tel: ; Fax: marcom@ixys.de Copyright 6 IXYS CORPORATION All rights reserved
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