IXA531L4. Preliminary Data Sheet. 500mA 3-Phase Bridge Driver. Features. General Description. Applications. Ordering Information

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1 500mA 3-Phase Bridge Preliminary Data Sheet Features Fully operational to +650V Tolerant of negative transient voltages dv/dt immune (50V/ns) Latch-up protected over entire operating range Fault-current shutdown for all drive outputs User selectable delay or latching function for clearing of the FAULT signal, independent user controlled clearing of the FAULT signal is also available UVLO protection for all drive outputs Enable signal capable of disabling all driver outputs 3 half-bridge driver pairs (independent) 3.3V logic compatible Cross-conduction prevention logic, 220 ns - 360ns Phase leg deadtime Peak output current: Pull-up/Source, Pull-down/Sink Wide operating supply voltage range: 8.0V to 35V Capacitive load drive capability: 1250pF in < 100ns Matched, low propagation delay times Low supply current Monolithic construction Fault monitoring is accompanied by a signal indication, with programmable reset or user selectable latched protection Target package power dissipation capability is 2.0W. Full level of function available from -55 C to C Available in 48-Lead 7mm x 7mm MLP Quad package and 44-Lead PLCC package General Description The IXA531 is a monolithic, 3-phase, MOSFET/IGBT gate driver consisting of three independent, high and low side output channels. addition to the six inputs, which are CMOS/TTL Compatible, for the three corresponding high side and three low side outputs, there are dedicated lines for FAULT, ABLE and RESET. Overload/Short Circuit protection is implemented by sensing a voltage across a shunt or low value resistor which carries load current. Upon Overload/Short Circuit detection, all outputs are disabled. Likewise ABLE () pin, when LOW under abnormal operating conditions, affords soft shut down of outputs. FAULT() signal s status indicates that shut down has occurred either due to Overload/Short Circuit in driven MOSFET/IGBT or Under Voltage on V CL. Clearing of FAULT () signal and restoration of normal operation ensue automatically after a programmed delay using an RC Network wired at RST (RESET) pin. Matched propagation delays ensure proper operation even at very high switching frequencies. Absence of cross conduction in output stages removes possibility of shoot through in driven power MOSFETs or IGBTs. Applications Driving MOSFETs and IGBTs in half-bridge circuits High voltage, high side and low side drivers Motor Controls Switch Mode Power Supplies (SMPS) DC to DC Converters Class D Switching Amplifiers Ordering formation Part IXA531S10 IXA531L4 Package 48L - SSLGA 44L - PLCC Warning: The IXA531 is ESD sensitive. Copyright IXYS CORPORATION First Release DS99187A(12/05)

2 Fig. 1. Single Phase Application up to V HIN1 LIN1 HIN1 LIN1 VCH1 HGO1 HS1 IXA531 To Load RST UVSEL LGO1 DG LS LGO3 LIN2 HG02 LGO2 LIN3 HS3 HG03 HIN2 VCH2 HS2 HIN3 VCH3 Pin Description And Configuration SYMBOL FUTION DESCRIPTION HS put High side put signal, TTL or CMOS compatible; HGO1,2,3 out of phase LIN1,2,3 LS put Low side put signal, TTL or CMOS compatible; LGO1,2,3 out of phase Enable Chip enable. When driven high, both outputs go low. DG Ground Logic Reference Ground VCH1,2,3 Supply Voltage High Side Power Supply HGO1,2,3 put High side driver output HS1,2,3 Return High side voltage return Supply Voltage Low side and Logic fixed power supply. This power supply provides power for all outputs. Voltage range is from 8.0 to 35V. LGO1,2,3 put Low side driver output LS Low side return Low side driver return Fault dicates Low-Side under voltage or Over Current Trip Trip put for over current shutdown RST Delay after trip Externally connected RC network decide FAULT CLEAR delay. 2

3 GND HIN1 HIN1 LIN1 LIN1 RST DG VCH1 HGO1 HS1 UVSEL LGO1 LS up to V VCH2 VCH3 HIN2 HIN2 HIN3 HIN3 LIN2 LIN2 HGO2 LIN3 LIN3 HGO3 PH1 To Load PH2 PH3 HS2 To Load HS3 To Load LGO2 LGO3 IXA531S10 Fig Phase Application for the IXA531. 3

4 Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to LS. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions IXA531 Symbol Definition Min. Max. Units VCH High side floating supply voltage, (VCH1,2,3) V V HS High side floating supply offset voltage, (V HS1,2,3 ) VCH1,2,3-35 VCH1,2, V V HGO High side floating output voltage, (V HGO1,2,3 ) VHS1,2,3 0.3 VCH1,2, V Low side and logic fixed supply voltage V VDG Logic Supply offset voltage VLS VLS V VLGO Low side output voltage V Lower of VIN put voltage, LIN1,2,3,, RST, VDG 0.3 (VDG + 35) or V ( + 0.3) V FAULT output voltage VDG V dv/dt Allowable offset voltage slew rate lew rate 50 V/ns PD Package power dissipation@ TA +25 O C 2.0 W RthJA Thermal resistance, junction to ambient 63 K/W TJ Junction temperature 125 O C TS Storage temperature O C TL Lead temperature (soldering, 10 seconds) 300 O C Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute values referenced to LS. The VHS offset rating is tested with all supplies baised at 15V differential. Symbol Definition Min. Max. Units VCH1,2,3 High side floating supply voltage VHS1,2, VHS1,2, V V HS1,2,3 High side floating supply offset voltage V V HGO1,2,3 High side floating output voltage VHS1,2,3 VCH1,2,3 V VLGO1,2,3 Low side output voltage 0 V Low side and logic fixed supply voltage V VDG Logic Supply offset voltage V LS V LS V V FAULT output voltage VDG V VRST RST input voltage VDG V V input voltage VDG V VIN Logic input voltage, LIN1,2,3, VDG or VLS V TA Ambient temperature O C 4

5 Static Electrical Characteristics V BIAS (V CL, V CH1,2,3 ) = 15V unless otherwise specified. The V IN, V TH and I IN parameters are referenced to DG and are applicable to all six channels. The V O and I O parameters are referenced to LS and V HS1,2,3 and are applicable to the respective output leads: H GO1,2,3 and L GO1,2,3. Symbol Definition Min. Typ. Max. Units Test Conditions VINL Logic 0 input voltage ; LIN1,2,3 0.8 V VINH Logic 1 input voltage ; LIN1,2,3 3.0 V V,TH+ positve going threshold 3.0 V V,TH - negative going threshold 0.8 V V, TH+ positve going threshold V V, HYS input hysteresis.07 V VRST,TH+ RST positive going threshold 8 V VRST, HYS RST input hysteresis 3 V VOH1,2,3 High level output voltage, VCH - VHGO or - VLGO V I0=20mA VOL1,2,3 Low level output voltage, VHGO or VLGO V I0=20mA UV+ supply under-voltage positive going threshold V VCHUV+ VCH supply under-voltage positive going threshold V UV- supply under-voltage negaitive going threshold V VCHUV- VCH supply under-voltage negaitive going threshold V UVH supply under-voltage lockout hysteresis 0.2 V VCHUVH VCH supply under-voltage lockout hysteresis 0.2 V ILK Offset supply leakage current 50 μa VCH1,2,3= VHS1,2,3=600 V I QVCH Quiescent V CH supply current μa VIN=0V or 5V I Q Quiescent V CL supply current ma VIN=0V or 5V VIN put clamp voltage (HIN,LIN,,) 4.9 V IIN = 100μA ILIN+or IIN+ Logic 1 put bias current for LIN1,2, μa VLIN = 5V ILIN-or IIN- Logic 0 put bias current for LIN1,2, μa VLIN = 0V IHIN+or IIN+ Logic 1 put bias current for μa VHIN = 5V IHIN-or IIN- Logic 0 put bias current for μa VHIN = 0V I+ high input bias current μa V = 5V I- low input bias current 0 1 μa V = 0V I+ high ABLE input bias current μa V = 5V I- low ABLE input bias current 0 1 μa V = 0V IRST RST input bias current 0 1 μa VRST = 0Vor 15V IGO+ put high short circuit pulsed current 600 ma V0=0V,PW <10 μs IGO- put low short circuit pulsed current 600 ma V0=15V,PW<10μs RON, RST RST low on resistance Ω RON, low on resistance Ω 5

6 Dynamic Electrical Characteristics V CL = V CH = V BIAS = 15V, V HS1,2,3 = V DG = V LS, T A = 25 C and C L = 1000pF unless otherwise specified. Symbol Definition Min. Typ. Max. Units Test Conds. t on Turn-on propagation delay ns V IN =0V & 5V t off Turn-off propagation delay ns V IN =0V & 5V t r Turn-on rise time ns ---- t f Turn-on fall time ns ---- t ABLE low to output shutdown ns V IN, V = 0 V propagation delay or 5 V t to output shutdown propagation delay ns V =5V t bl blanking time ns V IN =0V or 5V V = 5V t to FAULT propagation delay ns V IN = 0V or 5V V = 5V t FILIN put filter time (HIN, LIN, ) ns V IN = 0V & 5V t FLCLR FAULT clear time RST=2meg, C=1nF ms V IN = 0V or 5V V =0V DT Dead time ns V IN = 0V & 5V MT Matching delay ON and OFF ns External Dead MDT Matching delay, max (t on, t off ) - min (t on, t off ) ns Time (t on,t off are applicable to all 3 channels) >400nsec PM put pulse width matching, PWMIN-PWMOUT ns VCH ABLE FAULT LGO1,2,3 HGO1,2,3 <U X X X 0(note 1) V <UVCH 0V 15V high imp LIN1,2,3 0 15V 15V 0V 15V high imp LIN1,2,3 15V 15V >V 15V 0 (note 2) V 15V 0V 0V high imp 0 0 Notes: A Cross Conduction logic prevents LGO1,2,3 and HGO1,2,3 for each channel from turning on simultaneously. 1. U is not latched, when >U, FAULT returns to high impedance. 2. When < V, FAULT returns to high-impedance after RST pin becomes greater then 8V (@= 15V). 6

7 LIN1,2,3 RST HO1,2,3 LO1,2,3 Fig. Fig. 3. (5) Timing Timing Diagram Diagram t LO1,2,3 HO1,2,3 90% Fig. 4. (6) ABLE Enable Timing Waveforms LIN1,2,3 PWMIN LIN1,2,3 t on tr PWMOUT t off t f 90% 90% HO1,2,3 LO1,2,3 10% 10% Fig. 5. Switching Time Definitions 7

8 LIN1,2,3 LIN1,2,3 LO1,2,3 HO1,2,3 DT DT Fig. Fig. 6. Deadtime (8) Deadtime Waveforms Waveforms RST V RST,th+ t OUTPUT 90% t FLCLR t Fig. Fig. 7. (9) / RST / Waveforms RST Waveforms t FILIN t FILIN HIN / LIN on off on off on off HO / LO high low Fig. 8. ABLE Timing Waveforms Fig. (10) put Filter Diagram 8

9 VCH VCH1 HIN1 LIN1 hin1 en1 lin1 5V LOGIC to CMOS Level Shift, & Anti-Cross Conduction Logic h01 io1 Low to Isolation High Rst UVCC Detect HS Isolated High Side HGO1 HS1 VCH VCH2 HIN2 LIN2 hin2 en2 lin2 5V LOGIC to CMOS Level Shift, & Anti-Cross Conduction Logic h02 io2 Low to Isolation High Rst UVCC Detect HS Isolated High Side HGO2 HS2 VCH VCH3 HIN3 LIN3 hin3 en3 lin3 5V LOGIC to CMOS Level Shift, & Anti-Cross Conduction Logic h03 io3 Low to Isolation High Rst UVCC Detect HS Isolated High Side HGO3 HS3 U OUT Detect Low to High Delay Equalizer LGO1 50K 50K V S R Set Dominant Latch QB Low to High Delay Equalizer LGO2 RST N Low to High Delay Equalizer LGO3 N 1 LS DG Fig. (9) IXA531 Block Diagram 9

10 Fig. 10. Pin Diagram for the IXA531S10 48-Lead MLP Quad Package 0.276±0.002 [7.00±0.05] 0.039±0.002 [1.00±0.05] 0.276±0.002 [7.00±0.05] 0.015±0.001 [0.38±0.03] 0.009±0.001 [0.23±0.03] 0.030±0.001 [0.75±0.03] [0.50] Fig. 11. Pin Diagram for the IXA531L4 44-Lead PLCC package LS 7 39 LIN LIN2 9 LIN VCH2 HGO IXA531S HS VCH HGO3 RST HS DG LS LGO3 LGO2 LGO1 HIN3 HIN2 HIN1 VCH1 HGO1 HS IXA531L4 10

11 Fig Lead PLCC line Diagram IXYS Corporation 3540 Bassett St; Santa Clara, CA Tel: ; Fax: IXYS Semiconductor GmbH Edisonstrasse15 ; D-68623; Lampertheim Tel: ; Fax: marcom@ixys.de 11