IXZ421DF12N100 RF Power MOSFET & DRIVER

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1 Driver / MOSFET Combination DEIC421 Driver combined with a DE37-12N12A MOSFET Gate driver matched to MOSFET Features Isolated Substrate high isolation voltage (>V) excellent thermal transfer Increased temperature and power cycling capability IXYS advanced Z-MOS process Low R DS(on) Very low insertion inductance (<2nH) No beryllium oxide (BeO) or other hazardous materials Built using the advantages and compatibility of CMOS and IXYS HDMOS processes Latch-Up Protected Low Quiescent Supply Current Advantages Optimized for RF and high speed Easy to mount no insulators needed High power density Single package reduces size and heat sink area Figure 1. Functional Diagram IXZ421DF12N1 1 Volts 12 A.9 Ohms Applications Class D or E Switching Amplifier Multi MHz Switch Mode Power Supplies (SMPS) Description The IXZ421DF12N1 is a CMOS high speed high current gate driver and a MOSFET combination specifically designed Class D, E, HF, RF applications at up to MHz, as well as other applications. The IXZ421DF12N1 in pulse mode can provide 72A of peak current while producing voltage rise and fall times of less than ns, and minimum pulse widths of 8ns. The input of the driver is fully immune to latch up over the entire operating range. Designed with small internal delays, the IXZ421DF12N1 is suitable for higher power operation where combiners are used. Its features and wide safety margin in operating voltage and power make the IXZ421DF12N1 unmatched in performance and value. The IXZ421DF12N1 is packaged in DEIs low inductance RF package incorporating DEI's RF layout techniques to minimize stray lead inductances for optimum switching performance. The IXZ421DF12N1 is a surface-mountable device. V CC Drain IN INGND Source DGND

2 Device Performance Device Specifications Parameter Value Maximum Junction Temperature 1 C Operating Temperature Range - 4 C to 8 C Weight.g IXZ421DF12N1 Symbol Test Conditions Maximum Ratings fmax ID =.IDM MHz VDSS 1V VCC, VCCIN 2V IDSS VDS =.8VDSS TJ = C ua VGS = V TJ = 1C 1mA IDM TC = C 12A IDM TC = C, Pulse limited by TJM 72A IAR TC = C 12A PT (MOSFET and Driver) TC = C TBD W RthJC RthJHS. C/W.4 C/W Symbol Test Condition Minimum Typical Maximum Rds(ON) V CC = 1V, I D =.I DM Pulse Test, t µs, Duty Cycle 2%.92 Ω VCC 8V 1V 2V IN (Signal Input) - V VCC +.3V VIH (High Input Voltage) 3.V VIL (Low Input Voltage).8V ZIN f = 1MHz 1248-j1 Ω Cstray COSS f = 1MHz Any one pin to the back plane metal VGS = V, VDS =.8VDSS(max), f =1MHz 46pf 1pf tondly T C = C V CC, V CCIN, V IN = 1V 1µS Pulse, toffdly V DS = V, R L = 2.Ω tr T C = C V CC, V CCIN, V IN = 1V 1µS Pulse, tf V DS = V, R L = 2.Ω 32nS ns 4nS 3nS

3 Fig. 2 Fig. 3 Output Characteristics ID (A) V V DS (V) 1V to 2V 7.V 8V 9V ID (A) Transfer Characteristics, V DS = 6V Fig. 4 Fig. Transfer Characteristics vs. Junction Temperature ID (A) V DS = V, P.W. = 1µS 1-4 C V GS (V) C Fig. 6 Fig. 7 Normalized R DS(ON) vs. Junction Temperature V CC = 1V,, PW = 1µS RDS(ON) Ohms R DS(ON) vs. V CC Supply Voltage, Propagation ON Delay vs. V CC Supply Voltage RDS(ON) Normalized Propagation ON Time (ns) C C - 4 C Temperature ( C)

4 Fig. 8 Propagation OFF Delay vs. V CC Supply Voltage Fig. 9 Propragation Delay vs. Temperature V CC = 1V, Propagation OFF Time (ns) C C 8 Propagation Time (ns) 4 4 Toff Ton Case Temperature ( C) Fig. 1 Rise Time vs. V CC Supply Voltage Fig. 11 Fall Time vs. V CC Supply Voltage C Rise Time (ns) C Fall Time (ns) C - 4 C Fig. 12 Fig. 13 Rise and Fall Time vs. Temperature Time (ns) V CC = 1V, t R t F Case Temperature ( C) Capacitance (pf) V DS vs. Output Capacitance VDS Voltage (V)

5 Lead Description SYMBOL FUNCTION DESCRIPTION Drain MOSFET Drain Drain of Power MOSFET. Source VCC Source of Power MOSFET. This connection is common to DGND. MOSFET Source Driver Section Supply Voltage IN Input Input signal. DGND Power Driver Ground Power supply input for the logic input and driver output sections. The system ground leads. Internally connected to all circuitry, these leads provide ground reference for the entire chip. These leads should be connected to a low noise analog ground plane for optimum performance. Figure 14 Package Drawing

6 Figure 1 Test Circuit *Choke A Common Mode Choke is optional and can be used to help stabilize threshold levels due to ground bounce and minimize false triggering. C BULK - Bulk capacitance helps to stabilize both Vds for the drain Drain circuit and Vcc for the Driver circuit. Actual values vary according to load and operating conditions. For the driver section, Tantalum capacitors are recommended for their low ESR and fast energy delivery. C BYPASS - Ideally, the benefits realized through bypass capacitance increase as more is used with overlapping impedance curves, lowering the overall broadband impedance to ground. Typically a range of.1uf,.1uf,.1uf capacitors in sufficient quantities give good results. Circuit and PCB layout should be carefully considered for optimized operation. Each of the Vcc pins on the driver section should be treated as its own supply pin as it applies to bulk and bypass capacitance considerations. Likewise, the source pins of the MOSFET are connected symmetrically to the MOSFET and the ground return path for bulk and bypass capacitance should also be noted in the layout. Excessive parasitic inductance can result in V = L di/dt drops causing unstable operation. IXYS RF reserves the right to change limits, test conditions and dimensions without notice. IXYS RF MOSFETS are covered by one or more of the following U.S. patents: 4,8,92 4,86,72 4,881,16 4,891,686 4,931,844,17,8,34,796,49,961,63,7,187,117,237,481,486,71,381,,64,4 6,44,6 6,83, 6,71,463 6,727,8 6,731,2

7 Fig. 16 IXZ421DF12N1 Package Outline REV 9/1 21 IXYS RF An IXYS Company 241 Research Blvd., Suite 18 Fort Collins, CO USA Fax: Web: