IXZ4DF18N50 RF Power MOSFET & DRIVER

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1 Driver / MOSFET Combination DEIC-55 Driver combined with IXZ38N50 MOSFET Gate driver matched to MOSFET Features Isolated substrate high isolation voltage (>500V) excellent thermal transfer Increased temperature and power cycling capability IXYS advanced Z-MOS process Low R ds(on) Very low insertion inductance(<nh) No beryllium oxide (BeO) or other hazardous materials Built using the advantages and compatibility of CMOS and IXYS HDMOS processes Latch-up protected Low quiescent supply current Advantages Optimized for RF and high speed Easy to mount no insulators needed High power density Single package reduces size and heat sink area IXZ4DF8N50 Applications 500 Volts 9 A 0.9 Ohms Class D or E Switching Amplifier Multi MHz Switch Mode Power Supplies (SMPS) Description The IXZ4DF8N50 is a CMOS high speed high current gate driver and ZMOS MOSFET combination specifically designed Class D and E HF RF applications at up to 40MHz, as well as other applications. The IXZ4DF8N50 in pulse mode can provide 95A of peak current while producing voltage rise and fall times of less than 4ns, and minimum pulse widths of 8ns. The input of the driver is fully immune to latch up over the entire operating range. Designed with small internal delays, the IXZ4DF8N50 is suitable for higher power operation where combiners are used. Its features and wide safety margin in operating voltage and power make the IXZ4DF8N50 unmatched in performance and value. The IXZ4DF8N50 is packaged in DEI's low inductance RF package incorporating DEI's RF layout techniques to minimize stray lead inductances for optimum switching performance. The IXZ4DF8N50 is a surfacemountable device. Figure. Functional Diagram

2 Device Specifications Parameter Value Maximum Junction Temperature 50 C Operating Temperature Range - 40 C to 85 C Weight 5.5g Device Performance IXZ4DF8N50 Symbol Test Conditions Maximum Ratings fmax ID = 0.5IDM5 40MHz VDSS 500V, IN 0V IDSS VDS = 0.8VDSS TJ = 5C 50uA VGS = 0V TJ = 5C ma IDM5 TC = 5 C 9A IDM TC = 5 C, Pulse limited by TJM 95A IAR TC = 5 C 9A PT (MOSFET and Driver) TC = 5 C 500 W RthJC RthJHS 0.5 C/W TBD C/W Symbol Test Condition Minimum Typical Maximum Rds(ON) V CC = 5 V, I D = 0.5I DM5 Pulse Test, t 300µS, Duty Cycle % 0.9 Ω, IN 8V 5V 0V IN (Signal Input) - 5V IN0.3V VIH (High Input Voltage) V CCIN -V IN0.3V VIL (Low Input Voltage) 0.8V ZIN f = MHz 7960 Ω Cstray COSS f = MHz Any one pin to the back plane metal V GS = 0V, V DS = 0.8V DSS (max), f =MHz 46pf 39pf tondly T C = 5 C V CC, V CCIN, V IN = 5V, µs Pulse, V DS = 50V, R L = 5.0Ω toffdly tr T C = 5 C V CC, V CCIN, V IN = 5V,µS Pulse, V DS = 50V, R L = 5.0Ω tf 7 ns 6 ns 3 ns 3 ns

3 Fig. Fig. 3 I D (A) Extended Output 5 C V DS (V) V GS = 0V V GS = 5V V GS = 8V RDS(ON) Ω R DS(ON) vs. Temperature Fig Propagation Delay ON vs. Supply Voltage Fig Propagation Delay OFF vs. Supply Voltage Fig. 6 Propagation Delay ON vs. Temperature Fig. 7, V CC / V CCIN / IN = 5V Propagation Delay OFF vs. Temperature, V CC / V CCIN / IN =5V

4 Fig. 8 4 Rise Time vs. Supply Voltage Fig. 9 Fall Time vs. Supply Voltage Fig. Rise Time vs. Temperature Fig., V CC / V CCIN / IN = 5V 3 3 Fall Time vs. Temperature, V CC / V CCIN / IN = 5V Fig. O u tp u t C a p a cita n ce vs. V D S Vo lta g e Fig Capacitance (pf) 00 0 C O SS Current (A) 0. V CC Supply Current vs. Frequency Driver Section 0V 5V 8V V D S (V) Frequency (MHz)

5 Fig. 4 V CCIN Supply Current vs. Frequency Driver Section V CCIN Current (A) V 5V 8V Frequency (MHz) Test Circuit Fig u 0.0u 0.0u 0.0u 0.47u 0.47u VDD UF 0V DGND Source IN IN L CM Choke 0.0u 0.0u 0.0u 0.0u IN INGND DGND Drain Source 5 ohm 0W.0uF 0.47u 0.47u Place all capacitors on as close to the lead as possible

6 Lead Description SYMBOL FUNCTION DESCRIPTION Drain MOSFET Drain Drain of Power MOSFET. Source IN Source of Power MOSFET. This connection is common to DGND. MOSFET Source Driver Section Supply Voltage Input Section Supply Voltage IN Input Input signal. DGND INGND Power Driver Ground Input Section Ground Power supply input for the driver output section. These leads provide power to the output section of the DEIC55 driver. Both leads must be connected. Input for the positive input section power-supply voltage. This lead provide power to the input section of the DEIC55 driver. This lead should not be directly connected to. The system ground leads. Internally connected to all circuitry, these leads provide ground reference for the entire chip. These leads should be connected to a low noise analog ground plane for optimum performance. The input section ground lead. This lead is a Kelvin connection internally connected to DGND. This lead must not be connected to DGND as excessive current can damage this lead. IXYS RF reserves the right to change limits, test conditions and dimensions without notice. IXYS RF MOSFETS are covered by one or more of the following U.S. patents: 4,835,59 4,860,07 4,88,6 4,89,686 4,93,844 5,07,508 5,034,796 5,049,96 5,063,307 5,87,7 5,37,48 5,486,75 5,38,05 5,640,045 6,404,065 6,583,505 6,7,463 6,77,585 6,73,00

7 Fig. 6 IXZ4DF8N50 Package Outline IXYS RF An IXYS Company 40 Research Blvd. Ste. 8, Ft. Collins, CO 8056 Tel: ; Fax: deiinfo@directedenergy.com